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Product List
In order for SPI devices to communicate, they must be configured to operate in the same manner. Since the master device drives the clock signal it will be placing valid data on the MOSI pin and expecting valid data on the MISO pin according to the configured parameters of the clock with respect to the rising and falling edges. In the first SCK example above, it can be seen that the data is valid on the rising edge of the clock and the data is then changed to a new value on the falling edge. The slave device must latch the data from the MOSI line on the rising edge. These settings are configured through the CKPOL for the polarity and CKPHA for the phase. CKPHA should be set to 0 on the master when communicating with the Silicon Labs CP240x devices.
PTM Published on: 2011-05-13
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