Blinking a display requires setting a fixed time interval and toggling the segment outputs of the associated blinked segments. Typically, this was done with CPU overhead to set a time base and then using firmware to toggle the segment ON and OFF. That method has the disadvantage of requiring CPU overhead and increasing power consumption. The LCD controller in Silicon Labs devices provides the capability to blink segments via hardware greatly reducing the system power consumption. The rate at which segments blink is a function of the refresh rate and is set using the LCD0TOGR register. The equation for the toggle (blink) rate is shown above and is set using the lower 4 bits of the toggle register. The number of segments that can be blinked is dependent on the mode used. There is only one memory location that is used to set which segments blink, ULPMEM00, which represents at most 8 segments. Therefore, when in static mode two segments can blink since there are only two segments referenced to COM0 in ULPMEM00, bit 0 and bit 4. When using the 4 mux mode all bits in ULPMEM00 represent a segment so a total of 8 segments can be blinked. The LCD0BLINK register provides a mask to set the segments in the LCD0 and LCD1 ULP memory area that will blink. If a LCD0BLINK bit is set then the segment will blink at the rate specified in the TOGR bits.