The power modes above are achieved by disabling specific primary functions of the CP240x. The figure on this page, shows how power is distributed throughout the CP240x. Additional secondary functions may also be disabled to save power. Normal mode should be used whenever the host controller is communicating with the CP240x. In this mode, the device is fully functional and the host interface is capable of operating at full speed. In RAM Preservation Mode, the internal oscillator is disabled and the SmaRTClock oscillator provides the system clock. RAM Preservation Mode should be used when the CP240x needs to be active for a prolonged period of time in which communication with the host microcontroller is not required. In Ultra Low Power LCD Mode, the on-chip LDO is placed in a low power state and power is gated off from all digital logic residing outside the ULP block. The ULP block allows the device to refresh an LCD, maintain a real time clock, detect SmaRTClock Alarm, SmaRTClock Oscillator Fail, and ULP Port Match events. In Ultra Low Power SmaRTClock Mode, the on-chip LDO is placed in a low power state and power is gated off from all digital logic residing outside the ULP block and LCD functionality is disabled. The ULP block allows the device to maintain a real time clock and detect SmaRTClock Alarm, SmaRTClock Oscillator Fail, and ULP Port Match events. Shutdown mode is the lowest power mode for the CP240x. All device functionality is disabled in this mode and a reset is required to wake up the device. This mode is typically used when the device is not needed for prolonged periods of time.