This page shows an illustration of an I²C bus. Essentially, it is a multi-master bus with an underlying protocol. The data direction outlined above is based on the bus cycle and master device. Once a master gets control of the bus then all other devices become slaves as there can be only one master. I²C is based on peripheral addresses. A master addresses the peripheral device and provides the cycle type, whether it is a read or write. For a write operation, the master sends data on the bus for the slave device to accept. For a read, the slave takes over the bus and drives the data. The master always drives the clock on the bus. I²C also provides a level of error checking. It communicates with an ACK/NACK protocol. If the master or slave did not receive the data correctly or for some reason cannot accept the data it can NACK the transfer. All of the ACK and NACK signals are based on bit timing and are generated in the 9th bit position. The start and stop bits are also based on timing. These bits are defined by the state at the point of transition of the I²C clock. The legend shows which device controls the bus and therefore data direction.