The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. As previously seen in the multi-layer bus matrix discussion, this controller has an AHB bus master interface. The AHB master interface transfers display data from a selected slave (memory) to the LCD controller DMA FIFOs. It can also be configured to obtain data from on-chip SRAM, various types of off-chip static memory, or off-chip SDRAM. The LCD controller has dual, 16-deep programmable, 64-bit wide FIFOs for buffering incoming display data. There is also hardware cursor support, which reduces software overhead associated with maintaining a cursor image in the LCD frame buffer. Additionally, the controller has a 256 entry, 16-bit palette RAM arranged as 128x32-bit RAM and supports little and big-endian along with Windows CE data formats.