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Zero ASIC
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Tutorial: Constructing the Parallella aluminum case
Parallella: a Smart(er)TV
Parallella Introduction
Zero ASICについて
Zero ASICは、マサチューセッツ州ケンブリッジに本社を置く非上場の半導体デバイス企業です。同社は、エンドユーザー向けアプリケーションを対象とした世界初の自動受注生産型システムインパッケージの設計・製造プラットフォームを開発しています。同社の画期的なチップレットアプローチは、ASIC開発のコストと時間を大幅に改善し、エネルギー制約のある幅広い高性能システムのカスタムIC導入のハードルを取り除きます。
関連コンテンツ
ADDITIONAL LINKS
ANALYST REPORTS
- 451 Research Analysts Predicts Accelerators For Future
- Adapteva Believes High-Performance Computing is Ready for an Epiphany
- Adapteva Demos 100Gflops
- Adapteva Included in Gartner Report on Market Trends
- Adapteva: More Flops, Less Watts
- Adapteva’s Epiphany Floating Point Processor Core: A Leading-Edge Lithography May Finally Open Doors
- Epiphany Included in Guide to CPU Cores and Processor IP from Linley Group
- Processors that can do 20 GFLOPS/W
EPIPHANY RESOURCES
PARRALLELLA COMMUNITY FORUM
PARRALLELLA RESOURCES
PRODUCT TRAINING PRESENTATIONS
- A 1024-core 70GFLOP/W Floating Point Manycore Microprocessor
- A 1024-core 70GFLOPS/W Floating Point Manycore Microprocessor
- A 25 GFLOP/W Software Programmable Floating Point Accelerator
- A Manycore Coprocessor Architecture for Heterogeneous Computing
- A Scalable Processor Architecture for the Next Generation of Low Power Supercomputer
- A Sub 2 W 64-Core 100 GFLOPS Accelerator Programmable in C/C++ or OpenCL
- An Alternative to GPU Acceleration For Mobile Platforms (Updated) (GF@DAC-2013)
- An Introduction to the Epiphany Manycore Architecture
- Hybrid System Design: The Only Practical Way
- Improving Engineering Efficiency Through Tiled Hierarchical Flows
- Keynote: Kickstarting the Transition to Parallel Computing With Open Hardware
- Keynote: Presenting the Parallella (MIT ARMFEST-2013)
- Keynote: There’s STILL Plenty of Room at the Bottom!
- Parallella: A Love Story
- Peaceful Coexistence Between Architectures
- The Future of HPC: Task-Parallel, Heterogeneous, Efficient, Open
- The Good, the Bad, the Ugly of Semiconductor Crowd Funding
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