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LM5113
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5113
SNVS725I JUNE 2011REVISED OCTOBER 2019
LM5113 80-V, 1.2-A, 5-A, Half Bridge GaN Driver
1
1 Features
1 Independent high-side and low-side
TTL logic inputs
1.2 A / 5 A peak source/sink current
High-side floating bias voltage rail
Operates up to 100 VDC
Internal bootstrap supply voltage clamping
Split outputs for adjustable
turnon/turnoff strength
• 0.6-/ 2.1-pulldown/pullup resistance
Fast propagation times (28 ns typical)
Excellent propagation delay matching
(1.5 ns typical)
Supply rail undervoltage lockout
Low power consumption
2 Applications
Merchant telecom rectifiers
Merchant DC/DC
Closed loop stepper motor drive
Baseband unit (BBU)
Macro remote radio unit (RRU)
3 Description
The LM5113 device is designed to drive both the
high-side and the low-side enhancement mode
Gallium Nitride (GaN) FETs in a synchronous buck or
a half bridge configuration. The floating high-side
driver is capable of driving a high-side enhancement
mode GaN FET operating up to 100 V. The high-side
bias voltage is generated using a bootstrap technique
and is internally clamped at 5.2 V, which prevents the
gate voltage from exceeding the maximum gate-
source voltage rating of enhancement mode GaN
FETs. The inputs of the LM5113 are TTL logic
compatible, and can withstand input voltages up to 14
V regardless of the VDD voltage. The LM5113 has
split gate outputs, providing flexibility to adjust the
turnon and turnoff strength independently.
The LMG1205 is an enhancement over the LM5113.
The LMG1205 takes the design of the LM5113 and
includes start-up logic, level shifter, and power-off
Vgs clamp enhancements to provide a more robust
solution.
In addition, the strong sink capability of the LM5113
maintains the gate in the low state, preventing
unintended turnon during switching. The LM5113 can
operate up to several MHz. The LM5113 is available
in a standard WSON-10 pin package and a 12-bump
DSBGA package. The WSON-10 pin package
contains an exposed pad to aid power dissipation.
The DSBGA package offers a compact footprint and
minimized package inductance.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM5113 WSON (10) 4.00 mm × 4.00 mm
DSBGA (12) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics .......................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
7 Detailed Description............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram....................................... 11
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 13
8 Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application ................................................. 14
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 20
11 Device and Documentation Support ................. 21
11.1 Documentation Support ........................................ 21
11.2 Support Resources ............................................... 21
11.3 Trademarks........................................................... 21
11.4 Electrostatic Discharge Caution............................ 21
11.5 Glossary................................................................ 21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (January 2018) to Revision I Page
Removed "NRND" from data sheet title.................................................................................................................................. 1
Removed NRND disclosure statement .................................................................................................................................. 1
Changes from Revision G (January 2016) to Revision H Page
Changed data sheet title from: LM5113 100 V 1.2-A / 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN
FETs to: LM5113 80-V, 1.2-A, 5-A, Half Bridge GaN Driver.................................................................................................. 1
Added Not Recommended for New Designs statement to the data sheet............................................................................. 1
Added content to the Description section .............................................................................................................................. 1
Changed the first page key graphic ....................................................................................................................................... 1
Removed HB to VDD parameter from the Absolute Maximum Ratings table........................................................................ 5
Changed the HS to VSS maximum from: 100 V to: 93 V....................................................................................................... 5
Changed the HB to VSS maximum from: 107 V to: V(HS) + 7 V........................................................................................... 5
Changed the human-body model value from: ±2000 to: ±1000............................................................................................. 5
Changed HS maximum from: 100 V to: 90 V ........................................................................................................................ 5
Changed the Functional Block Diagram............................................................................................................................... 11
Changed the last paragraph and add new images to the Input and Output section ........................................................... 11
Added content to the Start-up and UVLO section ............................................................................................................... 12
Changes from Revision F (April 2013) to Revision G Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.................................................................................................. 1
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Changes from Revision E (April 2013) to Revision F Page
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
*9 TEXAS INSTRUMENTS
VDD LI
HI
VDD
HSHBHOHHOL
HS
LOH
LOL VSS
A
B
C
D
1 2 3 4
Thermal Pad
VDD 1
HB
HOH
HOL
LOH10
LOL
VSS
LI
HS HI
2 9
3 8
4 7
5 6
4
LM5113
SNVS725I JUNE 2011REVISED OCTOBER 2019
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5 Pin Configuration and Functions
DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View
YFX Package
12-Pin DSBGA
Top View
(1) I = Input, O = Output, G = Ground, P = Power
(2) A3 and C4, C1 and D4 are internally connected
Pin Functions
PIN TYPE (1) DESCRIPTION
NAME WSON DSBGA
VDD 1 A3, C4(2) P5-V Positive gate drive supply: locally decouple to VSS using low ESR/ESL capacitor
located as close to the IC as possible.
HB 2 D3 P High-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor
to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close
to the IC as possible.
HOH 3 D2 O High-side gate driver turnon output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnon speed.
HOL 4 D1 O High-side gate driver turnoff output: connect to the gate of high-side GaN FET with a short,
low inductance path. A gate resistor can be used to adjust the turnoff speed.
HS 5 C1, D4(2) PHigh-side GaN FET source connection: connect to the bootstrap capacitor negative
terminal and the source of the high-side GaN FET.
HI 6 B4 I High-side driver control input. The LM5113 inputs have TTL type thresholds. Unused
inputs should be tied to ground and not left open.
LI 7 A4 I Low-side driver control input. The LM5113 inputs have TTL type thresholds. Unused inputs
should be tied to ground and not left open.
VSS 8 A2 G Ground return: all signals are referenced to this ground.
LOL 9 A1 O Low-side gate driver sink-current output: connect to the gate of the low-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnoff speed.
LOH 10 B1 O Low-side gate driver source-current output: connect to the gate of high-side GaN FET with
a short, low inductance path. A gate resistor can be used to adjust the turnon speed.
Exposed
Pad EP Exposed pad: TI recommends that the exposed pad on the bottom of the package be
soldered to ground plane on the printed-circuit board to aid thermal dissipation.
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD to VSS –0.3 7 V
HB to HS –0.3 7 V
LI or HI input –0.3 15 V
LOH, LOL output –0.3 VDD + 0.3 V
HOH, HOL output VHS – 0.3 VHB +0.3 V
HS to VSS –5 93 V
HB to VSS 0 VHS + 7 V
Operating junction temperature 150 °C
Storage temperature, Tstg –55 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD 4.5 5.5 V
LI or HI input 0 14 V
HS –5 90 V
HB VHS + 4 VHS + 5.5 V
HS slew rate 50 V/ns
Operating junction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
LM5113
UNITDPR (WSON) YFX (DSBGA)
10 PINS 12 PINS
RθJA Junction-to-ambient thermal resistance 37.5 76.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35.8 0.6 °C/W
RθJB Junction-to-board thermal resistance 14.7 12.0 °C/W
ψJT Junction-to-top characterization parameter 0.3 1.6 °C/W
ψJB Junction-to-board characterization parameter 14.9 12.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.1 °C/W
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(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
6.5 Electrical Characteristics
Specifications are TJ= 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IDD VDD quiescent current LI = HI = 0 V TJ= 25°C 0.07 mA
TJ= –40°C to 125°C 0.1
IDDO VDD operating current f = 500 kHz TJ= 25°C 2.0 mA
TJ= –40°C to 125°C 3.0
IHB Total HB quiescent current LI = HI = 0 V TJ= 25°C 0.08 mA
TJ= –40°C to 125°C 0.1
IHBO Total HB operating current f = 500 kHz TJ= 25°C 1.5 mA
TJ= –40°C to 125°C 2.5
IHBS HB to VSS quiescent current HS = HB = 100 V TJ= 25°C 0.1 µA
TJ= –40°C to 125°C 8
IHBSO HB to VSS operating current f = 500 kHz TJ= 25°C 0.4 mA
TJ= –40°C to 125°C 1.0
INPUT PINS
VIR Input voltage threshold Rising edge TJ= 25°C 2.06 V
TJ= –40°C to 125°C 1.89 2.18
VIF Input voltage threshold Falling edge TJ= 25°C 1.66 V
TJ= –40°C to 125°C 1.48 1.76
VIHYS Input voltage hysteresis 400 mV
RIInput pulldown resistance TJ= 25°C 200 k
TJ= –40°C to 125°C 100 300
UNDERVOLTAGE PROTECTION
VDDR VDD rising threshold TJ= 25°C 3.8 V
TJ= –40°C to 125°C 3.2 4.5
VDDH VDD threshold hysteresis 0.2 V
VHBR HB rising threshold TJ= 25°C 3.2 V
TJ= –40°C to 125°C 2.5 3.9
VHBH HB threshold hysteresis 0.2 V
BOOTSTRAP DIODE
VDL Low-current forward voltage IVDD-HB = 100 µA TJ= 25°C 0.45 V
TJ= –40°C to 125°C 0.65
VDH High-current forward voltage IVDD-HB = 100 mA TJ= 25°C 0.90 V
TJ= –40°C to 125°C 1.00
RDDynamic resistance IVDD-HB = 100 mA TJ= 25°C 1.85
TJ= –40°C to 125°C 3.60
HB-HS clamp Regulation voltage TJ= 25°C 5.2 V
TJ= –40°C to 125°C 4.7 5.45
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Electrical Characteristics (continued)
Specifications are TJ= 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V.
No load on LOL and HOL or HOH and HOL(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOW- AND HIGH-SIDE GATE DRIVER
VOL Low-level output voltage IHOL = ILOL = 100 mA TJ= 25°C 0.06 V
TJ= –40°C to 125°C 0.10
VOH
High-level output voltage
VOH = VDD – LOH
or VOH = HB – HOH IHOH = ILOH = 100 mA TJ= 25°C 0.21 V
TJ= –40°C to 125°C 0.31
IOHL Peak source current HOH, LOH = 0 V 1.2 A
IOLL Peak sink current HOL, LOL = 5 V 5 A
IOHLK High-level output leakage current HOH, LOH = 0 V TJ= –40°C to 125°C 1.5 µA
IOLLK Low-level output leakage current HOL, LOL = 5 V TJ= –40°C to 125°C 1.5 µA
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tLPHL LO turnoff propagation delay LI falling to LOL falling TJ= 25°C 26.5 ns
TJ= –40°C to 125°C 45.0
tLPLH LO turnon propagation delay LI rising to LOH rising TJ= 25°C 28.0 ns
TJ= –40°C to 125°C 45.0
tHPHL HO turnoff propagation delay HI falling to HOL falling TJ= 25°C 26.5 ns
TJ= –40°C to 125°C 45.0
tHPLH HO turnon propagation delay HI rising to HOH rising TJ= 25°C 28.0 ns
TJ= –40°C to 125°C 45.0
tMON Delay matching
LO on & HO off
TJ= 25°C 1.5 ns
TJ= –40°C to 125°C 8.0
tMOFF Delay matching
LO off & HO on
TJ= 25°C 1.5 ns
TJ= –40°C to 125°C 8.0
tHRC HO rise time (0.5 V – 4.5 V) CL= 1000 pF 7.0 ns
tLRC LO rise time (0.5 V – 4.5 V) CL= 1000 pF 7.0 ns
tHFC HO fall time (0.5 V – 4.5 V) CL= 1000 pF 1.5 ns
tLFC LO fall time (0.5 V – 4.5 V) CL= 1000 pF 1.5 ns
tPW Minimum input pulse width
that changes the output 10 ns
tBS Bootstrap diode
reverse recovery time IF= 100 mA, IR= 100 mA 40 ns
l TEXAS CURRENT (HA) "‘2‘ ‘2. § 10‘ 10° 101 102 103 10‘ FREQUENCY (kHz) CURRENT (M) Q o 0: Q 10‘ INSTRUMENTS * + + , + + f 1.4 6 1.2 5 A 1.0 A s s 4 E o e E \ w 8 0.6 \ g 0.4 2 0.2 1 0.0 D 0 1 2 3 4 5 0 2 3 4 5 HOH. LOH (V) HOL, LOL (V) 105 105 10a 1 0‘ 1 02 1 03 FREQUENCY (kHz) 10‘
LI
HI
tHPLH
tLPLH
tHPHL
tLPHL
LO
HO
LI
HI
tMOFF
tMON
LO
HO
8
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Figure 1. Timing Diagram
6.7 Typical Characteristics
Figure 2. Peak Source Current vs Output Voltage Figure 3. Peak Sink Current vs Output Voltage
Figure 4. IDDO vs Frequency Figure 5. IHBO vs Frequency
l TEXAS INSTRUMENTS so so 75 35 70 so 2 2 a 55 3 75 .— .— 5 so 5 70 n: n: 5 E o 55 o 55 so so 45 55 40 so .50 .25 u 25 51) 75 1110125150 .50 .25 u 25 51) 75 1110125150 TEMPERATURE (no) TEMPERATURE (no) 2 E n 3'9 n _. _. O O I I (n (n m m n: K E E '50 .25 u 25 50 75 100125150 '—50 .25 u 25 so 75 100125150 TEMPERATURE (no) TEMPERATURE (ca) 0.50 2.1 V'R 2.0 0.45 E S \ a 1.9 a \\ m \ g 1.8 E 0.40 E '5 1.7 E E 1.6 0.35 1.5 1.4 0.30 .50 .25 u 25 so 75 100125150 50 .25 o 25 5o 75 100125150 TEMPERATURE (co) TEMPERATURE (vC)
9
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Typical Characteristics (continued)
Figure 6. IDD vs Temperature Figure 7. IHB vs Temperature
Figure 8. UVLO Rising Thresholds vs Temperature Figure 9. UVLO Falling Thresholds vs Temperature
Figure 10. Input Thresholds vs Temperature Figure 11. Input Threshold Hysteresis vs Temperature
l TEXAS INSTRUMENTS IO" 40 35 / 104 a T PLH / / A 5 30 ' < :2="" 3="" e="" 25="" t_f-'hl="" j="" 10="" 20="" 104="" 15="" 0.1="" 0.2="" 0.3="" 0.4="" 05="" 0.6="" 0.7="" 0.0="" 0.9="" 10="" .50="" .25="" 0="" 25="" 50="" 75="" 100="" 125="" 150="" vd(v)="" temperature="" (="0)" 0.50="" 5.5="" 0.25="" 5.4="" von="" s="" 0.20="" s="" 2="" d="" 1%="" 5.3="" 2="" 0.15="" j="">'3 8 52 0.10 V E \\ m , ” 0'05 ’- 5.1 0.00 50 ,50 -25 D 25 50 75 100125150 TEMPERATURE (9C) '—5o .25 0 25 50 75 100125150 TEMPERATURE (ca)
10
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Typical Characteristics (continued)
Figure 12. Bootstrap Diode Forward Voltage Figure 13. Propagation Delay vs Temperature
Note: Unless otherwise specified,
VDD = VHB = 5 V, VSS = VHS = 0 V.
Figure 14. LO & HO Gate Drive – High/Low Level
Output Voltage vs Temperature
Note: Unless otherwise specified,
VDD = VHB = 5 V, VSS = VHS = 0 V.
Figure 15. HB Regulation Voltage vs Temperature
l TEXAS INSTRUMENTS J7 HOH “E y V /\ Lonff 1 4E
LOH
UVLO
HOH
LEVEL
SHIFT
HB
HS
VDD
VSS
HI
LI
HOL
LOL
UVLO
& CLAMP
Copyright © 2017, Texas Instruments Incorporated
EXT HI
EXT LI
11
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7 Detailed Description
7.1 Overview
The LM5113 is a high frequency high- and low- side gate driver for enhancement mode Gallium Nitride (GaN)
FETs in a synchronous buck or a half bridge configuration. The floating high-side driver is capable of driving a
high-side enhancement mode GaN FET operating up to 100 V. The high-side bias voltage is generated using a
bootstrap technique and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding the
maximum gate-source voltage rating of enhancement mode GaN FETs. The LM5113 has split gate outputs with
strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently.
The LM5113 can operate up to several MHz, and available in a standard WSON-10 pin package and a 12-bump
DSBGA package. The WSON-10 pin package contains an exposed pad to aid power dissipation. The DSBGA
package offers a compact footprint and minimized package inductance.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Input and Output
The inputs are independently controlled with TTL input thresholds, and can withstand voltages up to 14 V
regardless of the VDD voltage, which means it could be directly connected to the outputs of PWM controllers
with up to 14-V power supply, saving a buffer stage between output of higher-voltage powered controller, for
example LM5025 with 10 V, and input of the LM5113.
The output pulldown and pullup resistance of LM5113 is optimized for enhancement mode GaN FETs to achieve
high frequency and efficient operation. The 0.6-Ωpulldown resistance provides a robust low impedance turnoff
path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ωpullup resistance
helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LM5113 offer
flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either the
turnon path, the turnoff path, or both.
l TEXAS INSTRUMENTS E I F l sN74chzGazva
100 k
50 pF
SN74LVC2G32YZP
HI
EXT HI
Copyright © 2017, Texas Instruments Incorporated
HI
1 k
22 pF
EXT HI
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Feature Description (continued)
It is very important that the input signal of the two channels HI and LI, which has logic compatible threshold and
hysteresis, must be tied to either VDD or VSS if they are not used. This inputs must not be left floating.
Additionally, the input signals avoid pulses shorter than 3 ns by using the input filter to the HI and LI input pins.
The values and part numbers of the circuit components are shown in the Figure 16.
Figure 16. Input Filter 1 (High-Side Input Filter)
If short pulses or short delays are required, the circuit in Figure 17 is recommended.
Figure 17. Input Filter 1 for Short Pulses (High-Side Input Filter)
7.3.2 Start-Up and UVLO
The start-up voltage sequencing for this device is as follows: VDD voltage first, with the VIN voltage present
thereafter.
The LM5113 requires an external bootstrap diode with a 20-series resistor to charge the high-side supply on a
cycle-by-cycle basis. The recommended bootstrap diode options are BAT46, BAT41, or LL4148.
The LM5113 has an Undervoltage Lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD
voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs
from being partially turned on. Also if there is insufficient VDD voltage, the UVLO will actively pull the LOL and
HOL low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only HOL is pulled low.
Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.
Table 1. VDD UVLO Feature Logic Operation
CONDITION (VHB-HS > VHBR for all cases below) HI LI HO LO
VDD - VSS < VDDR during device start-up H L L L
VDD - VSS < VDDR during device start-up L H L L
VDD - VSS < VDDR during device start-up H H L L
VDD - VSS < VDDR during device start-up L L L L
VDD - VSS < VDDR - VDDH after device start-up H L L L
VDD - VSS < VDDR - VDDH after device start-up L H L L
VDD - VSS < VDDR - VDDH after device start-up H H L L
VDD - VSS < VDDR - VDDH after device start-up L L L L
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Table 2. VHB-HS UVLO Feature Logic Operation
CONDITION (VDD > VDDR for all cases below) HI LI HO LO
VHB-HS < VHBR during device start-up H L L L
VHB-HS < VHBR during device start-up L H L H
VHB-HS < VHBR during device start-up H H L H
VHB-HS < VHBR during device start-up L L L L
VHB-HS < VHBR - VHBH after device start-up H L L L
VHB-HS < VHBR - VHBH after device start-up L H L H
VHB-HS < VHBR - VHBH after device start-up H H L H
VHB-HS < VHBR - VHBH after device start-up L L L L
7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
Due to the intrinsic feature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch, is
usually higher than a diode forward voltage drop when the gate is pulled low. This will cause negative voltage on
HS pin. Moreover, this negative voltage transient will be even worse, considering layout and device drain/source
parasitic inductances. With high side driver using the floating bootstrap configuration, Negative HS voltage can
lead to an excessive bootstrap voltage which can damage the high-side GaN FET. The LM5113 solves this
problem with an internal clamping circuit that prevents the bootstrap voltage from exceeding 5.2 V typical.
7.3.4 Level Shift
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and
provides excellent delay matching with the low-side driver. Typical delay matching between LO and HO is around
1.5 ns.
7.4 Device Functional Modes
Table 3 shows the device truth table.
Table 3. Truth Table
HI LI HOH HOL LOH LOL
L L Open L Open L
L H Open L H Open
H L H Open Open L
H H H Open H Open
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a
powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor.
Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the
switching devices. With the advent of digital power, this situation is often encountered because the PWM signal
from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shift
circuit is required to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting
capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also
find other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current
driver IC physically close to the power switch), driving gate-drive transformers and controlling floating power-
device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses
from the controller into the driver.
The LM5113 is a MHz high- and low-side gate driver for enhancement mode Gallium Nitride (GaN) FETs in a
synchronous buck or a half bridge configuration. The floating high-side driver is capable of driving a high-side
enhancement mode GaN FET operating up to 100 V. The high-side bias voltage is generated using a bootstrap
technique and is internally clamped at 5.2 V, which prevents the gate voltage from exceeding the maximum gate-
source voltage rating of enhancement mode GaN FETs. The LM5113 has split gate outputs with strong sink
capability, providing flexibility to adjust the turnon and turnoff strength independently.
8.2 Typical Application
The circuit in Figure 18 shows a synchronous buck converter to evaluate LM5113. Detailed synchronous buck
converter specifications are listed in Design Requirements. The active clamping voltage mode controller LM5025
is used for close-loop control and generates the PWM signals of the buck switch and the synchronous switch.
For more information, refer to the Related Documentation section.
l TEXAS INSTRUMENTS
2.2 F2.2 F2.2 F2.2 F
2.2 F2.2 F
VIN
J3
C2 C3 C4 C5 C6 C7
VIN
J1
TP4
+
+
-
GND
GND GND
GND
GND
GND
OUT
IN
ON/OFF BYP
C18
0.1 F
C19
1 F
R7
33.2k
C17
NU
R4
±1%
49.9
U1 LP2982AIM5-5.0 5V
5
4
C20
100 pF
C21
2.2 F
2
C24
1 F
6.3V
C25
0.1 F
GND
D3
NU
R11
0R
D4
GND
U3
HB HS
VDD HOH
HI HOL
LOH
LOLVSS
LI
25
3
4
10
9
8
7
6
1
EP
LM5113
GND
NU
R14
0R
C27
NU
C28
NU
R15
4.02k
¬
¬
¬
¬
¬
¬
¬
¬
¬
¬
R18
COMPSYNC
RT
TIME
REF
VCC
AGND
PGND
OUTBSS
RAMP OUTA
UVLO CS2
CS1
VIN
U4
16
1
2
12
15
14
6
3
4
8
9
13
5
11
10
7
LM5025
C30
0.01 FC31
0.1 F
R17
7.50k C32
1 F
GND
GND
0
D5
D6 MBR130T1G
1N4148W-7-F
R19
21.0k
GND
GND
R16
21.0k
C29
1 F
GND
U2
LM8261M5
C26
1 F
C23
1500 pF
C22
330 pF
R8
16.9k
2
4
1
5
3
R5
374
C15
1.5 nF
R6
21.0k
R1
10.0
C1
330 FC12
22 F
C10
22 F
C11
1 F
C14
1 uF
C13
NU
SER1360-272KL
2.7 H
L1
1
23
5
7
9
11
4
6
8
10
Q2
EPC2001
D2
MBR130T1G
GND
GND
GND
J4
VOUT
10V
J2
VOUT TP2
TP5
11 10
9
7
5
3
8
6
4
2
Q1
EPC2001
1
C9
0.01 uF
C8
0.1 uF
TP3
TP1
EX VCC GND
D1
MBR130T1G
R2
100k
±1%
R3
150k
C16
220 pF
R13
6.98k
R9
2R
R10
0R
¬
1
3
15
LM5113
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Typical Application (continued)
Input 15 V to 60 V, output 10 V, 800 kHz
Figure 18. Application Circuit
l TEXAS INSTRUMENTS quan a" CW AV Qgfi ‘HSX‘OVI+QN C531) AV P = ICmaH + Cam} X Véu X fsw P=( 0w QgL)vaDxf,w
16
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Typical Application (continued)
8.2.1 Design Requirements
Table 4 lists the design requirements for the typical application.
Table 4. Design Parameters
PARAMETER SPECIFICATION
Input operating range 15 – 60 V
Output voltage 10 V
Output current, 48-V input 10 A
Output current, 60-V input 7 A
Efficiency at 48 V, 10 A >90%
Frequency 800 kHz
8.2.2 Detailed Design Procedure
This procedure outlines the design considerations of LM5113 in a synchronous buck converter with enhancement
mode Gallium Nitride (GaN) FET. Refer to Figure 18 for component names and network locations. For additional
design help, see Related Documentation.
8.2.2.1 VDD Bypass Capacitor
The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 1.
(1)
QgH and QgL are gate charge of the high-side and low-side transistors respectively. Qrr is the reverse recovery
charge of the bootstrap diode, which is typically around 4 nC. ΔV is the maximum allowable voltage drop across
the bypass capacitor. A 0.1-µF or larger value, good-quality, ceramic capacitor is recommended. The bypass
capacitor should be placed as close to the pins of the IC as possible to minimize the parasitic inductance.
8.2.2.2 Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side switch, DC bias power for HB undervoltage
lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be
calculated with Equation 2.
(2)
IHB is the quiescent current of the high-side driver. ton is the maximum on-time period of the high-side transistor.
A good-quality, ceramic capacitor should be used for the bootstrap capacitor. TI recommends placing the
bootstrap capacitor as close to the HB and HS pins as possible.
8.2.2.3 Power Dissipation
The power consumption of the driver is an important measure that determines the maximum achievable
operating frequency of the driver. It should be kept below the maximum power dissipation limit of the package at
the operating temperature. The total power dissipation of the LM5113 is the sum of the gate driver losses and the
bootstrap diode power loss.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as:
(3)
CLoadH and CLoadL are the high-side and the low-side capacitive loads, respectively. It can also be calculated with
the total input gate charge of the high-side and the low-side transistors as:
(4)
l TEXAS INSTRUMENTS POWER (W) 0.1 001 0001 0.0001 10 100 1000 FREQUENCY (kHz) 10000 POWER (w) 01 mm 0001 a 0001 10 100 1000 FREQUENCY mm 10000 POWER AW) 10 a 001 0001 10 100 1000 FREQUENCY (kHz) 10000
(TJ - TA)
TJA
P =
17
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There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equations. This plot can be used to
approximate the power losses due to the gate drivers.
Gate Driver Power Dissipation (LO+HO), VDD = +5 V
Figure 19. Neglecting Bootstrap Diode Losses
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Larger
capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input
voltages (VIN) to the half bridge also result in higher reverse recovery losses.
The following two plots illustrate the forward bias power loss and the reverse bias power loss of the bootstrap
diode respectively. The plots are generated based on calculations and lab measurements of the diode reverse
time and current under several operating conditions. The plots can be used to predict the bootstrap diode power
loss under different operating conditions.
The Load of High-Side Driver is a GaN FET with Total Gate Charge
of 10 nC. Figure 20. Forward Bias Power Loss of
Bootstrap Diode VIN = 50 V
The Load of High-Side Driver is a GaN FET with Total Gate Charge
of 10 nC. Figure 21. Reverse Recovery Power Loss of
Bootstrap Diode VIN = 50 V
The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as Equation 5.
(5)
l TEXAS INSTRUMENTS
18
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8.2.3 Application Curves
Conditions:
Input Voltage = 48 V DC, Load Current = 5 A
Traces:
Top Trace: Gate of Low-Side eGaN FET, Volt/div = 2 V
Bottom Trace: LI of LM5113, Volt/div = 5 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 0.2 µs/div
Figure 22. Low-Side Driver Input and Output
Conditions:
Input Voltage = 48 V DC,
Load Current = 10 A
Traces:
Trace: Switch-Node Voltage, Volts/div = 20 V
Bandwidth Limit = 600 MHz
Horizontal Resolution = 50 ns/div
Figure 23. Switch-Node Voltage
9 Power Supply Recommendations
The recommended bias supply voltage range for LM5113 is from 4.5 V to 5.5 V. The lower end of this range is
governed by the internal undervoltage lockout (UVLO) protection feature of the VDD supply circuit. The upper
end of this range is driven by the 7-V absolute maximum voltage rating of the VDD or the GaN transistor gate
breakdown voltage limit, whichever is lower. TI recommends keeping a proper margin to allow for transient
voltage spikes.
The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in
normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage
drop do not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification,
the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on the auxiliary
power supply output should be smaller than the hysteresis specification of LM5113 to avoid triggering device
shutdown.
A local bypass capacitor should be placed between the VDD and VSS pins. And this capacitor should be located
as close to the device as possible. A low-ESR, ceramic surface mount capacitor is recommended. TI
recommends using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high
frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220-nF to 10-
μF, for IC bias requirements.
l TEXAS INSTRUMENTS
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10 Layout
10.1 Layout Guidelines
Small gate capacitance and miller capacitance enable enhancement mode GaN FETs to operate with fast
switching speed. The induced high dv/dt and di/dt, coupled with a low gate threshold voltage and limited
headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum
performance. Following are some hints.
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and
discharge the GaN FETs gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs should be placed close to the
driver.
2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass
capacitor and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the
bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval
and involves high peak current. Minimizing this loop length and area on the circuit board is important to
ensure reliable operation.
3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose
excessive negative voltage transients on the driver. TI recommends connecting the HS pin and VSS pin to
the respective source of the high-side and low-side transistors with a short and low-inductance path.
4. The parasitic source inductance, along with the gate capacitor and the driver pulldown path, can form a LCR
resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp
the ringing.
5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak current being drawn from VDD during turnon of the FETs. Keeping
bullet #1 (minimized GaN FETs gate driver loop) as the first priority, it is also desirable to place the VDD
decoupling capacitor and the HB to HS bootstrap capacitor on the same side of the printed-circuit board as
the driver. The inductance of vias can impose excessive ringing on the IC pins.
6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing low-
ESR ceramic capacitors adjacent to the GaN FETs.
The following figures show recommended layout patterns for WSON-10 package and DSBGA package,
respectively. Two cases are considered: (1) Without any gate resistors; (2) With an optional turnon gate resistor.
It should be noted that 0402 DSBGA package is assumed for the passive components in the drawings. For
information on DSBGA package assembly, refer to Related Documentation.
spacer
l TEXAS INSTRUMENTS Eumsllap Bnmslvap 0000 O O O O 0000 ammo GND Boalslmp 0000 O O O O 0000 c [I
A
B
C
D
1
To Hi-Side FET
HO
To Low-Side FET
LO
GNDBypass
Capacitor
Bootstrap
Capacitor
34
HS
2
VDD
LI
HI
VDD
HS HB HOH HOL
LOH
LOL
VSS
HS
A
B
C
D
1
2
To Hi-Side FET
HO
To Low-Side FET
LO
GND
Bypass
Capacitor
Bootstrap
Capacitor
HS
34
VDD
LI
HI
VDD
HS HB HOH HOL
LOH
LOL
VSS
HS
To Low-Side FET
HI
LI
VSS
LOH
LOL
9
10
To Hi-Side FET
LO
GND
HS
6
7
8
1
2
5
VDD
HB
Bypass
Capacitor
4
HS
Bootstrap
Capacitor HO
HOH
HOL
3
To Low-Side FET
HI
LI
VSS
LOH
LOL
9
10
To Hi-Side FET
LO
GND
HO
HS
6
7
8
1
2
3
4
5
VDD
HB
Bootstrap
Capacitor
Bypass
Capacitor
HS
20
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10.2 Layout Examples
Figure 24. WSON-10 Without Gate Resistors Figure 25. WSON-10 With HOH
and LOH Gate Resistors
Figure 26. DSBGA Without Gate Resistors Figure 27. DSBGA With HOH
and LOH Gate Resistors
l TEXAS INSTRUMENTS Am
21
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Texas Instruments, AN-1112 DSBGA Wafer Level Chip Scale Package Application Report
Texas Instruments, AN-2149 LM5113 Evaluation Board Application Report
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5113SD/NOPB NRND WSON DPR 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5113
LM5113SDE/NOPB NRND WSON DPR 10 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5113
LM5113SDX/NOPB NRND WSON DPR 10 4500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 L5113
LM5113TME/NOPB NRND DSBGA YFX 12 250 RoHS & Green SNAGCU Level-1-260C-UNLIM 5113
LM5113TMX/NOPB NRND DSBGA YFX 12 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM 5113
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5113 :
Automotive: LM5113-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
l TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension designed to accommodate the component tengtn K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pitch between SucCeSSWe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D D SprocketHotes ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5113SD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5113SDE/NOPB WSON DPR 10 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5113SDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5113TME/NOPB DSBGA YFX 12 250 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1
LM5113TMX/NOPB DSBGA YFX 12 3000 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
l TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5113SD/NOPB WSON DPR 10 1000 208.0 191.0 35.0
LM5113SDE/NOPB WSON DPR 10 250 208.0 191.0 35.0
LM5113SDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5113TME/NOPB DSBGA YFX 12 250 208.0 191.0 35.0
LM5113TMX/NOPB DSBGA YFX 12 3000 208.0 191.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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PACKAGE OUTLINE
C
10X 0.35
0.25
3 0.1
2.6 0.1
0.8
0.7
8X 0.8
10X 0.5
0.3
(0.1) TYP
2X
3.2
0.05
0.00
B4.1
3.9 A
4.1
3.9
(0.2)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
56
10
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
SEE ALTERNATIVE
LEAD DETAIL
11
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 3.000
20.000
FULL R
ALTERNATIVE LEAD
DETAIL
BOTTOM VIEW SIDE VIEW
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EXAMPLE BOARD LAYOUT
(R0.05) TYP
8X (0.8)
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(2.6)
(3.8)
10X (0.3)
10X (0.6)
(3)
( 0.2) VIA
TYP
(1.25)
(1.05)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
SYMM
1
56
10
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
11
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED
METAL
METAL
EDGE
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED
METAL
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EXAMPLE STENCIL DESIGN
10X (0.3)
10X (0.6)
8X (0.8)
4X
(1.31)
4X (1.15)
(0.76)
(3.8)
(R0.05) TYP
(0.68)
WSON - 0.8 mm max heightDPR0010A
PLASTIC SMALL OUTLINE - NO LEAD
4218856/B 01/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
77% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
SYMM
1
56
10
SYMM
METAL
TYP
11
m Mn 1 DIMENSIONS ARE IN MILUMEI'ERS ansm: m‘ m mum“ Au LAND PAntRN RECOMMENDATION [w mmuzm r ,/ mu ccwch Law A; awn ' TEXAS INSTRUMENTS
MECHANICAL DATA
YFX0012xxx
www.ti.com
TMP12XXX (Rev A)
TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215094/A 12/12
0.600
±0.075
D
E
D: Max =
E: Max =
1.905 mm, Min =
1.756 mm, Min =
1.845 mm
1.695 mm
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