Microchip Technologyが提供するPIC10F220,222 Programming Specのデータシート

Q ‘MICROCHIP PIC10F220/222 [Hi PS/MCLR D‘i Mi j‘i MCLR MM T
© 2007 Microchip Technology Inc. DS41266C-page 1
PIC10F220/222
This document includes the
programming specifications for the
following devices:
•PIC10F220
•PIC10F222
1.0 PROGRAMMING THE
PIC10F220/222
The PIC10F220/222 is programmed using a serial
method. The Serial mode will allow the PIC10F220/222
to be programmed while in the user’s system. This
allows for increased design flexibility. This programming
specification applies to PIC10F220/222 devices in all
packages.
1.1 Hardware Requirements
The PIC10F220/222 requires one power supply for
VDD (5.0V) and one for VPP (12V).
1.2 Program/Verify Mode
The Program/Verify mode for the PIC10F220/222
allows programming of user program memory for user
ID locations, backup OSCCAL location and the
Configuration Word.
Pin Diagrams
TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
Pin Name
During Programming
Function Pin Type Pin Description
GP1 ICSPCLK I Clock input – Schmitt Trigger input
GP0 ICSPDAT I/O Data input/output – Schmitt Trigger input
MCLR/VPP Program/Verify mode P Programming Power
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
PIC10F22X
1
2
3
6
5
4
GP0/AN0/ICSPDAT
VSS
GP1/AN1/ICSPCLK
GP3/MCLR/VPP
VDD
GP2/T0CKI/FOSC4
6-Lead SOT-23
GP2/T0CKI/FOSC4
N/C
N/C
8-Lead DIP
PIC10F22X
1
2
3
4
8
7
6
5
VDD
GP3/MCLR/VPP
VSS
GP0/AN0/ICSPDAT
GP1/AN1/ICSPCLK
Memory Programming Specification
PIC10F220/222
DS41266C-page 2 © 2007 Microchip Technology Inc.
2.0 MEMORY MAPPING
2.1 User Program Memory Map
The user memory space extends from (0x000-0x0FF)
on the PIC10F220 and (0x000-0x1FF) on the
PIC10F222. In Program/Verify mode, the program
memory space extends from (0x000-0x1FF) for the
PIC10F220 and (0x000-0x3FF) for the PIC10F222.
The first half, (0x000-0x0FF) and (0x000-0x1FF),
respectively, is user program memory. The second half,
(0x100-0x1FF) and (0x200-0x3FF), respectively, is
configuration memory. In Program/Verify mode the PC
will increment from (0x000-0x0FF) and (0x000-0x1FF)
respectively, then to 0x100 and 0x200, respectively
(not to 0x000).
In the configuration memory space, 0x100-0x13F for
the PIC10F220 and 0x200-0x23F for the PIC10F222
are physically implemented. However, only locations
0x100-0x103 and 0x200-0x203 are available. Other
locations are reserved.
2.2 User ID Locations
A user may store identification (ID) information in four
user ID locations. The user ID locations are mapped in
[0x100:0x103] and [0x200:0x203], respectively. It is
recommended that the user use only the four Least
Significant bits (LSb) of each user ID location and
program the upper 8 bits as ‘1’s. The user ID locations
read out normally, even after code protection is
enabled. It is recommended that user ID location is
written as ‘1111 1111 bbbb’ where ‘bbbb’ is user
ID information.
2.3 Configuration Word
The Configuration Word register is physically located at
0x1FF and 0x3FF, respectively. It is only available upon
Program mode entry. Once an Increment Address
command is issued, the Configuration Word is no
longer accessible, regardless of the address of the
program counter.
FIGURE 2-1: PIC10F220 PROGRAM
MEMORY MAP
FIGURE 2-2: PIC10F222 PROGRAM
MEMORY MAP
2.4 Oscillator Calibration Bits
The oscillator Calibration bits are stored at the Reset
vector as the operand of a MOVLW instruction. Program-
ming interfaces must allow users to program the
Calibration bits themselves for custom trimming of the
INTOSC. Capability for programming the Calibration
bits when programming the entire memory array must
also be maintained for backwards compatibility.
2.5 Backup OSCCAL Value
The backup OSCCAL value, 0x104/0x204, is a factory
reserved location where the OSCCAL value is stored
during testing of the INTOSC. This location is not
erased during a standard Bulk Erase, but is erased if
the PC is moved into configuration memory prior to
invoking a Bulk Erase. If this value is erased, it is the
user’s responsibility to rewrite it back to this location for
future use.
Note: By convention, the Configuration Word
register is stored at the logical address
location of 0xFFF within the hex file gener-
ated for the PIC10F220/222. This logical
address location may not reflect the actual
physical address for the part itself. It is the
responsibility of the programming software
to retrieve the Configuration Word data
from the logical address within the hex file
and translate the address to the proper
physical location when programming.
User Memory
Space
000h
Reset Vector 0FFh
On-chip
User
Program
Memory
User ID Locations
Reserved
Configuration Word
100h-
103h
104h
1FEh
1FFh
13Fh
140h
Unimplemented
0FEh
Backup OSCCAL value
105h
Config Memory
Space
00Fh
010h
User Memory
Space
000h
1FFh
Reset Vector
0FFh
100h
On-chip
User
Program
Memory
User ID Locations
Reserved
Configuration Word
200h
203h
204h
3FEh
3FFh
23Fh
240h
Unimplemented
1FEh
Backup OSCCAL value
205h
Config Memory
Space
MCLR
© 2007 Microchip Technology Inc. DS41266C-page 3
PIC10F220/222
3.0 COMMANDS AND
ALGORITHMS
3.1 Program/Verify Mode
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising VDD pin from
VIL to VDD. Then raise VPP from VIL to VIHH. Once in
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger inputs in
this mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at VIL). This means
that all I/O are in the Reset state (high-impedance
inputs).
3.1.1 PROGRAMMING
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x1FF for the PIC10F220 and 0x3FF for the
PIC10F222. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1: ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
3.1.2 SERIAL PROGRAM/VERIFY
OPERATION
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (TSET1)
and hold (THLD1) times with respect to the falling edge
of the clock (see Table 6-1).
Commands that do not have data associated with them
are required to wait a minimum of TDLY2, measured
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 6-1).
Commands that do have data associated with them
(Read and Load) are also required to wait TDLY2
between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don't care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
During Read commands, in which the data is output
from the PIC10F22X, the ICSPDAT pin transitions from
the high-impedance input state to the low-impedance
output state at the rising edge of the second data clock
(first clock edge after the Start cycle). The ICSPDAT pin
returns to the high-impedance state at the rising edge
of the 16th data clock (first edge of the Stop cycle). See
Figure 3-4.
The commands that are available are described in
Table 3-1.
FIGURE 3-2: PROGRAM/VERIFY MODE
EXIT
VPP
THLD0
ICSPDAT
ICSPCLK
VDD
TPPDP
Note: After every End Programming command,
a delay of TDIS is required.
VPP
ICSPDAT
ICSPCLK
VDD
THLD0
PIC10F220/222
DS41266C-page 4 © 2007 Microchip Technology Inc.
TABLE 3-1: COMMAND MAPPING FOR PIC10F220/222
3.1.2.1 Load Data For Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-3.
FIGURE 3-3: LOAD DATA COMMAND (PROGRAM/VERIFY)
3.1.2.2 Read Data From Program Memory
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘0’s.
If the program memory is code-protected (CP = 0),
portions of the program memory will be read as zeros.
See Section 5.0 “Code Protection” for details.
FIGURE 3-4: READ DATA FROM PROGRAM MEMORY COMMAND
Command Mapping (MSb … LSb) Data
Load Data for Program Memory xx00100, data (14), 0
Read Data from Program Memory xx01000, data (14), 0
Increment Address xx0110
Begin Programming xx1000Externally Timed
End Programming xx1110
Bulk Erase Program Memory xx1001Internally Timed
TDLY21514133216543
THLD1
1
TSET1
21
ICSPCLK
0
ICSPDAT 00
TDLY1
xx strt_bit stp_bit
TSET1
-+THLD1
16
MSb xx
LSb
TDLY1
TSET1
THLD1
TDLY2
12 3 4 56
010xx
12 3 13141516
TDLY3
Input Output Input
strt_bit stp_bit
LSb
MSb
0
ICSPCLK
ICSPDAT
b—u ‘ \ x x \ \4—M
© 2007 Microchip Technology Inc. DS41266C-page 5
PIC10F220/222
3.1.2.3 Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-5.
It is not possible to decrement the address counter. To
reset this counter, the user must either exit and re-enter
Program/Verify mode or increment the PC from 0x1FF
for the PIC10F220 or 0x3FF for the PIC10F222 to
0x000.
FIGURE 3-5: INCREMENT ADDRESS COMMAND
3.1.2.4 Begin Programming (Externally
Timed)
A Load command must be given before every Begin
Programming command. Programming will begin after
this command is received and decoded. Programming
requires (TPROG) time and is terminated using an End
Programming command. This command programs the
current location, no erase is performed.
FIGURE 3-6: BEGIN PROGRAMMING (EXTERNALLY TIMED)
TSET1
THLD1
TDLY2
12 3 4 56
011 xx
12
0
Next Command
ICSPCLK
ICSPDAT
ICSPCLK
ICSPDAT
TSET1THLD1
TPROG
1234 56
000 x
12
0
1
End Programming Command
x1
PIC10F220/222
DS41266C-page 6 © 2007 Microchip Technology Inc.
3.1.2.5 End Programming
The End Programming command terminates the
program process. A delay of TDIS (see Table 6-1) is
required before the next command to allow the internal
programming voltage to discharge (see Figure 3-7).
FIGURE 3-7: END PROGRAMMING (EXTERNALLY TIMED)
3.1.2.6 Bulk Erase Program Memory
After this command is performed, the entire program
memory and Configuration Word is erased.
To perform a Bulk Erase of the program memory and
configuration fuses, the following sequence must be
performed (see Figure 3-13).
1. Read and save 0x0FF/0x1FF oscillator Calibra-
tion bits and 0x104/0x204 backup OSCCAL bits
into computer/programmer temporary memory.
2. Enter Program/Verify mode. PC is set to
Configuration Word address.
3. Perform a Bulk Erase Program Memory
command.
4. Wait TERA to complete Bulk Erase.
5. Restore OSCCAL bits.
To perform a full device Bulk Erase of the program
memory, configuration fuses, user IDs and backup
OSCCAL value, the following sequence must be
performed (see Figure 3-14).
1. Read and save 0x0FF/0x1FF oscillator Calibra-
tion bits and 0x104/0x204 backup OSCCAL bits
into computer/programmer temporary memory.
2. Enter Program/Verify mode.
3. Increment PC to 0x200/0x400 (first user ID
location).
4. Perform a Bulk Erase command.
5. Wait T
ERA to complete Bulk Erase.
6. Restore OSCCAL bits.
7. Restore backup OSCCAL bits.
ICSPCLK
ICSPDAT
TSET1THLD1
1234 56
011 x
12
1
Next Command
x
TDIS
Note 1: A fully erased part will read ‘1’s in every
program memory location.
2: The oscillator Calibration bits are erased
if a Bulk Erase is invoked. They must be
read and saved prior to erasing the
device and restored during the program-
ming operation. Oscillator Calibration bits
are stored at the Reset vector as the
operand of a MOVLW instruction.
© 2007 Microchip Technology Inc. DS41266C-page 7
PIC10F220/222
TABLE 3-2: BULK ERASE RESULTS
FIGURE 3-8: BULK ERASE PROGRAM MEMORY COMMAND
PC =
Program Memory Space Configuration Memory Space
Program Memory Reset Vector Configuration
Word User ID Backup
OSCCAL
Configuration Word or
Program Memory Space EEEUU
First User ID Location E E E E E
TERA
12 3 4 56 12
Next Command
11x
00 x
ICSPCLK
ICSPDAT
TSET1
THLD1
C7 PC : ‘7 DxOFF/Ox! FF" J
PIC10F220/222
DS41266C-page 8 © 2007 Microchip Technology Inc.
FIGURE 3-9: READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS
Start
Done
Enter Programming
Mode
PC =
PC =
Address
Increment
Read Calibration
Bits and Save in
Computer/Programmer
Temp. Memory
Address
Increment
Read Backup OSCCAL
and Save in
Computer/Programmer
Temp. Memory
Calibration Bits
Exit Programming Mode
Yes
No
No
Yes
0x0FF/0x1FF?
0x104/0x204?
F PC = ‘7 UX1U4/OX2047 l Ves
© 2007 Microchip Technology Inc. DS41266C-page 9
PIC10F220/222
FIGURE 3-10: RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS
Start
Done
Enter Programming
Mode
PC =
PC =
Address
Increment
Read Calibration
Bits from
Computer/Programmer
Temp. Memory
Address
Increment
Read Backup OSCCAL
Computer/Programmer
Temp. Memory
Calibration Bits from
Exit Programming Mode
Write Calibration Bits
back as the operand
Yes
No
Yes
No
Write Backup OSCCAL
Bits back to 0x104/0x204
0x0FF/0x1FF?
0x104/0x204?
of a MOVLW instruction
to 0x0FF/0x1FF
$ § (m
PIC10F220/222
DS41266C-page 10 © 2007 Microchip Technology Inc.
FIGURE 3-11: PROGRAM FLOWCHART – PIC10F220/222 PROGRAM MEMORY
Start
Program Cycle
Read Data
Program Memory
Data Correct?
Report
Programming
Failure
Done
Wait TDIS
PROGRAM CYCLE
No
No
Increment
Address
Command
from
Bulk Erase
Device
Program
Configuration
Load Data
for
Program Memory
Yes
Begin
Programming
Wait TPROG
Command
(Externally timed)
End
Programming
One-Word
Yes
Memory
(Figure 3-12)
Increment
Address
Enter Programing
Mode
PC = 0x1FF/0x3FF
Exit Programming
Mode
(Config Word)
Read and save
OSCCAL bits
Restore OSCCAL bits
All Programming
Locations
Done?
(Figure 3-10)
(Figure 3-9)
E:
© 2007 Microchip Technology Inc. DS41266C-page 11
PIC10F220/222
FIGURE 3-12: PROGRAM FLOWCHART – PIC10F220/222 CONFIGURATION MEMORY
Start
Read Data Command
Data Report
Programming
Failure
Address =
0x100/0x200
One-Word
Programming
Cycle Read Data Command
Data Report
Programming
Failure
Yes
No
Yes
No
Increment
Address
Command
No
Done
(see Figure 3-11)
One-Word
Programming
Cycle
(see Figure 3-11)
Enter Programming
Mode
Load Data Command
Correct?
Load Data
Command
Increment Address
Command
Correct?
Address =
0x104/0x204?
Yes
Programs Configuration Word
Yes
Programs User ID’s
No
PC = 0x1FF/0x3FF
(Config Word)
Exit Programming Mode
Yes
Q
PIC10F220/222
DS41266C-page 12 © 2007 Microchip Technology Inc.
FIGURE 3-13: PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION WORD
FIGURE 3-14: PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION WORD
AND USER ID
Start
Done
Wait TERA
Bulk Erase Device
Enter
Program/Verify mode
PC = 0x1FF/0x3FF
(Config Word)
Read and save
OSCCAL bits
Restore OSCCAL bits
(Figure 3-9)
(Figure 3-10)
Exit Programming Mode
Start
Done
Bulk Erase Device
PC = 0x100/0x200?
Restore OSCCAL Bits
Yes
Increment
PC
No
Enter
Program/Verify mode
PC = 0x1FF/
0x
3FF
(Config Word)
(First User ID)
Read and save
OSCCAL bits
Wait TERA
(Figure 3-9)
(Figure 3-10)
Exit Programming Mode
© 2007 Microchip Technology Inc. DS41266C-page 13
PIC10F220/222
4.0 CONFIGURATION WORD
The PIC10F220/222 has several Configuration bits.
These bits can be programmed (reads ‘0’) or left
unchanged (reads ‘1’), to select various device
configurations.
REGISTER 4-1: CONFIGURATION WORD PIC10F220/222
— — — — — MCLRE CP WDTE MCPU IOFSCS
bit 11 bit 0
bit 11-5 Unimplemented: Read as1
bit 4 MCLRE: Master Clear Enable bit
1 =RB3/MCLR
pin functions as MCLR
0 =RB3/MCLR pin functions as RB3, MCLR internally tied to VDD
bit 3 CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1 MCPU: Master Clear Pull-up Enable bit
1 =MCPU
disabled
0 =MCPU
enabled
bit 0 IOFSCS: Internal Oscillator Frequency Select bit
1 = 8 MHz
0 = 4 MHz
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC10F220/222
DS41266C-page 14 © 2007 Microchip Technology Inc.
5.0 CODE PROTECTION
For the PIC10F220/222, once code protection is
enabled, all program memory locations 0x040-0x0FE
(PIC10F220) and 0x040-x1FE (PIC10F222) inclusive,
read all0’s. Program memory locations 0x000-0x03F,
0x0FF (PIC10F220) and 0x1FF PIC10F222) are
always unprotected. The user ID locations, backup
OSCCAL locations and the Configuration Word read
out in an unprotected fashion. It is possible to program
the user ID locations, backup OSCCAL locations and
the Configuration Word after code-protect is enabled.
5.1 Disabling Code Protection
It is recommended that the following procedure be
performed before any other programming is attempted.
It is also possible to turn code protection off (CP = 1)
using this procedure. However, all data within the
program memory will be erased when this
procedure is executed, and thus, the security of the
code is not compromised.
To disable code-protect:
a) Enter Program mode.
b) Execute Bulk Erase Program Memory
command (001001).
c) Wait TERA.
5.2 Embedding Configuration Word
and User ID Information in the
Hex File
5.3 Checksum Computation
5.3.1 CHECKSUM
Checksum is calculated by reading the contents of
the PIC10F220/222 memory locations and adding up
the opcodes up to the maximum user addressable
location (e.g., 0x1FF for the PIC10F222). Any Carry
bits exceeding 16 bits are neglected. Finally, the
Configuration Word (appropriately masked) is added
to the checksum. Checksum computation for the
PIC10F220/222 is shown in Table 5-2.
The checksum is calculated by summing the following:
The contents of all program memory locations
The Configuration Word, appropriately masked
Masked user ID locations (when applicable)
The Least Significant 16 bits of this sum is the
checksum.
The following table describes how to calculate the
checksum for each device.
Note: To allow portability of code, the program-
mer is required to read the Configuration
Word and user ID locations from the hex
file when loading the hex file. If Configura-
tion Word information was not present in
the hex file, then a simple warning
message may be issued. Similarly, while
saving a hex file, the Configuration Word
and user ID information must be included.
An option to not include this information
may be provided.
Microchip Technology Incorporated feels
strongly that this feature is important for
the benefit of the end customer.
Note: The checksum calculation differs depend-
ing on the code-protect setting. The
Configuration Word and user ID locations
can always be read regardless of the
code-protect settings.
© 2007 Microchip Technology Inc. DS41266C-page 15
PIC10F220/222
TABLE 5-1: CHECKSUM COMPUTATIONS – PIC10F220
TABLE 5-2: CHECKSUM COMPUTATIONS – PIC10F222
Device Code-Protect Checksum* Blank
Value
0x723 at 0
and Max
Address
PIC10F220 OFF SUM[0x000:0x0FE] + CFGW & 0x01F 0xEF20 0xDD68
ON SUM[0x00:0x3F] + CFGW & 0x01F + SUM_ID(1) 0xEEF7 0xD463
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.
Device Code-Protect Checksum* Blank
Value
0x723 at 0
and Max
Address
PIC10F222 OFF SUM[0x000:0x1FE] + CFGW & 0x01F 0xEE20 0xDC68
ON SUM[0x00:0x3F] + CFGW & 0x01F + SUM_ID(1) 0xEDF7 0xD363
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.
n MCLR MCLR MCLR MCLR VMCLR 11) 1“)
PIC10F220/222
DS41266C-page 16 © 2007 Microchip Technology Inc.
6.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature 10°C TA 40°C
Operating Voltage 4.5V VDD 5.5V
Sym. Characteristics Min. Typ. Max. Units Conditions/
Comments
General
VDDPROG VDD level for programming operations,
program memory
4.5 — 5.5 V
VDDERA VDD level for Bulk Erase operations,
program memory
4.5 — 5.5 V
IDDPROG IDD level for programming operations,
program memory
——0.5mA
IDDERA IDD level for Bulk Erase operations, program
memory
——0.5mA
VPP High voltage on MCLR for Program/Verify
mode entry
12.5 — 13.5 V
IPP MCLR pin current during Program/Verify
mode
——0.45mA
TVHHR MCLR rise time (VSS to VIHH) for Program/
Verify mode entry
——1.0μs
TPPDP Hold time after VPP5—μs
VIH1 (ICSPCLK, ICSPDAT) input high-level 0.8 VDD —— V
VIL1 (ICSPCLK, ICSPDAT) input low-level 0.2 VDD V
TSET0 ICSPCLK, ICSPDAT setup time before
MCLR (Program/Verify mode selection
pattern setup time)
100 — ns
THLD0 ICSPCLK, ICSPDAT hold time after MCLR
(Program/Verify mode selection pattern
setup time)
5—μs
Serial Program/Verify
TSET1 Data in setup time before clock100 — ns
THLD1 Data in hold time after clock100 — ns
TDLY1 Data input not driven to next clock input
(delay required between command/data or
command/command)
1.0 — μs
TDLY2 Delay between clockto clockof next
command or data
1.0 — μs
TDLY3 Clock to data out valid (during Read Data) 80 ns
TERA Erase cycle time 6 10(1) ms
TPROG Programming cycle time (externally timed) 1 2(1) ms
TDIS Time delay for internal programming voltage
discharge
100 — μs
TRESET Time between exiting Program mode with
VDD and VPP at GND and then re-entering
Program mode by applying VDD.
—10— ms
Note 1: Minimum time to ensure that function completes successfully over voltage, temperature and device
variations.
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =
© 2007 Microchip Technology Inc. DS41266C-page 17
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS41266C-page 18 © 2007 Microchip Technology Inc.
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10/05/07