SLG59M1558V Datasheet by Dialog Semiconductor GmbH

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TM“
Silego Technology, Inc. Rev 1.04
000-0059M1558-104 Revised November 14, 2017
Ultra-small 28.5 mΩ, 1.0 A
Integrated Power Switch
SLG59M1558V
Block Diagram
General Description
The SLG59M1558V is designed for load switching applica-
tions with ultra low quiescent current. The part comes with one
28.5 mΩ 1.0 A rated P-channel MOSFET controlled by a single
ON control pin. The product is packaged in an ultra-small 1.0
x 1.0 mm package.
Features
One 1.0 A MOSFET
Ultra Low Quiescent Current
Low RDSON
28.5 mΩ @ 5.0 V
36.4 mΩ @ 3.3 V
44.3 mΩ @ 2.5 V
60.8 mΩ @ 1.8 V
77.6 mΩ @ 1.5 V
•V
IN = 1.5 V to 5.5 V
Pb-Free / Halogen-Free / RoHS compliant
STDFN 4L, 1.0 x 1.0 x 0.55 mm
Pin Configuration
4-pin STDFN
(Top View)
ON 1
VOUT
GND
VIN 23
4
SLG59M1558V
VIN VOUT
ON
1.0 A
Fixed Slew
Rate Control
000-0059M1558-104 Page 2 of 10
SLG59M1558V
Pin Description
Ordering Information
Pin # Pin Name Type Pin Description
1 ON Input Turns on MOSFET.
2 VIN MOSFET Power MOSFET input
3 VOUT MOSFET Power MOSFET output
4 GND GND Ground
Part Number Type Production Flow
SLG59M1558V STDFN 4L Industrial, -40 °C to 85 °C
SLG59M1558VTR STDFN 4L (Tape and Reel) Industrial, -40 °C to 85 °C
000-0059M1558-104 Page 3 of 10
SLG59M1558V
Absolute Maximum Ratings
Electrical Characteristics
Parameter Description Conditions Min. Typ. Max. Unit
VIN Power Supply -- -- 6 V
TSStorage Temperature -65 -- 140 °C
ESDHBM ESD Protection Human Body Model 2000 -- -- V
WDIS Package Power Dissipation -- -- 0.5 W
MOSFET IDSPK Peak Current from Drain to Source For no more than 1 ms with 1% duty cycle -- -- 1.5 A
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TA = -40 °C to 85 °C (unless otherwise stated)
Parameter Description Conditions Min. Typ. Max. Unit
VIN Power Supply Voltage -40 °C to 85 °C 1.5 -- 5.5 V
IDD Power Supply Current (PIN 2) when OFF, VIN = 5.5 V, No load -- 0.02 1 μA
when ON = VIN, No load -- 0.05 0.5 μA
ION_LKG ON Pin Input Leakage -- -- 0.1 μA
RDSON Static Drain to Source
ON Resistance @ TA 25°C
@ 5.5 V -- 28.5 32.0 mΩ
@ 3.3 V -- 36.4 40.0 mΩ
@ 2.5 V -- 44.3 49.0 mΩ
@ 1.8 V -- 60.8 65.0 mΩ
@ 1.5 V -- 77.6 82.0 mΩ
RDSON Static Drain to Source
ON Resistance @ TA 85°C
@ 5.5 V -- 34.0 36.0 mΩ
@ 3.3 V -- 43.8 46.0 mΩ
@ 2.5 V -- 53.3 56.0 mΩ
@ 1.8 V -- 72.2 76.0 mΩ
@ 1.5 V -- 90.7 94.0 mΩ
IDS Operating Current VIN = 1.5 V to 5.5 V -- -- 1.0 A
TON_Delay ON pin Delay Time
50% ON to Ramp Begin
VIN = 5 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
10 15 27 μs
50% ON to Ramp Begin
VIN = 3.3 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
17 31 40 μs
50% ON to Ramp Begin
VIN = 1.5 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
44 69 96 μs
TTotal_ON Total Turn On Time
50% ON to 90% VOUT
VIN = 5 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
114 122 134 μs
50% ON to 90% VOUT
VIN = 3.3 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
146 156 176 μs
50% ON to 90% VOUT
VIN = 1.5 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
292 332 399 μs
000-0059M1558-104 Page 4 of 10
SLG59M1558V
TRISE Rise Time
10% VOUT to 90% VOUT
VIN = 5.0 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
92 97 107 μs
10% VOUT to 90% VOUT
VIN = 3.3 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
116 120 131 μs
10% VOUT to 90% VOUT
VIN = 1.5 V, VOUT_Cap = 0.1 μF,
RL = 10 Ω
228 253 296 μs
ON_VIH Initial Turn On Voltage 0.85 -- VIN V
ON_VIL Low Input Voltage on ON pin -0.3 0 0.3 V
TDelay_OFF OFF Delay Time 50% ON to VOUT Fall, VIN = 5 V,
RL =10 Ω6.2 6.5 7.0 μs
TA = -40 °C to 85 °C (unless otherwise stated)
Parameter Description Conditions Min. Typ. Max. Unit
000-0059M1558-104 Page 5 of 10
SLG59M1558V
VIN vs. Max IDS, Safe Operation Area
TTotal_ON, TON_Delay and Slew Rate Measurement
0
1
2
3
4
5
6
7
8
00.511.52
VIN
Max IDS
Safe Operation Area
VIN vs. Max IDS
SOA Boundary
90% VOUT
50% ON
TON_DELAY
TRISE
ON
VOUT
TTotal_ON
10% VOUT
50% ON
10% VOUT
TOFF_DELAY
TFALL
90% VOUT
s SILEGO |:| Exposed Pad |:| Recommended Land Pattern (PKG face down) (PKG face down) a 400 565 8 (4x) 0 (V) N ,71 i, o v 3 o E W * 9r a + A i, 00 O o o X ,x 9r 3 1 F ‘— 2 200 L 200 170 1000 1300
000-0059M1558-104 Page 6 of 10
SLG59M1558V
SLG59M1558V Power-Up/Power-Down Sequence Considerations
A nominal power-up sequence is to apply VIN and toggle the ON pin LOW-to-HIGH after VIN is at least 90% of its final value. A
nominal power-down sequence is the power-up sequence in reverse order. If VIN ramp is too fast, a voltage glitch may appear
on the output pin at VOUT. To prevent glitches at the output, it is recommended to connect at least 0.1uF capacitor from the VOUT
pin to GND and to keep the VIN ramp time less than 2 ms.
SLG59M1558V Layout Suggestion
Note: All dimensions shown in micrometers (μm)
000-0059M1558-104 Page 7 of 10
SLG59M1558V
Package Top Marking System Definition
NN Serial Number Line 1
Pin 1 Identifier
NN -Part Serial Number Field Line 1
where each “N” character can be A-Z and 0-9
+Serial Number Line 2
+ -Part Serial Number Field Line 2
where “+” character can be +, -, =, or blank
SILEGO Index Area (D/2 x E/2) L A2 D D Unit: mm Symbol Min Nom. Max Symbol Min Nom. Max A 0.50 0.55 0.60 0.95 1.00 1.05 A1 0.005 0.060 0.95 1.00 1.05 A2 0.10 0.15 0.20 0.35 0.40 0.45 UJr—rno b 0.15 0.20 0.25 0.2 REF e 0.40 BSC
000-0059M1558-104 Page 8 of 10
SLG59M1558V
Package Drawing and Dimensions
4 Lead STDFN Package 1.0 x 1.0 mm
s SILEGO STDFNAL F MP etBTM ”°'° 1 F VA Pu 7E / ‘ ./ 4; WV” ' 5m , \ K/ / \_ ‘ ‘ / / , (— . . g/ I g T +777 6”,, <97 ,,,="" {77=""> ~ {7 7v f \ L I” / «K0
000-0059M1558-104 Page 9 of 10
SLG59M1558V
Tape and Reel Specifications
Carrier Tape Drawing and Dimensions
Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 0.55 mm3 (nominal). More
information can be found at www.jedec.org.
Package
Type # of
Pins
Nominal
Package Size
[mm]
Max Units Reel &
Hub Size
[mm]
Leader (min) Trailer (min) Tape
Width
[mm]
Part
Pitch
[mm]
per Reel per Box Pockets Length
[mm] Pockets Length
[mm]
STDFN 4L
1x1mm
0.4P FC
Green
4 1.0 x 1.0 x 0.55 8000 8000 178 / 60 200 400 200 400 8 2
Package
Type
Pocket BTM
Length Pocket BTM
Width Pocket
Depth Index Hole
Pitch Pocket
Pitch Index Hole
Diameter
Index Hole
to Tape
Edge
Index Hole
to Pocket
Center Tape Width
A0 B0 K0 P0 P1 D0 E F W
STDFN 4L
1x1mm 0.4P
FC Green 1.16 1.16 0.63 4 2 1.5 1.75 3.5 8
Refer to EIA-481 specification
000-0059M1558-104 Page 10 of 10
SLG59M1558V
Revision History
Date Version Change
11/14/2017 1.04 Updated Package Marking Definition
11/30/2016 1.03 Fixed Parameter name from VDD to VIN in Abs. Max Table
6/22/2016 1.02 Added section on Power Up/Down Sequence Considerations
Removed IDS_lkg parameter (same as IDD when OFF)
Updated Recommended Layout suggestion
9/11/2015 1.01 Updatd IDD and Tdelay_ON

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