ABLIC Inc.が提供するS-1003 Seriesのデータシート

AABLIC www.cblic‘com ABLIC Inc.
S-1003 Series
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
HIGH-ACCURACY VOLTAGE DETECTOR
© ABLIC Inc., 2013 Rev.1.0_03
1
The S-1003 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixed
internally with an accuracy of 1.0% (VDET 2.2 V). It operates with current consumption of 500 nA typ.
The release signal can be delayed by setting a capacitor externally. Delay time accuracy is 15%.
Moreover, since the S-1003 Series includes the manual reset function, the reset signal can be also output forcibly.
Two output forms Nch open-drain output and CMOS output are available.
Features
Detection voltage: 1.2 V to 5.0 V (0.1 V step)
Detection voltage accuracy: 1.0% (2.2 V VDET 5.0 V)
22 mV (1.2 V VDET 2.2 V)
Current consumption: 500 nA typ.
Operation voltage range: 0.95 V to 10.0 V
Hysteresis width: 5% 2%
Manual reset function: MR pin logic active "L", active "H"
Delay time accuracy: 15% (CD = 4.7 nF)
Output form: Nch open-drain output (Active "L")
CMOS output (Active "L")
Operation temperature range: Ta = 40°C to 85°C
Lead-free (Sn 100%), halogen-free
Applications
Power supply monitor for microcomputer and reset for CPU
Constant voltage power supply monitor for TV, Blu-ray recorder and home appliance
Power supply monitor for portable devices such as notebook PC, digital still camera and mobile phone
Packages
SOT-23-5
SNT-6A
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MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERN 5-1003 Series l Block Diagrams 1. Nch open-drain omput product (5-100 2 ABLICInc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
2
Block Diagrams
1. Nch open-drain output product (S-1003NAxxI)
*1
VSS
*1
*1
VREF


OUT
VDD
Delay
circuit
MR
circuit
CD
MR
*1
*1
Function Status
Output logic Active "L"
MR pin logic Active "L"
*1. Parasitic diode
Figure 1
2. Nch open-drain output product (S-1003NBxxI)
VSS
*1
*1
V
REF


OUT
VDD
Delay
circuit
MR
circuit
CD
MR
*1
*1
*1
Function Status
Output logic Active "L"
MR pin logic Active "H"
*1. Parasitic diode
Figure 2
IIIIIIIII
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
3
3. CMOS output product (S-1003CAxxI)
*1
VSS
*1
*1
V
REF


OUT
VDD
Delay
circuit
MR
circuit
CD
MR
*1
*1 *1
Function Status
Output logic Active "L"
MR pin logic Active "L"
*1. Parasitic diode
Figure 3
4. CMOS output product (S-1003CBxxI)
*1
VSS
*1
*1
V
REF


OUT
VDD
Delay
circuit
MR
circuit
CD
MR
*1
*1 *1
Function Status
Output logic Active "L"
MR pin logic Active "H"
*1. Parasitic diode
Figure 4
IIIIIIIII
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
4
Product Name Structure
Users can select the output form, MR pin logic, detection voltage value, and package type for the S-1003 Series. Refer
to "1. Product name" regarding the contents of product name, "2. Product type list" regarding the product types,
"3. Packages" regarding the package drawings and "4. Product name list" regarding details of product name.
1. Product name
S-1003 x x xx I - xxxx U
Package abbreviation and IC packing specifications*1
M5T1: SOT-23-5, Tape
I6T1: SNT-6A, Tape
Detection voltage value
12 to 50
(e.g., when the detection voltage is 1.2 V, it is expressed as 12.)
Environmental code
U: Lead-free (Sn 100%), halogen-free
Operation temperature
I: Ta = 40C to 85C
Output form*2
N: Nch open-drain output (Active "L")*3
C: CMOS output (Active "L")*3
MR pin logic*2
A: Active "L"
B: Active "H"
*1. Refer to the tape drawing.
*2. Refer to "2. Product type list".
*3. If you request the product with output logic active "H", contact our sales office.
2. Product type list
Table 1
Product Type Output Form MR Pin Logic Output Logic
NA Nch open-drain output Active "L" Active "L"
NB Active "H" Active "L"
CA CMOS output Active "L" Active "L"
CB Active "H" Active "L"
3. Packages
Table 2 Package Drawing Codes
Package Name Dimension Tape Reel Land
SOT-23-5 MP005-A-P-SD MP005-A-C-SD MP005-A-R-SD
SNT-6A PG006-A-P-SD PG006-A-C-SD PG006-A-R-SD PG006-A-L-SD
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
5
4. Product name list
4. 1 S-1003 Series NA type
Output form: Nch open-drain output (Active "L")
MR pin logic: Active "L"
Table 3
Detection Voltage SOT-23-5 SNT-6A
1.2 V 22 mV S-1003NA12I-M5T1U S-1003NA12I-I6T1U
1.3 V 22 mV S-1003NA13I-M5T1U S-1003NA13I-I6T1U
1.4 V 22 mV S-1003NA14I-M5T1U S-1003NA14I-I6T1U
1.5 V 22 mV S-1003NA15I-M5T1U S-1003NA15I-I6T1U
1.6 V 22 mV S-1003NA16I-M5T1U S-1003NA16I-I6T1U
1.7 V 22 mV S-1003NA17I-M5T1U S-1003NA17I-I6T1U
1.8 V 22 mV S-1003NA18I-M5T1U S-1003NA18I-I6T1U
1.9 V 22 mV S-1003NA19I-M5T1U S-1003NA19I-I6T1U
2.0 V 22 mV S-1003NA20I-M5T1U S-1003NA20I-I6T1U
2.1 V 22 mV S-1003NA21I-M5T1U S-1003NA21I-I6T1U
2.2 V 1.0% S-1003NA22I-M5T1U S-1003NA22I-I6T1U
2.3 V 1.0% S-1003NA23I-M5T1U S-1003NA23I-I6T1U
2.4 V 1.0% S-1003NA24I-M5T1U S-1003NA24I-I6T1U
2.5 V 1.0% S-1003NA25I-M5T1U S-1003NA25I-I6T1U
2.6 V 1.0% S-1003NA26I-M5T1U S-1003NA26I-I6T1U
2.7 V 1.0% S-1003NA27I-M5T1U S-1003NA27I-I6T1U
2.8 V 1.0% S-1003NA28I-M5T1U S-1003NA28I-I6T1U
2.9 V 1.0% S-1003NA29I-M5T1U S-1003NA29I-I6T1U
3.0 V 1.0% S-1003NA30I-M5T1U S-1003NA30I-I6T1U
3.1 V 1.0% S-1003NA31I-M5T1U S-1003NA31I-I6T1U
3.2 V 1.0% S-1003NA32I-M5T1U S-1003NA32I-I6T1U
3.3 V 1.0% S-1003NA33I-M5T1U S-1003NA33I-I6T1U
3.4 V 1.0% S-1003NA34I-M5T1U S-1003NA34I-I6T1U
3.5 V 1.0% S-1003NA35I-M5T1U S-1003NA35I-I6T1U
3.6 V 1.0% S-1003NA36I-M5T1U S-1003NA36I-I6T1U
3.7 V 1.0% S-1003NA37I-M5T1U S-1003NA37I-I6T1U
3.8 V 1.0% S-1003NA38I-M5T1U S-1003NA38I-I6T1U
3.9 V 1.0% S-1003NA39I-M5T1U S-1003NA39I-I6T1U
4.0 V 1.0% S-1003NA40I-M5T1U S-1003NA40I-I6T1U
4.1 V 1.0% S-1003NA41I-M5T1U S-1003NA41I-I6T1U
4.2 V 1.0% S-1003NA42I-M5T1U S-1003NA42I-I6T1U
4.3 V 1.0% S-1003NA43I-M5T1U S-1003NA43I-I6T1U
4.4 V 1.0% S-1003NA44I-M5T1U S-1003NA44I-I6T1U
4.5 V 1.0% S-1003NA45I-M5T1U S-1003NA45I-I6T1U
4.6 V 1.0% S-1003NA46I-M5T1U S-1003NA46I-I6T1U
4.7 V 1.0% S-1003NA47I-M5T1U S-1003NA47I-I6T1U
4.8 V 1.0% S-1003NA48I-M5T1U S-1003NA48I-I6T1U
4.9 V 1.0% S-1003NA49I-M5T1U S-1003NA49I-I6T1U
5.0 V 1.0% S-1003NA50I-M5T1U S-1003NA50I-I6T1U
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
6
4. 2 S-1003 Series NB type
Output form: Nch open-drain output (Active "L")
MR pin logic: Active "H"
Table 4
Detection Voltage SOT-23-5 SNT-6A
1.2 V 22 mV S-1003NB12I-M5T1U S-1003NB12I-I6T1U
1.3 V 22 mV S-1003NB13I-M5T1U S-1003NB13I-I6T1U
1.4 V 22 mV S-1003NB14I-M5T1U S-1003NB14I-I6T1U
1.5 V 22 mV S-1003NB15I-M5T1U S-1003NB15I-I6T1U
1.6 V 22 mV S-1003NB16I-M5T1U S-1003NB16I-I6T1U
1.7 V 22 mV S-1003NB17I-M5T1U S-1003NB17I-I6T1U
1.8 V 22 mV S-1003NB18I-M5T1U S-1003NB18I-I6T1U
1.9 V 22 mV S-1003NB19I-M5T1U S-1003NB19I-I6T1U
2.0 V 22 mV S-1003NB20I-M5T1U S-1003NB20I-I6T1U
2.1 V 22 mV S-1003NB21I-M5T1U S-1003NB21I-I6T1U
2.2 V 1.0% S-1003NB22I-M5T1U S-1003NB22I-I6T1U
2.3 V 1.0% S-1003NB23I-M5T1U S-1003NB23I-I6T1U
2.4 V 1.0% S-1003NB24I-M5T1U S-1003NB24I-I6T1U
2.5 V 1.0% S-1003NB25I-M5T1U S-1003NB25I-I6T1U
2.6 V 1.0% S-1003NB26I-M5T1U S-1003NB26I-I6T1U
2.7 V 1.0% S-1003NB27I-M5T1U S-1003NB27I-I6T1U
2.8 V 1.0% S-1003NB28I-M5T1U S-1003NB28I-I6T1U
2.9 V 1.0% S-1003NB29I-M5T1U S-1003NB29I-I6T1U
3.0 V 1.0% S-1003NB30I-M5T1U S-1003NB30I-I6T1U
3.1 V 1.0% S-1003NB31I-M5T1U S-1003NB31I-I6T1U
3.2 V 1.0% S-1003NB32I-M5T1U S-1003NB32I-I6T1U
3.3 V 1.0% S-1003NB33I-M5T1U S-1003NB33I-I6T1U
3.4 V 1.0% S-1003NB34I-M5T1U S-1003NB34I-I6T1U
3.5 V 1.0% S-1003NB35I-M5T1U S-1003NB35I-I6T1U
3.6 V 1.0% S-1003NB36I-M5T1U S-1003NB36I-I6T1U
3.7 V 1.0% S-1003NB37I-M5T1U S-1003NB37I-I6T1U
3.8 V 1.0% S-1003NB38I-M5T1U S-1003NB38I-I6T1U
3.9 V 1.0% S-1003NB39I-M5T1U S-1003NB39I-I6T1U
4.0 V 1.0% S-1003NB40I-M5T1U S-1003NB40I-I6T1U
4.1 V 1.0% S-1003NB41I-M5T1U S-1003NB41I-I6T1U
4.2 V 1.0% S-1003NB42I-M5T1U S-1003NB42I-I6T1U
4.3 V 1.0% S-1003NB43I-M5T1U S-1003NB43I-I6T1U
4.4 V 1.0% S-1003NB44I-M5T1U S-1003NB44I-I6T1U
4.5 V 1.0% S-1003NB45I-M5T1U S-1003NB45I-I6T1U
4.6 V 1.0% S-1003NB46I-M5T1U S-1003NB46I-I6T1U
4.7 V 1.0% S-1003NB47I-M5T1U S-1003NB47I-I6T1U
4.8 V 1.0% S-1003NB48I-M5T1U S-1003NB48I-I6T1U
4.9 V 1.0% S-1003NB49I-M5T1U S-1003NB49I-I6T1U
5.0 V 1.0% S-1003NB50I-M5T1U S-1003NB50I-I6T1U
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
7
4. 3 S-1003 Series CA type
Output form: CMOS output (Active "L")
MR pin logic: Active "L"
Table 5
Detection Voltage SOT-23-5 SNT-6A
1.2 V 22 mV S-1003CA12I-M5T1U S-1003CA12I-I6T1U
1.3 V 22 mV S-1003CA13I-M5T1U S-1003CA13I-I6T1U
1.4 V 22 mV S-1003CA14I-M5T1U S-1003CA14I-I6T1U
1.5 V 22 mV S-1003CA15I-M5T1U S-1003CA15I-I6T1U
1.6 V 22 mV S-1003CA16I-M5T1U S-1003CA16I-I6T1U
1.7 V 22 mV S-1003CA17I-M5T1U S-1003CA17I-I6T1U
1.8 V 22 mV S-1003CA18I-M5T1U S-1003CA18I-I6T1U
1.9 V 22 mV S-1003CA19I-M5T1U S-1003CA19I-I6T1U
2.0 V 22 mV S-1003CA20I-M5T1U S-1003CA20I-I6T1U
2.1 V 22 mV S-1003CA21I-M5T1U S-1003CA21I-I6T1U
2.2 V 1.0% S-1003CA22I-M5T1U S-1003CA22I-I6T1U
2.3 V 1.0% S-1003CA23I-M5T1U S-1003CA23I-I6T1U
2.4 V 1.0% S-1003CA24I-M5T1U S-1003CA24I-I6T1U
2.5 V 1.0% S-1003CA25I-M5T1U S-1003CA25I-I6T1U
2.6 V 1.0% S-1003CA26I-M5T1U S-1003CA26I-I6T1U
2.7 V 1.0% S-1003CA27I-M5T1U S-1003CA27I-I6T1U
2.8 V 1.0% S-1003CA28I-M5T1U S-1003CA28I-I6T1U
2.9 V 1.0% S-1003CA29I-M5T1U S-1003CA29I-I6T1U
3.0 V 1.0% S-1003CA30I-M5T1U S-1003CA30I-I6T1U
3.1 V 1.0% S-1003CA31I-M5T1U S-1003CA31I-I6T1U
3.2 V 1.0% S-1003CA32I-M5T1U S-1003CA32I-I6T1U
3.3 V 1.0% S-1003CA33I-M5T1U S-1003CA33I-I6T1U
3.4 V 1.0% S-1003CA34I-M5T1U S-1003CA34I-I6T1U
3.5 V 1.0% S-1003CA35I-M5T1U S-1003CA35I-I6T1U
3.6 V 1.0% S-1003CA36I-M5T1U S-1003CA36I-I6T1U
3.7 V 1.0% S-1003CA37I-M5T1U S-1003CA37I-I6T1U
3.8 V 1.0% S-1003CA38I-M5T1U S-1003CA38I-I6T1U
3.9 V 1.0% S-1003CA39I-M5T1U S-1003CA39I-I6T1U
4.0 V 1.0% S-1003CA40I-M5T1U S-1003CA40I-I6T1U
4.1 V 1.0% S-1003CA41I-M5T1U S-1003CA41I-I6T1U
4.2 V 1.0% S-1003CA42I-M5T1U S-1003CA42I-I6T1U
4.3 V 1.0% S-1003CA43I-M5T1U S-1003CA43I-I6T1U
4.4 V 1.0% S-1003CA44I-M5T1U S-1003CA44I-I6T1U
4.5 V 1.0% S-1003CA45I-M5T1U S-1003CA45I-I6T1U
4.6 V 1.0% S-1003CA46I-M5T1U S-1003CA46I-I6T1U
4.7 V 1.0% S-1003CA47I-M5T1U S-1003CA47I-I6T1U
4.8 V 1.0% S-1003CA48I-M5T1U S-1003CA48I-I6T1U
4.9 V 1.0% S-1003CA49I-M5T1U S-1003CA49I-I6T1U
5.0 V 1.0% S-1003CA50I-M5T1U S-1003CA50I-I6T1U
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
8
4. 4 S-1003 Series CB type
Output form: CMOS output (Active "L")
MR pin logic: Active "H"
Table 6
Detection Voltage SOT-23-5 SNT-6A
1.2 V 22 mV S-1003CB12I-M5T1U S-1003CB12I-I6T1U
1.3 V 22 mV S-1003CB13I-M5T1U S-1003CB13I-I6T1U
1.4 V 22 mV S-1003CB14I-M5T1U S-1003CB14I-I6T1U
1.5 V 22 mV S-1003CB15I-M5T1U S-1003CB15I-I6T1U
1.6 V 22 mV S-1003CB16I-M5T1U S-1003CB16I-I6T1U
1.7 V 22 mV S-1003CB17I-M5T1U S-1003CB17I-I6T1U
1.8 V 22 mV S-1003CB18I-M5T1U S-1003CB18I-I6T1U
1.9 V 22 mV S-1003CB19I-M5T1U S-1003CB19I-I6T1U
2.0 V 22 mV S-1003CB20I-M5T1U S-1003CB20I-I6T1U
2.1 V 22 mV S-1003CB21I-M5T1U S-1003CB21I-I6T1U
2.2 V 1.0% S-1003CB22I-M5T1U S-1003CB22I-I6T1U
2.3 V 1.0% S-1003CB23I-M5T1U S-1003CB23I-I6T1U
2.4 V 1.0% S-1003CB24I-M5T1U S-1003CB24I-I6T1U
2.5 V 1.0% S-1003CB25I-M5T1U S-1003CB25I-I6T1U
2.6 V 1.0% S-1003CB26I-M5T1U S-1003CB26I-I6T1U
2.7 V 1.0% S-1003CB27I-M5T1U S-1003CB27I-I6T1U
2.8 V 1.0% S-1003CB28I-M5T1U S-1003CB28I-I6T1U
2.9 V 1.0% S-1003CB29I-M5T1U S-1003CB29I-I6T1U
3.0 V 1.0% S-1003CB30I-M5T1U S-1003CB30I-I6T1U
3.1 V 1.0% S-1003CB31I-M5T1U S-1003CB31I-I6T1U
3.2 V 1.0% S-1003CB32I-M5T1U S-1003CB32I-I6T1U
3.3 V 1.0% S-1003CB33I-M5T1U S-1003CB33I-I6T1U
3.4 V 1.0% S-1003CB34I-M5T1U S-1003CB34I-I6T1U
3.5 V 1.0% S-1003CB35I-M5T1U S-1003CB35I-I6T1U
3.6 V 1.0% S-1003CB36I-M5T1U S-1003CB36I-I6T1U
3.7 V 1.0% S-1003CB37I-M5T1U S-1003CB37I-I6T1U
3.8 V 1.0% S-1003CB38I-M5T1U S-1003CB38I-I6T1U
3.9 V 1.0% S-1003CB39I-M5T1U S-1003CB39I-I6T1U
4.0 V 1.0% S-1003CB40I-M5T1U S-1003CB40I-I6T1U
4.1 V 1.0% S-1003CB41I-M5T1U S-1003CB41I-I6T1U
4.2 V 1.0% S-1003CB42I-M5T1U S-1003CB42I-I6T1U
4.3 V 1.0% S-1003CB43I-M5T1U S-1003CB43I-I6T1U
4.4 V 1.0% S-1003CB44I-M5T1U S-1003CB44I-I6T1U
4.5 V 1.0% S-1003CB45I-M5T1U S-1003CB45I-I6T1U
4.6 V 1.0% S-1003CB46I-M5T1U S-1003CB46I-I6T1U
4.7 V 1.0% S-1003CB47I-M5T1U S-1003CB47I-I6T1U
4.8 V 1.0% S-1003CB48I-M5T1U S-1003CB48I-I6T1U
4.9 V 1.0% S-1003CB49I-M5T1U S-1003CB49I-I6T1U
5.0 V 1.0% S-1003CB50I-M5T1U S-1003CB50I-I6T1U
HHH ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
9
Pin Configurations
1. SOT-23-5
132
45
Top view
Figure 5
Table 7
Pin No. Symbol Description
1 CD Connection pin for delay capacitor
2 VSS GND pin
3 MR Manual reset pin
4 OUT Voltage detection output pin
5 VDD Voltage input pin
2. SNT-6A
5
4
6
2
3
1
Top view
Figure 6
Table 8
Pin No. Symbol Description
1 CD Connection pin for delay capacitor
2 VDD Voltage input pin
3 OUT Voltage detection output pin
4 MR Manual reset pin
5
NC*1 No connection
6 VSS GND pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
ABLIC Inc. 6A , 0 0 2 0 300 100 SE; an: :Emgmmfi saga. 1O
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
10
Absolute Maximum Ratings
Table 9
(Ta = 25°C unless otherwise specified)
Item Symbol Absolute Maximum Rating Unit
Power supply voltage VDDVSS 12.0 V
CD pin input voltage VCD V
SS0.3 to VDD 0.3 V
MR pin input voltage VMR V
SS0.3 to VDD 0.3 V
Output voltage Nch open-drain output product VOUT VSS0.3 to 12.0 V
CMOS output product VSS0.3 to VDD 0.3 V
Output current IOUT 50 mA
Power dissipation SOT-23-5 PD 600*1 mW
SNT-6A 400*1 mW
Operation ambient temperature To
pr
40 to 85 °C
Storage temperature Tst
g
40 to 125 °C
*1. When mounted on board
[Mounted board]
(1) Board size: 114.3 mm 76.2 mm t1.6 mm
(2) Name: JEDEC STANDARD51-7
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
0 50 100 150
0
Power Dissipation (PD) [mW]
Ambient Temperature (Ta) [C]
200
100
300
500
700
SOT-23-5
400
600
SNT-6A
Figure 7 Power Dissipation of Package (When Mounted on Board)
A , VDET A , VDEI ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
11
Electrical Characteristics
1. Nch open-drain output product
Table 10
(Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Detection voltage*1 VDET
1.2 V VDET 2.2 V VDET(S)
0.022 VDET(S) VDET(S)
0.022 V 1
2.2 V VDET 5.0 V VDET(S)
0.99 VDET(S) VDET(S)
1.01 V 1
Hysteresis width VHYS VDET
0.03
VDET
0.05
VDET
0.07 V 1
Current consumption ISS V
DD = VDET
(
S
)
1.0 V 0.50 0.90 A 2
Operation voltage VDD 0.95 10.0 V 1
Output current IOUT
Output transistor
Nch
VDS*2 = 0.5 V
MR pin active
VDD = 0.95 V 0.59 1.00 mA 3
VDD = 1.2 V 0.73 1.33 mA 3
VDD = 2.4 V 1.47 2.39 mA 3
VDD = 4.8 V 1.86 2.50 mA 3
Leakage current ILEAK
Output transistor
Nch
VDD = 10.0 V, VOUT = 10.0 V
MR pin non-active
0.08 A 3
Delay time*3 tD C
D = 4.7 nF 8.5 10.0 11.5 ms 4
Detection voltage
temperature
coefficient*4
VDET
Ta VDET Ta = 40°C to 85°C 100 350 ppm/°C 1
MR pin
input voltage "H" VMRH
NA type
(MR pin logic active "L")
VDD
0.3  V 6
NB type
(MR pin logic active "H") 1.2   V 6
MR pin
input voltage "L" VMRL
NA type
(MR pin logic active "L")   VDD
1.2V 6
NB type
(MR pin logic active "H")   0.3 V 6
MR pin
input resistance RMR 0.5 1.0 1.6 M 6
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 3 or Table 4.)
*2. VDS: Drain-to-source voltage of the output transistor
*3. The time period from when the pulse voltage of 0.95 V VDET(S)1.0 V is applied to the VDD pin to when VOUT
reaches VDD 0.9, after the output pin is pulled up to VDD by the resistance of 100 k
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
Ta []
mV/°C *1 = VDET(S) (typ.)[]
V*2 VDET
Ta VDET []
ppm/°C *3 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
A , VDET LVDEY 7 ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
12
2. CMOS output product
Table 11
(Ta = 25°C unless otherwise specified)
Item Symbol Condition Min. Typ. Max. Unit
Test
Circuit
Detection voltage*1 VDET
1.2 V VDET 2.2 V VDET(S)
0.022 VDET(S) VDET(S)
0.022 V 1
2.2 V VDET 5.0 V VDET(S)
0.99 VDET(S) VDET(S)
1.01 V 1
Hysteresis width VHYS VDET
0.03
VDET
0.05
VDET
0.07 V 1
Current consumption ISS V
DD = VDET
(
S
)
1.0 V 0.50 0.90 A 2
Operation voltage VDD 0.95 10.0 V 1
Output current IOUT
Output transistor
Nch
VDS*2 = 0.5 V
MR pin active
VDD = 0.95 V 0.59 1.00 mA 3
VDD = 1.2 V 0.73 1.33 mA 3
VDD = 2.4 V 1.47 2.39 mA 3
VDD = 4.8 V 1.86 2.50 mA 3
Output transistor
Pch
VDS*2 = 0.5 V
VDD = 4.8 V
S-1003Cx12 to 43 1.62 2.60 mA 5
VDD = 6.0 V 1.78 2.86  mA 5
Delay time*3 tD C
D = 4.7 nF 8.5 10.0 11.5 ms 4
Detection voltage
temperature
coefficient*4
VDET
Ta VDET Ta = 40°C to 85°C 100 350 ppm/°C 1
MR pin
input voltage "H" VMRH
CA type
(MR pin logic active "L")
VDD
0.3  V 6
CB type
(MR pin logic active "H") 1.2   V 6
MR pin
input voltage "L" VMRL
CA type
(MR pin logic active "L")   VDD
1.2V 6
CB type
(MR pin logic active "H")   0.3 V 6
MR pin
input resistance RMR 0.5 1.0 1.6 M 6
*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value (the center value of the detection voltage
range in Table 5 or Table 6.)
*2. VDS: Drain-to-source voltage of the output transistor
*3. The time period from when the pulse voltage of 0.95 V VDET(S)1.0 V is applied to the VDD pin to when VOUT
reaches VDD 0.9.
*4. The temperature change of the detection voltage [mV/°C] is calculated by using the following equation.
VDET
Ta []
mV/°C *1 = VDET(S) (typ.)[]
V*2 VDET
Ta VDET []
ppm/°C *3 1000
*1. Temperature change of the detection voltage
*2. Set detection voltage
*3. Detection voltage temperature coefficient
MR VSS OUT CD OUT CD ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
13
Test Circuits
VDD VDD
VSS
OUT
R*1
100 k
V
V
CD
MR

*2
VDD
OUT
A
VDD
VSS CD
MR
*1
*1. R is unnecessary for CMOS output product. *1. Set to VDD or GND (MR pin non-active).
*2. Set to VDD or GND (MR pin non-active).
Figure 8 Test Circuit 1 Figure 9 Test Circuit 2
VDS
VDD
AV
V
VDD
VSS CD
OUT
MR
*1


P.G
.
VDD
VSS
OUT
R
100 k
CD
MR
CD
VOUT
*2
Oscilloscope
*1. Set to VDD or GND. *1. R is unnecessary for CMOS output product.
*2. Set to VDD or GND (MR pin non-active).
Figure 10 Test Circuit 3 Figure 11 Test Circuit 4
VDD
VDS
AV
V
VDD
VSS CD
OUT
MR


*1
VDD VDD
VSS CD
OUT
A
VV
MR
R*1
100 k
VMR
*1. Set to VDD or GND (MR pin non-active). *1. R is unnecessary for CMOS output product.
Figure 12 Test Circuit 5 Figure 13 Test Circuit 6
Hys‘eresis wxdlh (VHvs) Ou‘pm from OUT pin _ Vss Ou‘pm from OUT pin ABLIC Inc. _ Minimum nperauon vohage VDD IVSS VDD I
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
14
Timing Charts
1. Nch open-drain output product
V
OUT
VDD
VSS
R
100 k
VDD
VSS
Output from OUT pin
VDD
VSS
MR
tD
CD
VDD

Hysteresis width
(VHYS)
Release voltage (VDET)
Detection voltage (VDET)
Minimum operation voltage
*1. Set to VDD or GND (MR pin non-active).
*1
Figure 14
2. CMOS output product
Release voltage (VDET)
Detection voltage (VDET)
VDD
VSS
Minimum operation voltage
Hysteresis width
(VHYS)
Output from OUT pin
VSS
VDD
tD
OUT
VDD
VSS
MR
CD V
VDD
*1
*1. Set to VDD or GND (MR pin non-active).
Remark When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 15
R5+ Rc 'VDD + + Ra - VDD ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
15
Operation
1. Basic operation: CMOS output (active "L") product
(1) When the power supply voltage (VDD) is the release voltage (VDET) or more, the Nch transistor is OFF and
the Pch transistor is ON to output VDD ("H"). Since the Nch transistor N1 in Figure 16 is OFF, the comparator
input voltage is (RB RC ) VDD
RA RB RC .
(2) Although VDD decreases to VDET or less, VDD is output when VDD is higher than the detection voltage (VDET).
When VDD decreases to VDET or less (point A in Figure 17), the Nch transistor is ON and the Pch transistor
is OFF so that VSS ("L") is output. At this time, the Nch transistor N1 in Figure 16 is turned on, and the input
voltage to the comparator is RB VDD
RA RB .
(3) The output is indefinite by decreasing VDD to the IC's minimum operation voltage or less. If the output is
pulled up, it will be VDD.
(4) VSS is output by increasing VDD to the minimum operation voltage or more. Although VDD exceeds VDET and
VDD is less than VDET, the output is VSS.
(5) When increasing VDD to VDET or more (point B in Figure 17), the Nch transistor is OFF and the Pch
transistor is ON so that VDD is output. At this time, VDD is output from the OUT pin after the passage of the
delay time (tD).
VSS
*1
*1
VREF


OUT
VDD
CD
Delay
circuit
*1
*1
CD
Pch
Nch
N1
RC
RA
RB
MR
*1
MR
circuit
*1
*1. Parasitic diode
Figure 16 Operation 1
Hysteresis width
(V
HYS
)
A
BV
DD
V
SS
Minimum operation voltage
Output from OUT pin
V
DD
V
SS
(1) (2) (3) (5) (4)
Release voltage (V
DET
)
Detection voltage (V
DET
)
t
D
Remark When VDD is the minimum operation voltage or less, the output voltage from the OUT pin is indefinite
in the shaded area.
Figure 17 Operation 2
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
16
2. Manual reset function
The OUT pin voltage can be changed to detection status forcibly by the MR pin input voltage (VMR).
When not using the manual reset function, set VMR = VDD in the S-1003 Series xA type, and VMR = VSS in the
S-1003 Series xB type.
Caution Perform thorough evaluation in the actual application when using the MR pin in open. Due to the
parasitic capacitance of the MR pin, the manual reset function may malfunction when the power supply
fluctuates.
2. 1 S-1003 Series xA type (MR pin logic active "L")
(1) MR pin = "L"
When the VDD pin voltage is the release voltage (VDET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the
MR pin.
(2) MR pin = "H"
If a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.
VDD (VDET)
VDD
VSS
MR pin input voltage "H" (VMRH)
Input from VDD pin
tD
Input from MR pin
Output from OUT pin
MR pin input voltage "L" (VMRL)
(1) (2)
Figure 18 Timing Chart of MR Pin Logic Active "L"
Remark Since the MR pin is pulled up to the VDD pin internally, output from the OUT pin is determined to be "H" or "L" in
the floating status depending on the VDD pin voltage (Refer to Figure 19).
VSS
VDD
MR
*1
*1
RMR
*1. Parasitic diode
Figure 19
IIIIIIIII
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
17
2. 2 S-1003 Series xB type (MR pin logic active "H")
(1) MR pin = "H"
When the VDD pin voltage is the release voltage (VDET) or more, the OUT pin changes to the detection status
from the release status immediately if a voltage of the MR pin input voltage "H" (VMRH) or more is applied to the
MR pin.
(2) MR pin = "L"
If a voltage of the MR pin input voltage "L" (VMRL) or less is applied to the MR pin, output from the OUT pin is
determined to be "H" or "L" depending on the VDD pin voltage.
After the passage of the delay time (tD), the OUT pin changes to the release status from the detection status.
VDD (VDET)
VDD
VSS
MR pin input voltage "H" (VMRH)
tD
MR pin input voltage "L" (VMRL)
(1) (2)
Input from VDD pin
Input from MR pin
Output from OUT pin
Figure 20 Timing Chart of MR Pin Logic Active "H"
Remark Since the MR pin is pulled down to the VSS pin internally, output from the OUT pin is determined to be "H" or
"L" in the floating status depending on the VDD pin voltage (Refer to Figure 21).
VSS
VDD
MR
*1
*1
RMR
*1. Parasitic diode
Figure 21
VMRH , VMRL A ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
18
2. 3 Cautions of manual reset function
2. 3. 1 Slew rate when switching manual reset function
Although there is a hysteresis width between the MR pin input voltage "L" (VMRL) and the MR pin input voltage "H"
(VMRH), note that the IC may malfunction if the slew rate (Refer to Figure 22, Figure 23) is low when the MR pin
voltage is changed.
The slew rate is calculated by using the following equation.
Slew rate = VMRH VMRL
t
(1) When MR pin logic is active "L"
The OUT pin voltage may oscillate if the parasitic resistance (RP) between the power supply and the VDD pin is
high.
In case of RP 8 k  Connect a capacitor of 1 nF or more between the VDD pin and the VSS pin.
In case of 5 k RP 8 kCapacitors are unnecessary if the slew rate is 100 V/s or higher.
In case of RP 5 k Capacitors are unnecessary if the slew rate is 1 V/s or higher.
V
MR
t
V
MRH
V
MRL
Tim
e
Figure 22
(2) When MR pin logic is active "H"
Connect a capacitor of 100 pF or more to the CD pin, and set the slew rate 20 V/s or higher.
V
MR
t
V
MRH
V
MRL
Time
Figure 23
on ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
19
2. 4 When connecting resistance (RA) between power supply voltage (VDD) and VDD pin
When the MR pin voltage (VMR) is an intermediate voltage (especially VMRLVMRVMRH), the current consumption
increases by 25 A max. A voltage drop occurs since this current flows through RA. If the VDD pin voltage (VIN)
becomes the detection voltage (VDET) or less for that reason, the OUT pin changes to the detection status, and the
detection status or the release status are not controlled by VMR. The OUT pin may not be able to change to the
release status unless VDD is raised (Refer to Figure 24).
(1) When MR pin logic is active "L"
In case of VIN VMR, a current also flows through the MR pin input resistance (RMR). For example, when VIN =
10 V, VMR = 1 V, RMR = 0.5 M (min.), a current of 18 A flows from the VDD pin to the MR pin. Therefore, set
RA so as to satisfy the following equation.
RA (VDD (VDET)) / (25 AMR pin current)
(2) When MR pin logic is active "H"
Set RA so as to satisfy the following equation.
RA (VDD (VDET)) / 25 A
OUT
VDD
VSS CD
MR
V
DD
V
MR
R
A
GND
V
IN
(Nch open-drain output product)
Figure 24
Do ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
20
3. Delay circuit
The delay circuit delays the output signal to the OUT pin from the time at which the power supply voltage (VDD)
exceeds the release voltage (VDET) when VDD is turned on. The output signal is not delayed when VDD decreases
to the detection voltage (VDET) or less (refer to "Figure 17 Operation 2").
The delay time (tD) is determined by the time constant of the built-in constant current (approx. 100 nA) and the
attached delay capacitor (CD), or the delay time (tD0) when the CD pin is open, and calculated from the following
equation. When the CD value is sufficiently large, the tD0 value can be disregarded.
tD [ms] = Delay coefficient CD [nF] tD0 [ms]
Table 12 Delay Coefficient
Operation
Temperature
Delay Coefficient
Min. Typ. Max.
Ta = 85°C 1.60 1.89 2.13
Ta = 25°C 1.78 2.05 2.30
Ta = 40°C 2.01 2.31 2.71
Table 13 Delay Time
Operation Temperature Delay Time (tD0)
Min. Typ. Max.
Ta = 40°C to 85°C 0.021 ms 0.044 ms 0.147 ms
Caution 1. When the CD pin is open, a double pulse shown in Figure 25 may appear at release.
To avoid the double pulse, attach a 100 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin from the exterior.
VOUT
Time
Figure 25
2. Mounted board layout should be made in such a way that no current flows into or flows from
the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be
provided.
3. There is no limit for the capacitance of CD as long as the leakage current of the capacitor can
be ignored against the built-in constant current value. Leakage current causes deviation in
delay time. When the leakage current is larger than the built-in constant current, no release
takes place.
A * V051 A A + Von A A + Von +VDEr A 7 Van A + Vnzr A r V951 A VHVS A r VDEY ABLIC Inc. A + VDEY A 7 Von
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
21
4. Other characteristics
4. 1 Temperature characteristics of detection voltage
The shaded area in Figure 26 shows the temperature characteristics of detection voltage in the operation
temperature range.
40 25
0.945 mV/°C
V
DET
[V]
85 Ta [°C]
0.945 mV/°C
V
DET25*1
*1. VDET25 is an actual detection voltage value at Ta = 25°C.
Figure 26 Temperature Characteristics of Detection Voltage (Example for VDET = 2.7 V)
4. 2 Temperature characteristics of release voltage
The temperature change VDET
Ta of the release voltage is calculated by using the temperature change
VDET
Ta of the detection voltage as follows:
VDET
Ta = VDET
VDET VDET
Ta
The temperature change of the release voltage and the detection voltage has the same sign consequently.
4. 3 Temperature characteristics of hysteresis voltage
The temperature change of the hysteresis voltage is expressed as VDET
Ta VDET
Ta and is calculated as
follows:
VDET
Ta VDET
Ta = VHYS
VDET VDET
Ta
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
22
Standard Circuit
VDD
OUT
VSS
R*1
100 k
CD
*2
CD
MR
*1. R is unnecessary for CMOS output product.
*2. The delay capacitor (CD) should be connected directly to the CD pin and the VSS pin.
Figure 27
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
if: ABLIC Inc. § i7; [TOU
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
23
Explanation of Terms
1. Detection voltage (VDET)
The detection voltage is a voltage at which the output in Figure 30 turns to "L". The detection voltage varies slightly
among products of the same specification. The variation of detection voltage between the specified minimum
(VDET min.) and the maximum (VDET max.) is called the detection voltage range (Refer to Figure 28).
Example: In the S-1003Cx15, the detection voltage is either one in the range of 1.478 V VDET 1.522 V.
This means that some S-1003Cx15 have VDET = 1.478 V and some have VDET = 1.522 V.
2. Release voltage (VDET)
The release voltage is a voltage at which the output in Figure 30 turns to "H". The release voltage varies slightly
among products of the same specification. The variation of release voltage between the specified minimum (VDET
min.) and the maximum (VDET max.) is called the release voltage range (Refer to Figure 29). The range is
calculated from the actual detection voltage (VDET) of a product and is in the range of VDET 1.03 VDET VDET
1.07.
Example: For the S-1003Cx15, the release voltage is either one in the range of 1.522 V VDET 1.629 V.
This means that some S-1003Cx15 have VDET = 1.522 V and some have VDET = 1.629 V.
Detection voltage
Detection voltage
range
V
DD
V
DET
min.
V
DET
max.
OUT
Release voltage
VDD
VDET min.
VDET max.
OUT
Release voltage
range
tD
Figure 28 Detection Voltage Figure 29 Release Voltage
VDD VDD
VSS
OUT
R*1
100 k
V
V
CD
MR

*2
*1. R is unnecessary for CMOS output product.
*2. Set to VDD or GND (MR pin non-active).
Figure 30 Test Circuit of Detection Voltage and Release Voltage
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
24
3. Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage at
point B the voltage at point A = VHYS in "Figure 17 Operation 2"). Setting the hysteresis width between the
detection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.
4. Delay time (tD)
The delay time in the S-1003 Series is a period from the input voltage to the VDD pin exceeding the release voltage
(VDET) until the output from the OUT pin inverts. The delay time changes according to the delay capacitor (CD).
t
D
V
DD
OUT
V
DET
Figure 31 Delay Time
5. Feed-through current
Feed-through current is a current that flows instantaneously at the time of detection and release of a voltage
detector. The feed-through current is large in CMOS output product, small in Nch open-drain output product.
6. Oscillation
In applications where a resistor is connected to the voltage detector input (Figure 32), taking a CMOS active "L"
product for example, the feed-through current which is generated when the output goes from "L" to "H" (release)
causes a voltage drop equal to [feed-through current] [input resistance] across the resistor. When the input
voltage drops below the detection voltage (VDET) as a result, the output voltage goes to "L". In this status, the
feed-through current stops and its resultant voltage drop disappears, and the output goes from "L" to "H". The
feed-through current is then generated again, a voltage drop appears, and repeating the process finally induces
oscillation.
(CMOS output product)
R
A
V
IN
GND
V
DD
R
B
VDD
CD
VSS
OUT
MR
Figure 32 Example for Bad Implementation Due to Detection Voltage Change
(RA : mo k9) 51¢ ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
25
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
In CMOS output product of the S-1003 Series, the feed-through current flows at the detection and the release. If the
input impedance is high, oscillation may occur due to the voltage drop by the feed-through current when releasing.
In CMOS output product oscillation may occur when a pull-down resistor is used, and falling speed of the power
supply voltage (VDD) is slow near the detection voltage.
When designing for mass production using an application circuit described herein, the product deviation and
temperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
As seen in Figure 33, when connecting an input resistance (RA) in Nch open-drain output product of the S-1003
Series, RA should be 100 k or less to prevent oscillation. Moreover, note that the hysteresis width may be larger
as the following equation.
Maximum hysteresis width = VHYSRA 20 A
When using the manual reset function, refer to "2. 4 When connecting resistance (RA) between power supply
voltage (VDD) and VDD pin" in " Operation" to set the constant.
(Nch open-drain output product)
GND
RA
(RA 100 k)
VDD
CD
VSS
OUT
MR
Set to VIN or GND (MR pin non-active)
VDD
VIN
Figure 33
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
26
Characteristics (Typical Data)
1. Detection voltage (VDET) vs. Temperature (Ta)
S-1003CA12
1.40
1.30
1.20
1.10
1.00
VDET [V]
40 857550250
25
Ta [ C]
+VDET
VDET
S-1003CA24
2.60
2.50
2.40
2.30
2.20
VDET [V]
40 857550250
25
Ta [ C]
+VDET
VDET
S-1003CA50
5.40
5.20
5.00
4.80
4.60
V
DET
[V]
40 857550250
25
Ta [ C]
+V
DET
V
DET
2. Hysteresis width (VHYS) vs. Temperature (Ta)
S-1003CA12
7
6
5
4
3
V
HYS
[%]
40 857550250
25
Ta [ C]
S-1003CA24
7
6
5
4
3
V
HYS
[%]
40 857550250
25
Ta [ C]
S-1003CA50
7
6
5
4
3
V
HYS
[%]
40 857550250
25
Ta [ C]
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
27
3. Current consumption (ISS) vs. Input voltage (VDD)
S-1003CA12 Ta = 25°C
1.50
1.25
1.00
0.75
0.50
0.25
0
0246810
I
SS
[μA]
V
DD
[V]
S-1003CA24 Ta = 25°C
1.50
1.25
1.00
0.75
0.50
0.25
0
0246810
I
SS
[μA]
V
DD
[V]
S-1003CA50 Ta = 25°C
1.50
1.25
1.00
0.75
0.50
0.25
0
0246810
I
SS
[μA]
V
DD
[V]
4.
Current consumption (I
SS
) vs. Temperature (Ta)
S-1003NA12 VDD = VDET(S) 1.0 V
1.00
0.75
0.50
0.25
0
I
SS
[μA]
40 857550250
25
Ta [ C]
S-1003NA24 VDD = VDET(S) 1.0 V
1.00
0.75
0.50
0.25
0
I
SS
[μA]
40 857550250
25
Ta [ C]
S-1003NA50 VDD = VDET(S) 1.0 V
1.00
0.75
0.50
0.25
0
ISS [μA]
40 857550250
25
Ta [ C]
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
28
5. Nch transistor output current (IOUT)
vs.
VDS 6. Pch transistor output current (IOUT)
vs.
VDS
S-1003NA12 Ta = 25°C, MR pin active
20.0
0
0 7.0
I
OUT
[mA]
V
DS
[V]
6.05.04.03.02.01.0
17.5
15.0
12.5
10.0
7.5
5.0
2.5
V
DD
= 6.00 V
V
DD
= 4.80 V
V
DD
= 3.60 V
V
DD
= 2.40 V
V
DD
= 1.20 V
V
DD
= 0.95 V
S-1003CA12 Ta = 25°C
40.0
0
0 10.0
IOUT [mA]
VDS [V]
30.0
20.0
10.0
2.0 4.0 6.0 8.0
VDD = 8.4 V
VDD = 7.2 V
VDD = 6.0 V
VDD = 4.8 V
VDD = 3.6 V
VDD = 2.4 V
7. Nch transistor output current (IOUT)
vs.
Input voltage (VDD)
8. Pch transistor output current (IOUT)
vs.
Input voltage (VDD)
S-1003NA12 VDS = 0.5 V, MR pin active
4.0
0
0 10.0
IOUT [mA]
VDD [V]
3.0
2.0
1.0
2.0 4.0 6.0 8.0
Ta = 40°C
Ta = +25°C
Ta = +85°C
S-1003CA12 VDS = 0.5 V
5.0
0
0 10.0
IOUT [mA]
VDD [V]
2.0 4.0 6.0 8.0
4.0
3.0
2.0
1.0
Ta = 40°C
Ta = +25°C
Ta = +85°C
Remark VDS: Drain-to-source voltage of the output transistor
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
29
9. Minimum operation voltage (VOUT)
vs.
Input voltage (VDD)
S-1003NA12 Pull-up to VDD
Pull-up resistance: 100 k
1.8
0
0 1.6
V
OUT
[V]
V
DD
[V]
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.41.21.00.80.60.40.2
Ta = 40°C
Ta = +25°C
Ta = +85°C
S-1003NA24 Pull-up to VDD
Pull-up resistance: 100 k
3.0
0
0 2.8
V
OUT
[V]
V
DD
[V]
2.5
2.0
1.5
1.0
0.5
2.42.01.61.20.80.4
Ta = 40°C
Ta = +25°C
Ta = +85°C
S-1003NA50 Pull-up to VDD
Pull-up resistance: 100 k
6.0
0
0 5.5
V
OUT
[V]
V
DD
[V]
5.0
4.0
3.0
2.0
1.0
5.04.54.03.53.02.52.01.51.00.5
Ta = 40°C
Ta = +25°C
Ta = +85°C
S-1003NA12 Pull-up to 10 V
Pull-up resistance: 100 k
12.0
0
0 1.6
V
OUT
[V]
V
DD
[V]
1.41.21.00.80.60.40.2
10.0
8.0
6.0
4.0
2.0
Ta = 40°C
Ta = +25°C
Ta = +85°C
S-1003NA24 Pull-up to 10 V
Pull-up resistance: 100 k
12.0
0
0 2.8
V
OUT
[V]
V
DD
[V]
10.0
8.0
6.0
4.0
2.0
2.42.01.61.20.80.4
Ta = 40°C
Ta = +25°C
Ta = +85°C
S-1003NA50 Pull-up to 10 V
Pull-up resistance: 100 k
12.0
0
0 5.5
VOUT [V]
VDD [V]
10.0
8.0
6.0
4.0
2.0
5.04.54.03.53.02.52.01.51.00.5
Ta = 40°C
Ta = +25°C
Ta = +85°C
ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
30
10. Dynamic response
vs.
Output pin capacitance (COUT) (CD pin; open)
S-1003CA12
0.00001
Response time [ms]
0.001
Output pin capacitance [μF]
1
0.01
0.1
0.10.0001 0.010.001
t
PLH
t
PHL
S-1003CA24
0.00001
Response time [ms]
0.001
Output pin capacitance [μF]
1
0.01
0.1
0.10.0001 0.010.001
t
PLH
t
PHL
S-1003CA50
0.00001
Response time [ms]
0.001
Output pin capacitance [μF]
1
0.01
0.1
0.10.0001 0.010.001
t
PLH
t
PHL
S-1003NA12
0.00001
Response time [ms]
0.001
Output pin capacitance [μF]
100
0.10.0001 0.010.001
0.01
0.1
10
1
t
PHL
t
PLH
S-1003NA24
0.00001
Response time [ms]
0.001
Output pin capacitance [μF]
100
0.10.0001 0.010.001
0.01
0.1
10
1
t
PHL
t
PLH
S-1003NA50
0.00001
Response time [ms]
0.001
Output pin capacitance [μF]
100
0.10.0001 0.010.001
0.01
0.1
10
1
t
PHL
t
PLH
vm;3 x 90% Output vo‘lage VDD‘3 x 10% *1. Vw : 10 V *2. Vm : 0.95 V *3. CMOS oumul product VDD Nah openrdram product. Vnm ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
31
VIH
*1
Input voltage
VIL
*2
VDD
*3
tPHL tPLH
1 s1 s
VDD
*3 10%
VDD
*3 90%
Output voltage
*1. VIH = 10 V
*2. VIL = 0.95 V
*3. CMOS output product: VDD
Nch open-drain product: VDD1
V
R
*1
100 k
C
OUT
V
DD
V
CD V
DD1*1
VDD OUT
VSS
MR
*2
*1. R and VDD1 are unnecessary for CMOS output
product.
*2. Set to VDD or GND (MR pin non-active).
Figure 34 Test Condition of Response Time Figure 35 Test Circuit of Response Time
Caution 1. The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. When the CD pin is open, a double pulse may appear at release.
To avoid the double pulse, attach a 100 pF or more capacitor to the CD pin.
Response time when detecting (tPHL) is not affected by CD pin capacitance. Besides, response
time when releasing (tPLH) can set the delay time by attaching the CD pin.
Refer to "11. Delay time (tD) vs. CD pin capacitance (CD) (Without output pin capacitance)" for
details.
11. Delay time (tD)
vs.
CD pin capacitance (CD) (Without output pin capacitance)
S-1003NA12 Ta = 25°C
0.01 0.1 1 10 100
0.01
10000
1000
1000
100
10
1
0.1
t
D
[ms]
C
D
[nF]
S-1003NA24 Ta = 25°C
0.01 0.1 1 10 100
0.01
10000
1000
1000
100
10
1
0.1
t
D
[ms]
C
D
[nF]
S-1003NA50 Ta = 25°C
0.01 0.1 1 10 100
0.01
10000
1000
1000
100
10
1
0.1
t
D
[ms]
C
D
[nF]
Inpm voltage ' VDD X 90% Oulpul vollage v55 *1. Vw : Vums, +1 0 v *2. VxL : 0.95 v 32 ABLICInc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
32
12. Delay time (tD)
vs.
Temperature (Ta)
S-1003NA12
CD = 4.7 nF, VDD = 0.95 V VDET(S) 1.0 V
12
11
10
9
8
t
D
[ms]
40 857550250
25
Ta [ C]
S-1003NA24
CD = 4.7 nF, VDD = 0.95 V VDET(S) 1.0 V
12
11
10
9
8
t
D
[ms]
40 857550250
25
Ta [ C]
S-1003NA50
CD = 4.7 nF, VDD = 0.95 V VDET(S) 1.0 V
12
11
10
9
8
tD [ms]
40 857550250
25
Ta [ C]
1 s
t
D
V
DD
90%
Input voltage
Output voltage
V
IL*2
V
SS
V
IH*1
*1. VIH = VDET(S)1.0 V
*2. VIL = 0.95 V
V
R
*1
100 k
V
DD
V
CD
VSS
VDD OUT
C
D
MR
*2
*1. R is unnecessary for CMOS output product.
*2. Set to VDD or GND (MR pin non-active).
Figure 36 Test Condition for Delay Time Figure 37 Test Circuit for Delay Time
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
‘1. MR OUT VSS CD Mmroeompuler H31 DD f GND I|r I Sel to VDD or GND (MR pm nonraclive). ABLIC Inc. -+ DD
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
Rev.1.0_03 S-1003 Series
33
Application Circuit Examples
1. Microcomputer reset circuits
In microcomputers, when the power supply voltage is lower than the guaranteed operation voltage, an unspecified
operation may be performed or the contents of the memory register may be lost. When power supply voltage
returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may
malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched
off or lowered.
Using the S-1003 Series which has the low operation voltage, a high accuracy detection voltage and hysteresis,
reset circuits can be easily constructed as seen in Figure 38 and Figure 39.
GND
V
DD
VDD
MR
CD
VSS
OUT
*1
Microcomputer
*1. Set to VDD or GND (MR pin non-active).
GND
V
DD
V
DD1
VDD
VSS
MR
CD
OUT
*1
Microcomputer
*1. Set to VDD or GND (MR pin non-active).
Figure 38 Example of Reset Circuit
(CMOS Output Product)
Figure 39 Example of Reset Circuit
(Nch Open-drain Output Product)
Caution The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
RA" (RA: 100 kn) 100 k!) VDD OUT MR VSS CD J— (Nch openrdrain oulpul producn GND Demclion vo‘lage : RA+5R5 . rVDET Hys:eresis wxdlh : RA+5R3 . sz GND RA+ Ra ABLIC Inc.
MANUAL RESET BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) HIGH-ACCURACY VOLTAGE DETECTOR
S-1003 Series Rev.1.0_03
34
2. Change of detection voltage (Nch open-drain output product only)
If there is not a product with a specified detection voltage value in the S-1003N Series, the detection voltage can be
changed by using a resistance divider or a diode, as seen in Figure 40 and Figure 41.
In Figure 40, hysteresis width also changes.
(Nch open-drain
output product)
RA*1
VIN
GND
VDD
RB
(RA 100 k)
R
100 k
VDD
CD
VSS
OUT
MR
*2
Detection voltage = RA RB
RB VDET
Hysteresis width = RA RB
RB VHYS
(Nch open-drain
output product)
V
f1
V
IN
GND
V
DD
R
100 k
VDD
CD
VSS
OUT
MR
*1
Detection voltage = Vf1 (VDET)
*1. Set to VIN or GND (MR pin non-active).
*1. RA should be 100 k or less to prevent oscillation.
*2. Set to VIN or GND (MR pin non-active).
Caution If RA and RB are large, the hysteresis width
may also be larger than the value given by
the above equation due to the feed-through
current.
Figure 40 Figure 41
Caution 1. The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.
2. Note that the hysteresis width may be larger as the following equation shows when using the
above connections. Perform thorough evaluation using the actual application to set the
constant.
Maximum hysteresis width = RA RB
RB VHYSRA 20 A
3. When using the manual reset function, refer to "2. 4 When connecting resistance (RA)
between power supply voltage (VDD) and VDD pin" in " Operation" to set the constant.
N0. MP005—A-P-SD-1.3
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
2.9±0.2
1.9±0.2
0.95±0.1
0.4±0.1
0.16 +0.1
-0.06
123
4
5
No. MP005-A-P-SD-1.3
MP005-A-P-SD-1.3
SOT235-A-PKG Dimensions
mm
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
ø1.5 +0.1
-0 2.0±0.05
ø1.0 +0.2
-0 4.0±0.1 1.4±0.2
0.25±0.1
3.2±0.2
123
45
No. MP005-A-C-SD-2.1
MP005-A-C-SD-2.1
SOT235-A-Carrier Tape
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
mm
mac 3 +0 2150 43 No. MP005.A_R_SD_1_1
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY. 3,000
No. MP005-A-R-SD-1.1
MP005-A-R-SD-1.1
SOT235-A-Reel
Enlarged drawing in the central part
mm
1.6:!) 04 1.8010 03 W (0.2)
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A-PKG Dimensions
PG006-A-P-SD-2.1
No. PG006-A-P-SD-2.1
0.2±0.05
0.48±0.02
0.08 +0.05
-0.02
0.5
1.57±0.03
123
45
6
o' 4 4 H 20 005I S ~~9~>®4~94 414444: .1 4444 4444444 44 “ - <—> 20510.05 No. PGOOB—A-C-SD—ZD
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5
1.85±0.05 0.65±0.05
0.25±0.05
mm
PG006-A-C-SD-2.0
SNT-6A-A-Carrier Tape
No. PG006-A-C-SD-2.0
+0.1
-0
1
2
4
3
56
N0. PGOOB—A—R-SD-1 .0
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
QTY.
No. PG006-A-R-SD-1.0
PG006-A-R-SD-1.0
Enlarged drawing in the central part
SNT-6A-A-Reel
5,000
mm
++<74>¢+ >'< asziaiymlfilzathmiéu="" a="">'<><75éb\ a="" fig="" 1.="" ii'y‘r-‘fwe—il="" fnie‘fid‘alo="" edbhoa‘zfi’f—dfil’ik'="" l’ailvg="" (="" t53“,="" 2.=""> FIifi-‘zkfibfl’c ( T53“, 4. EH“: " /(‘y‘7‘—°}f§fi0$§l%" E$E§Lt'< iiiifififiléfifl‘mfi="" a="">'< iimflifiéfiiflfflifi‘éfififl="" 0="" iii="" 1.="" ilwfifiifimfimn‘fififliléfi‘="" qe.="" 1‘="" efifi‘r="" fifitmlfifllll="" wflflflfilfifl)="" we’je="" 0‘03="" mm="" blt.="" 33‘="" iflmfiflrfiiflfiflfilill-‘sfllfliwfi.="" 4.="" manama:="" "snt="" fifiwfiflmfi".="" n0.="" pgoog-a-l—sd—4.="" 1="">
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-6A-A
-Land Recommendation
PG006-A-L-SD-4.1
No. PG006-A-L-SD-4.1
0.3
0.2
0.52
1.36
0.52
1
2
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.30 mm ~ 1.40 mm)
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package ( 1.30 mm ~ 1.40 mm ).
1.
2. (1.30 mm ~ 1.40 mm)
(0.25 mm min. / 0.30 mm typ.)
Disclaimers (Handling Precautions)
1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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