EPCが提供するEPC9003C Quick Start Guideのデータシート

EFFICIENI POWER CONVERSION l
Quick Start Procedure
DESCRIPTION
The EPC9003 development board is a 200 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by in-
cluding all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9003 development board does not have any current or thermal protection on board. Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
Figure 1: Block Diagram of EPC9003 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Level Shift,
Dead-time Adjust
and Gate Drive
Gate Drive
Supply
Enable
Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<170 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Efficiency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
EPC9003 – 200V DEVELOPMENT BOARD
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
EPC9003 – 200V DEVELOPMENT BOARD
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measure-
ment and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
Development Board EPC9003C
Quick Start Guide
200 V Half-Bridge with Gate Drive, Using EPC2010C
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 170 V
V
OUT
Switch Node Output Voltage 200 V
I
OUT
Switch Node Output Current 5* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 500#ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
confi uration wwth am drivers, but also an on board
Quick Start Procedure
DESCRIPTION
The EPC9003C development board is a 200 V maximum device
voltage, 5 A maximum output current, half bridge with onboard
gate drives, featuring the EPC2010C enhancement mode
(eGaN®) field effect transistor (FET). The purpose of this
development board is to simplify the evaluation process of the
EPC2010C eGaN FET by in-cluding all the critical components on
a single board that can be easily connected into any existing
converter.
The EPC9003C development board is 2” x 1.5” and contains
not only two EPC2010C eGaN FET in a half bridge
configuration with gate drivers, but also an on board
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9003 development board does not have any current or thermal protection on board. Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
Figure 1: Block Diagram of EPC9003 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Level Shift,
Dead-time Adjust
and Gate Drive
Gate Drive
Supply
Enable
Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<170 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Efficiency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
EPC9003 – 200V DEVELOPMENT BOARD
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
EPC9003 – 200V DEVELOPMENT BOARD
gate drive supply and bypass capacitors. The board contains
all critical components and layout for optimal switching
performance. There are also various probe points to
facilitate simple waveform measurement and efficiency
calculation. A complete block diagram of the circuit is given
in Figure 1.
For more information on the EPC2010Cs eGaN FET please refer
to the datasheet available from EPC at www.epc-co.com. The
data-sheet should be read in conjunction with this quick start
guide.
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
Development Board EPC9003
Quick Start Guide
200 V Half-Bridge with Gate Drive, Using EPC2010
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 170 V
V
OUT
Switch Node Output Voltage 200 V
I
OUT
Switch Node Output Current 5* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 500#ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
Quick Start Procedure
DESCRIPTION
The EPC9003 development board is a 200 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by in-
cluding all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
Development board EPC9003C is easy to set up to evaluate the performance of the EPC2010C eGaN FET. Refer to Figure 2 for proper
connect and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9003C development board showcases the EPC2010C eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003C is intended for bench evaluation with
low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating
of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE: The EPC9003C development board does not have any current or thermal protection on board.
Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
Figure 1: Block Diagram of EPC9003 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Level Shift,
Dead-time Adjust
and Gate Drive
Gate Drive
Supply
Enable
Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<170 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Efficiency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
EPC9003 – 200V DEVELOPMENT BOARD
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
EPC9003 – 200V DEVELOPMENT BOARD
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measure-
ment and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
Development Board EPC9003
Quick Start Guide
200 V Half-Bridge with Gate Drive, Using EPC2010
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 170 V
V
OUT
Switch Node Output Voltage 200 V
I
OUT
Switch Node Output Current 5* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 500#ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
Quick Start Procedure
DESCRIPTION
The EPC9003 development board is a 200 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by in-
cluding all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9003 development board does not have any current or thermal protection on board. Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
Figure 1: Block Diagram of EPC9003C Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Level Shift,
Dead-time Adjust
and Gate Drive
Gate Drive
Supply
Enable
Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<170 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Efficiency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
EPC9003 – 200V DEVELOPMENT BOARD
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
EPC9003 – 200V DEVELOPMENT BOARD
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measure-
ment and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board / Demonstration Board Notification
The EPC9003 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
Development Board EPC9003
Quick Start Guide
200 V Half-Bridge with Gate Drive, Using EPC2010
www.epc-co.com
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Contact us:
www.epc-co.com
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 170 V
V
OUT
Switch Node Output Voltage 200 V
I
OUT
Switch Node Output Current 5* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 500#ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
Rev 3.0
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
200V Half-Bridge with Gate Drive, using EPC2010
U2
SS8610BC
U5
Optional
R3 Zero
170V Max
SW OUT
GND
1
TP3
CON1
C12
0.22uF, 25V
C13
0.22uF, 25V
D3
BAV21
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
1
TP2
Keystone 5015
TP1
Keystone 5015
R1
10k
PWM1
GND
3
A
1
B
2
Y4
VDD 6
55
U1
NC7SZ00L6X R2
Zero
R14
Optional
R15
Zero
R5
470
C7
100p
D2
SDM03U40
R4
100
C6
100p
D1
SDM03U40
PWM2
1
2
J2
CON2
1
2
J9
CON2
2
P1
Optional
2
P2
Optional
GND
A
B
Y
VDD
U4
NC7SZ08L6X
7 - 12 Vdc
C10
1uF, 25V
1
2
J1
CON2
C11
1uF, 25V
VCC
VCC
C2
1uF, 25V
C3
1uF, 25V
6
2
37
4
5
LDO VREF
VSS
1VDD
U6
UCC27611
6
2
37
4
5
LDO VREF
VSS
1VDD
U7
UCC27611
C8
0.22uF,
25V
C9
0.22uF, 25V
C1
1uF, 25V
D4BAS40LP
D5BAS40LP
C18
C16
C17
0.1uF, 250V
R12zero
R11zero
VDD
VDD
R6
zero
Q1
EPC2010
Q2
EPC2010
Table 2 : Bill of Material
Item Qty Reference Part Description
1 5 C1, C2, C3, C10, C11 Capacitor, 1uF, 10%, 25V, X5R
2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0
3 4 C8, C9, C12, C13 Capacitor, 0.22uF, 10%, 16V, X7R
4 3 C16, C17, C18 Capacitor, 0.1uF, 10%, 250V, X7T
5 2 D1, D2 Schottky Diode, 30V
6 1 D3 Diode, 200V
7 2 D4, D5 Diode, 40V
8 1 J1 Connector
9 1 J2 Connector
10 1 J3, J4, J5, J6, J7, J8 Connector
11 2 Q1, Q2
12 1 R1
Manufacturer / Part #
Murata, GRM188R61E105KA12D
TDK, C1608C0G1H101J
TDK, C1005X7R1C224K
C2012X7T2E104K125AA
Diodes Inc., SDM03U40-7
Diodes Inc.,BAV21WS-7-F
Diodes Inc.,BAS40LP-7
2pins of Tyco, 4-103185-0
4pins of Tyco, 4-103185-0
FCI, 68602-224HLF
EPC, EPC2010C
Stackpole, RMCF0603FT10K0
13 2 R11, R12 Stackpole, RMCF0402ZT0R00
14 4 R2, R3, R6, R15 Stackpole, RMCF0603FT00R0
15 1 R4 Stackpole, RMCF0603FT100R
16 1 R5 Stackpole, RMCF0603FT470R
17 2 TP1, TP2 Keystone Elect, 5015
18 1 TP3 1/40th of Tyco, 4-103185-0
19 1 U1 Fairchild, NC7SZ00L6X
20 1 U2 Silicon Labs, Si8610BC
21 1 U4 Fairchild, NC7SZ08L6X
22 2 U6, U7 Texas Instruments, UCC27611
23 0 P1, P2
24 0 R13
25 0 U5
eGaN®FET
Resistor, 10.0K, 5%, 1/8W
Resistor, 0 Ohm, 1/16W
Resistor, 0 Ohm, 1/8W
Resistor, 100Ohm, 1%, 1/8W
Resistor, 470 Ohm, 1%, 1/8W
Test Point
Connector
I.C., Logic
I.C., Opto-coupler
I.C., Logic
I.C., Gate driver
Optional potentiometer
Optional resistor
Optional I.C.
w:
Rev 3.0
1
1
2
2
3
3
4
4
5
5
6
6
DD
CC
BB
AA
200V Half-Bridge with Gate Drive, using EPC2010C
U2
Si8610BC
U5
Optional
R3 Zero
170V Max
SW OUT
GND
1
TP3
CON1
C12
0.22uF, 16V
C13
0.22uF, 16V
D3
BAV21
1
2
3
4
J8
CON4
1
2
3
4
J7
CON4
1
2
3
4
J3
CON4
1
2
3
4
J4
CON4
1
2
3
4
J6
CON4
1
2
3
4
J5
CON4
1
TP2
Keystone 5015
TP1
Keystone 5015
R1
10k
PWM1
GND
3
A
1
B
2
Y4
VDD 6
55
U1
NC7SZ00L6X R2
Zero
R14
Optional
R15
Zero
R5
470
C7
100p
D2
SDM03U40
R4
100
C6
100p
D1
SDM03U40
PWM2
1
2
J2
CON2
1
2
J9
CON2
2
P1
Optional
2
P2
Optional
GND
A
B
Y
VDD
U4
NC7SZ08L6X
7 - 12 Vdc
C10
1uF, 25V
1
2
J1
CON2
C11
1uF, 25V
VCC
VCC
C2
1uF, 25V
C3
1uF, 25V
6
2
37
4
5
LDO VREF
VSS
1VDD
U6
UCC27611
6
2
37
4
5
LDO VREF
VSS
1VDD
U7
UCC27611
C8
0.22uF,
16V
C9
0.22uF, 16V
C1
1uF, 25V
D4 BAS40LP
D5 BAS40LP
C18
C16
C17
0.1uF, 250V
R12zero
R11zero
VDD
VDD
R6
zero
Q1
EPC2010C
Q2
EPC2010C
Table 2 : Bill of Material
Item Qty Reference Part Description Manufacturer / Part #
1 5 C1, C2, C3, C10, C11 Capacitor, 1uF, 10%, 25V, X5R Murata, GRM188R61E105KA12D
2 2 C6, C7 Capacitor, 100pF, 5%, 50V, NP0 TDK, C1608C0G1H101J
3 4 C8, C9, C12, C13 Capacitor, 0.22uF, 10%, 16V, X7R TDK, C1005X7R1C224K
4 3 C16, C17, C18 Capacitor, 0.1uF, 10%, 250V, X7T C2012X7T2E104K125AA
5 2 D1, D2 Schottky Diode, 30V Diodes Inc., SDM03U40-7
6 1 D3 Diode, 200V Diodes Inc.,BAV21WS-7-F
7 2 D4, D5 Diode, 40V Diodes Inc.,BAS40LP-7
8 1 J1 Connector 2pins of Tyco, 4-103185-0
9 1 J2 Connector 4pins of Tyco, 4-103185-0
10 1 J3, J4, J5, J6, J7, J8 Connector FCI, 68602-224HLF
11 2 Q1, Q2 eGaNFET EPC, EPC2010
12 1 R1 Resistor, 10.0K, 5%, 1/8W Stackpole, RMCF0603FT10K0
13 2 R11, R12 Resistor, 0 Ohm, 1/16W Stackpole, RMCF0402ZT0R00
14 4 R2, R3, R6, R15 Resistor, 0 Ohm, 1/8W Stackpole, RMCF0603FT00R0
15 1 R4 Resistor, 100Ohm, 1%, 1/8W Stackpole, RMCF0603FT100R
16 1 R5 Resistor, 470 Ohm, 1%, 1/8W Stackpole, RMCF0603FT470R
17 2 TP1, TP2 Test Point Keystone Elect, 5015
18 1 TP3 Connector 1/40th of Tyco, 4-103185-0
19 1 U1 I.C., Logic Fairchild, NC7SZ00L6X
20 1 U2 I.C., Opto-coupler Silicon Labs, Si8610BC
21 1 U4 I.C., Logic Fairchild, NC7SZ08L6X
22 2 U6, U7 I.C., Gate driver Texas Instruments, UCC27611
23 0 P1, P2 Optional potentiometer
24 0 R13 Optional resistor
25 0 U5 Optional I.C.
mmmvrnwmouvmslou I
Quick Start Procedure
DESCRIPTION
The EPC9003 development board is a 200 V maximum device volt-
age, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2010 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2010 eGaN FET by in-
cluding all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9003 development board is 2” x 1.5” and contains not
only two EPC2010 eGaN FET in a half bridge configuration
Development board EPC9003 is easy to set up to evaluate the performance of the EPC2010 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
1. With power off, connect the input power supply bus to +VIN (J5, J6) and ground / return to –VIN (J7, J8).
2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required.
3. With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 200 V on VOUT).
7. Turn on the controller / PWM input source and probe switching node to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique.
THERMAL CONSIDERATIONS
The EPC9003 development board showcases the EPC2010 eGaN FET. Although the electrical performance surpasses that for traditional Silicon
devices, their relatively smaller size does magnify the thermal management requirements. The EPC9003 is intended for bench evaluation with low
ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of
these devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
NOTE. The EPC9003 development board does not have any current or thermal protection on board. Figure 4: Waveforms for VIN = 170 V to 5 V/5 A (100kHz) Buck converter
CH1: VPWM Input voltage – CH4: (VOUT) Switch node voltage
Figure 1: Block Diagram of EPC9003 Development Board
Figure 2: Proper Connection and Measurement Setup
Figure 3: Proper Measurement of Switch Node – OUT
VDD
VIN
PWM
Input OUT
Gate Drive
Regulator
Level Shift,
Dead-time Adjust
and Gate Drive
Gate Drive
Supply
Enable
Half-Bridge with Bypass
7 V – 12 V
VDD Supply
PWM Input
External Circuit
VIN Supply
<170 V
VIN
++
+
––
–
IIN
V
A
Gate Drive Supply
(Note Polarity)
(For Efficiency
Measurement)
Switch Node
EPC
EFFICIENT POWER CONVERSION
EPC9003 – 200V DEVELOPMENT BOARD
EPC
EFFICIENT POWER CONVERSION
Do not use probe ground lead
Place probe in large via at OUTMinimize loop
Ground probe
against TP3
EPC9003 – 200V DEVELOPMENT BOARD
with gate drivers, but also an on board gate drive supply and
bypass capacitors. The board contains all critical components
and layout for optimal switching performance. There are also
various probe points to facilitate simple waveform measure-
ment and efficiency calculation. A complete block diagram of
the circuit is given in Figure 1.
For more information on the EPC2010s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The data-
sheet should be read in conjunction with this quick start guide.
Development Board EPC9003
Quick Start Guide
200 V Half-Bridge with Gate Drive, Using EPC2010
www.epc-co.com
Table 1: Performance Summary (TA = 25°C)
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
V
DD
Gate Drive Input Supply Range 7 12 V
V
IN
Bus Input Voltage Range 170 V
V
OUT
Switch Node Output Voltage 200 V
I
OUT
Switch Node Output Current 5* A
V
PWM
PWM Logic Input Voltage Threshold Input ‘High’ 3.5 6 V
Input ‘Low’ 0 1.5 V
Minimum ‘High’ State Input Pulse Width VPWM rise and fall time < 10ns 60 ns
Minimum ‘Low’ State Input Pulse Width VPWM rise and fall time < 10ns 500#ns
* Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Dependent on time needed to ‘refresh’ high side bootstrap supply voltage.
EPC Products are distributed through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9003C board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is
not designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
For More Information:
Please contact info@epc-co.com
or your local sales representative
Visit our website:
www.epc-co.com
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bit.ly/EPCupdates
or text “EPC” to 22828