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7 Series FPGA Overview Datasheet

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Datasheet

DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 1
© 2011– 2018 Xilinx, Inc. XILINX, the Xilinx logo, Artix, Virtex, Kintex, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
Introduction
Artix®-7 FPGAs are available in -3, -2, -1, -1LI, and -2L
speed grades, with -3 having the highest performance. The
Artix-7 FPGAs predominantly operate at a 1.0V core voltage.
The -1LI and -2L devices are screened for lower maximum
static power and can operate at lower core voltages for
lower dynamic power than the -1 and -2 devices,
respectively. The -1LI devices operate only at
VCCINT =V
CCBRAM = 0.95V and have the same speed
specifications as the -1 speed grade. The -2L devices can
operate at either of two VCCINT voltages, 0.9V and 1.0V and
are screened for lower maximum static power. When
operated at VCCINT = 1.0V, the speed specification of a -2L
device is the same as the -2 speed grade. When operated at
VCCINT = 0.9V, the -2L static and dynamic power is reduced.
Artix-7 FPGA DC and AC characteristics are specified in
commercial, extended, industrial, expanded (-1Q), and
military (-1M) temperature ranges. Except the operating
temperature range or unless otherwise noted, all the DC
and AC electrical parameters are the same for a particular
speed grade (that is, the timing characteristics of a -1M
speed grade military device are the same as for a -1C speed
grade commercial device). However, only selected speed
grades and/or devices are available in each temperature
range. For example, -1M is only available in the
defense-grade Artix-7Q family and -1Q is only available in
XA Artix-7 FPGAs.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parameters
included are common to popular designs and typical
applications.
Available device and package combinations can be found in
:
7 Series FPGAs Overview (DS180)
Defense-Grade 7 Series FPGAs Overview (DS185)
XA Artix-7 FPGAs Overview (DS197)
This Artix-7 FPGA data sheet, part of an overall set of
documentation on the 7 series FPGAs, is available on the
Xilinx website at www.xilinx.com/documentation.
DC Characteristics
Artix-7 FPGAs Data Sheet:
DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 Product Specification
Table 1: Absolute Maximum Ratings(1)
Symbol Description Min Max Units
FPGA Logic
VCCINT Internal supply voltage –0.5 1.1 V
VCCAUX Auxiliary supply voltage –0.5 2.0 V
VCCBRAM Supply voltage for the block RAM memories –0.5 1.1 V
VCCO Output drivers supply voltage for HR I/O banks –0.5 3.6 V
VREF Input reference voltage –0.5 2.0 V
VIN(2)(3)(4)
I/O input voltage –0.4 VCCO +0.55 V
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards
except TMDS_33(5) –0.4 2.625 V
VCCBATT Key memory battery backup supply –0.5 2.0 V
GTP Transceiver
VMGTAVCC Analog supply voltage for the GTP transmitter and receiver circuits –0.5 1.1 V
VMGTAVTT Analog supply voltage for the GTP transmitter and receiver termination circuits –0.5 1.32 V
VMGTREFCLK Reference clock absolute input voltage –0.5 1.32 V
VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 2
IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating 14 mA
IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT 12 mA
IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND 6.5 mA
IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating 14 mA
IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT 12 mA
XADC
VCCADC XADC supply relative to GNDADC –0.5 2.0 V
VREFP XADC reference input relative to GNDADC –0.5 2.0 V
Temperature
TSTG Storage temperature (ambient) –65 150 °C
TSOL
Maximum soldering temperature for Pb/Sn component bodies(6) –+220°C
Maximum soldering temperature for Pb-free component bodies(6) –+260°C
TjMaximum junction temperature(6) –+125°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. The lower absolute voltage specification always applies.
3. For I/O operation, refer to 7 Series FPGAs SelectIO Resources User Guide (UG471).
4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.
5. See Table 9 for TMDS_33 specifications.
6. For soldering guidelines and thermal considerations, see 7 Series FPGA Packaging and Pinout Specification (UG475).
Table 2: Recommended Operating Conditions(1)(2)
Symbol Description Min Typ Max Units
FPGA Logic
VCCINT(3)
For -3, -2, -2LE (1.0V), -1, -1Q, -1M devices: internal supply voltage 0.95 1.00 1.05 V
For -1LI (0.95V) devices: internal supply voltage 0.92 0.95 0.98 V
For -2LE (0.9V) devices: internal supply voltage 0.87 0.90 0.93 V
VCCAUX Auxiliary supply voltage 1.71 1.80 1.89 V
VCCBRAM(3)
For -3, -2, -2LE (1.0V), -2LE (0.9V), -1, -1Q, -1M devices: block RAM supply
voltage
0.95 1.00 1.05 V
For -1LI (0.95V) devices: block RAM supply voltage 0.92 0.95 0.98 V
VCCO(4)(5) Supply voltage for HR I/O banks 1.14 3.465 V
VIN(6)
I/O input voltage –0.20 VCCO +0.20 V
I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards
except TMDS_33(7) –0.20 – 2.625 V
IIN(8) Maximum current through any pin in a powered or unpowered bank when
forward biasing the clamp diode.
–– 10mA
VCCBATT(9) Battery voltage 1.0 1.89 V
GTP Transceiver
VMGTAVCC(10) Analog supply voltage for the GTP transmitter and receiver circuits 0.97 1.0 1.03 V
VMGTAVTT(10) Analog supply voltage for the GTP transmitter and receiver termination circuits 1.17 1.2 1.23 V
XADC
VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V
Table 1: Absolute Maximum Ratings(1) (Cont’d)
Symbol Description Min Max Units
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 3
VREFP Externally supplied reference voltage 1.20 1.25 1.30 V
Temperature
Tj
Junction temperature operating range for commercial (C) temperature devices 0 85 °C
Junction temperature operating range for extended (E) temperature devices 0 100 °C
Junction temperature operating range for industrial (I) temperature devices –40 100 °C
Junction temperature operating range for expanded (Q) temperature devices –40 125 °C
Junction temperature operating range for military (M) temperature devices –55 125 °C
Notes:
1. All voltages are relative to ground.
2. For the design of the power distribution system consult 7 Series FPGAs PCB Design and Pin Planning Guide (UG483).
3. If VCCINT and VCCBRAM are operating at the same voltage, VCCINT and VCCBRAM should be connected to the same supply.
4. Configuration data is retained even if VCCO drops to 0V.
5. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, and 3.3V at ±5%.
6. The lower absolute voltage specification always applies.
7. See Table 9 for TMDS_33 specifications.
8. A total of 200 mA per bank should not be exceeded.
9. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.
10. Each voltage listed requires the filter circuit described in 7 Series FPGAs GTP Transceiver User Guide (UG482).
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ(1) Max Units
VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 V
VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 V
IREF VREF leakage current per pin 15 µA
ILInput or output leakage current per pin (sample-tested) 15 µA
CIN(2) Die input capacitance at the pad 8 pF
IRPU
Pad pull-up (when selected) @ VIN =0V, V
CCO =3.3V 90 330 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =2.5V 68 250 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.8V 34 220 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.5V 23 150 µA
Pad pull-up (when selected) @ VIN =0V, V
CCO =1.2V 12 120 µA
IRPD Pad pull-down (when selected) @ VIN =3.3V 68 330 µA
ICCADC Analog supply current, analog circuits in powered up state 25 mA
IBATT(3) Battery supply current 150 nA
RIN_TERM(4)
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_40)
28 40 55 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_50)
35 50 65 Ω
Thevenin equivalent resistance of programmable input termination to VCCO/2
(UNTUNED_SPLIT_60)
44 60 83 Ω
Table 2: Recommended Operating Conditions(1)(2) (Cont’d)
Symbol Description Min Typ Max Units
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 4
n Temperature diode ideality factor 1.010
r Temperature diode series resistance 2 Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
4. Termination resistance to a VCCO/2 level.
Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2)
AC Voltage Overshoot % of UI @–55°C to 125°C AC Voltage Undershoot % of UI @–55°C to 125°C
VCCO + 0.55 100
–0.40 100
–0.45 61.7
–0.50 25.8
–0.55 11.0
VCCO + 0.60 46.6 –0.60 4.77
VCCO + 0.65 21.2 –0.65 2.10
VCCO + 0.70 9.75 –0.70 0.94
VCCO + 0.75 4.55 –0.75 0.43
VCCO + 0.80 2.15 –0.80 0.20
VCCO + 0.85 1.02 –0.85 0.09
VCCO + 0.90 0.49 –0.90 0.04
VCCO + 0.95 0.24 –0.95 0.02
Notes:
1. A total of 200 mA per bank should not be exceeded.
2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND 0.20V, must not exceed the values
in this table.
Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d)
Symbol Description Min Typ(1) Max Units
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 5
Table 5: Typical Quiescent Supply Current
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2 -2LE -1 -1LI -2LE
ICCINTQ Quiescent VCCINT supply current XC7A12T 48 48 48 48 43 38 mA
XC7A15T 95 95 95 95 58 66 mA
XC7A25T 48 48 48 48 43 38 mA
XC7A35T 95 95 95 95 58 66 mA
XC7A50T 95 95 95 95 58 66 mA
XC7A75T 155 155 155 155 96 108 mA
XC7A100T 155 155 155 155 96 108 mA
XC7A200T 328 328 328 328 203 232 mA
XA7A12T N/A 48 N/A 48 N/A N/A mA
XA7A15T N/A 95 N/A 95 N/A N/A mA
XA7A25T N/A 48 N/A 48 N/A N/A mA
XA7A35T N/A 95 N/A 95 N/A N/A mA
XA7A50T N/A 95 N/A 95 N/A N/A mA
XA7A75T N/A 155 N/A 155 N/A N/A mA
XA7A100T N/A 155 N/A 155 N/A N/A mA
XQ7A50T N/A 95 N/A 95 58 N/A mA
XQ7A100T N/A 155 N/A 155 96 N/A mA
XQ7A200T N/A 328 N/A 328 203 N/A mA
ICCOQ Quiescent VCCO supply current XC7A12T 1 1 1 1 1 1 mA
XC7A15T111111mA
XC7A25T111111mA
XC7A35T111111mA
XC7A50T111111mA
XC7A75T444444mA
XC7A100T 4 4 4 4 4 4 mA
XC7A200T 5 5 5 5 5 5 mA
XA7A12T N/A 1 N/A 1 N/A N/A mA
XA7A15T N/A 1 N/A 1 N/A N/A mA
XA7A25T N/A 1 N/A 1 N/A N/A mA
XA7A35T N/A 1 N/A 1 N/A N/A mA
XA7A50T N/A 1 N/A 1 N/A N/A mA
XA7A75T N/A 4 N/A 4 N/A N/A mA
XA7A100T N/A 4 N/A 4 N/A N/A mA
XQ7A50T N/A 1 N/A 1 1 N/A mA
XQ7A100T N/A 4 N/A 4 4 N/A mA
XQ7A200T N/A 5 N/A 5 5 N/A mA
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 6
ICCAUXQ Quiescent VCCAUX supply current XC7A12T 13 13 13 13 13 13 mA
XC7A15T 22 22 22 22 19 22 mA
XC7A25T 13 13 13 13 13 13 mA
XC7A35T 22 22 22 22 19 22 mA
XC7A50T 22 22 22 22 19 22 mA
XC7A75T 36 36 36 36 32 36 mA
XC7A100T 36 36 36 36 32 36 mA
XC7A200T 73 73 73 73 65 73 mA
XA7A12T N/A 13 N/A 13 N/A N/A mA
XA7A15T N/A 22 N/A 22 N/A N/A mA
XA7A25T N/A 13 N/A 13 N/A N/A mA
XA7A35T N/A 22 N/A 22 N/A N/A mA
XA7A50T N/A 22 N/A 22 N/A N/A mA
XA7A75T N/A 36 N/A 36 N/A N/A mA
XA7A100T N/A 36 N/A 36 N/A N/A mA
XQ7A50T N/A 22 N/A 22 19 N/A mA
XQ7A100T N/A 36 N/A 36 32 N/A mA
XQ7A200T N/A 73 N/A 73 65 N/A mA
Table 5: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2 -2LE -1 -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 7
ICCBRAMQ Quiescent VCCBRAM supply current XC7A12T 1 1 1 1 1 1 mA
XC7A15T222212mA
XC7A25T111111mA
XC7A35T222212mA
XC7A50T222212mA
XC7A75T444424mA
XC7A100T 4 4 4 4 2 4 mA
XC7A200T 11 11 11 11 6 11 mA
XA7A12T N/A 1 N/A 1 N/A N/A mA
XA7A15T N/A 2 N/A 2 N/A N/A mA
XA7A25T N/A 1 N/A 1 N/A N/A mA
XA7A35T N/A 2 N/A 2 N/A N/A mA
XA7A50T N/A 2 N/A 2 N/A N/A mA
XA7A75T N/A 4 N/A 4 N/A N/A mA
XA7A100T N/A 4 N/A 4 N/A N/A mA
XQ7A50T N/A 2 N/A 2 1 N/A mA
XQ7A100T N/A 4 N/A 4 2 N/A mA
XQ7A200T N/A 11 N/A 11 6 N/A mA
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperature (Tj) with single-ended SelectIO resources.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption for
conditions other than those specified.
Table 5: Typical Quiescent Supply Current (Cont’d)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2 -2LE -1 -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 8
Power-On/Off Power Supply Sequencing
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure
that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If
VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped
simultaneously. If VCCAUX and VCCO have the same recommended voltage levels then both can be powered by the same
supply and ramped simultaneously.
For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:
The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each
power-on/off cycle to maintain device reliability levels.
•The T
VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.
The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is VCCINT, VMGTAVCC,
VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended
power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.
If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-
up and power-down.
•When V
MGTAVTT is powered before VMGTAVCC and VMGTAVTT –V
MGTAVCC > 150 mV and VMGTAVCC <0.7V, the V
MGTAVTT
current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be
up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
•When V
MGTAVTT is powered before VCCINT and VMGTAVTT –V
CCINT > 150 mV and VCCINT <0.7V, the V
MGTAVTT current
draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to
0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down.
There is no recommended sequence for supplies not shown.
Table 6 shows the minimum current, in addition to ICCQ, that is required by Artix-7 devices for proper power-on and
configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied.
Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies.
Table 6: Power-On Current for Artix-7 Devices
Device ICCINTMIN ICCAUXMIN ICCOMIN ICCBRAMMIN Units
XC7A12T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XC7A15T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XC7A25T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XC7A35T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XC7A50T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XC7A75T ICCINTQ +170 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XC7A100T ICCINTQ +170 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XC7A200T ICCINTQ +340 I
CCAUXQ +50 I
CCOQ + 40 mA per bank ICCBRAMQ +80 mA
XA7A12T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XA7A15T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XA7A25T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XA7A35T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XA7A50T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XA7A75T ICCINTQ +170 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XA7A100T ICCINTQ +170 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XQ7A50T ICCINTQ +120 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 9
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH
voltage levels shown. Other standards are sample tested.
XQ7A100T ICCINTQ +170 I
CCAUXQ +40 I
CCOQ + 40 mA per bank ICCBRAMQ +60 mA
XQ7A200T ICCINTQ +340 I
CCAUXQ +50 I
CCOQ + 40 mA per bank ICCBRAMQ +80 mA
Table 7: Power Supply Ramp Time
Symbol Description Conditions Min Max Units
TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms
TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms
TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms
TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms
TVCCO2VCCAUX Allowed time per power cycle for VCCO – VCCAUX > 2.625V
TJ = 125°C(1) –300
msTJ = 100°C(1) –500
TJ = 85°C(1) –800
TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms
TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms
Notes:
1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with worst case VCCO of 3.465V.
Table 8: SelectIO DC Input and Output Levels(1)(2)
I/O Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min
HSTL_I –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00
HSTL_I_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.00 –8.00
HSTL_II –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16.00 –16.00
HSTL_II_18 –0.300 VREF – 0.100 VREF + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 16.00 –16.00
HSUL_12 –0.300 VREF – 0.130 VREF + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.10 –0.10
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO –0.400 Note 3 Note 3
LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 25% VCCO 75% VCCO Note 4 Note 4
LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO –0.450 Note 5 Note 5
LVCMOS25 –0.300 0.7 1.700 VCCO + 0.300 0.400 VCCO –0.400 Note 4 Note 4
LVCMOS33 –0.300 0.8 2.000 3.450 0.400 VCCO –0.400 Note 4 Note 4
LVTTL –0.300 0.8 2.000 3.450 0.400 2.400 Note 5 Note 5
MOBILE_DDR –0.300 20% VCCO 80% VCCO VCCO + 0.300 10% VCCO 90% VCCO 0.10 –0.10
PCI33_3 –0.400 30% VCCO 50% VCCO VCCO + 0.500 10% VCCO 90% VCCO 1.50 –0.50
SSTL135 –0.300 VREF – 0.090 VREF + 0.090 VCCO +0.300 V
CCO/2–0.150 V
CCO/2 + 0.150 13.00 –13.00
SSTL135_R –0.300 VREF – 0.090 VREF + 0.090 VCCO +0.300 V
CCO/2–0.150 V
CCO/2 + 0.150 8.90 –8.90
SSTL15 –0.300 VREF – 0.100 VREF + 0.100 VCCO +0.300 V
CCO/2–0.175 V
CCO/2 + 0.175 13.00 –13.00
Table 6: Power-On Current for Artix-7 Devices (Cont’d)
Device ICCINTMIN ICCAUXMIN ICCOMIN ICCBRAMMIN Units
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 10
SSTL15_R –0.300 VREF – 0.100 VREF + 0.100 VCCO +0.300 V
CCO/2–0.175 V
CCO/2 + 0.175 8.90 –8.90
SSTL18_I –0.300 VREF – 0.125 VREF + 0.125 VCCO +0.300 V
CCO/2–0.470 V
CCO/2 + 0.470 8.00 –8.00
SSTL18_II –0.300 VREF – 0.125 VREF + 0.125 VCCO +0.300 V
CCO/2–0.600 V
CCO/2 + 0.600 13.40 –13.40
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in HR I/O banks.
3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.
4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.
5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. For detailed interface specific DC voltage levels, see 7 Series FPGAs SelectIO Resources User Guide (UG471).
Table 9: Differential SelectIO DC Input and Output Levels
I/O Standard VICM(1) VID(2) VOCM(3) VOD(4)
V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max
BLVDS_25 0.300 1.200 1.425 0.100 1.250 Note 5
MINI_LVDS_25 0.300 1.200 VCCAUX 0.200 0.400 0.600 1.000 1.200 1.400 0.300 0.450 0.600
PPDS_25 0.200 0.900 VCCAUX 0.100 0.250 0.400 0.500 0.950 1.400 0.100 0.250 0.400
RSDS_25 0.300 0.900 1.500 0.100 0.350 0.600 1.000 1.200 1.400 0.100 0.350 0.600
TMDS_33 2.700 2.965 3.230 0.150 0.675 1.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.400 0.600 0.800
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOCM is the output common mode voltage.
4. VOD is the output differential voltage (Q – Q).
5. VOD for BLVDS will vary significantly depending on topology and loading.
Table 10: Complementary Differential SelectIO DC Input and Output Levels
I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH
V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min
DIFF_HSTL_I 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 8.00 –8.00
DIFF_HSTL_II 0.300 0.750 1.125 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSTL_II_18 0.300 0.900 1.425 0.100 0.400 VCCO–0.400 16.00 –16.00
DIFF_HSUL_12 0.300 0.600 0.850 0.100 20% VCCO 80% VCCO 0.100 –0.100
DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100 10% VCCO 90% VCCO 0.100 –0.100
DIFF_SSTL135 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 13.0 –13.0
DIFF_SSTL135_R 0.300 0.675 1.000 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.9 8.9
DIFF_SSTL15 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 13.0 –13.0
DIFF_SSTL15_R 0.300 0.750 1.125 0.100 (VCCO/2) – 0.175 (VCCO/2) + 0.175 8.9 –8.9
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 (VCCO/2) – 0.470 (VCCO/2) + 0.470 8.00 –8.00
Table 8: SelectIO DC Input and Output Levels(1)(2) (Cont’d)
I/O Standard VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 11
LVDS DC Specifications (LVDS_25)
DIFF_SSTL18_II 0.300 0.900 1.425 0.100 (VCCO/2) – 0.600 (VCCO/2) + 0.600 13.4 –13.4
Notes:
1. VICM is the input common mode voltage.
2. VID is the input differential voltage (Q – Q).
3. VOL is the single-ended low-output voltage.
4. VOH is the single-ended high-output voltage.
Table 11: LVDS_25 DC Specifications(1)
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.375 2.500 2.625 V
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals 1.675 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.700 V
VODIFF Differential Output Voltage:
(Q – Q), Q = High
(Q –Q), Q=High
RT = 100 Ω across Q and Q signals 247 350 600 mV
VOCM Output Common-Mode Voltage RT = 100 Ω across Q and Q signals 1.000 1.250 1.425 V
VIDIFF Differential Input Voltage:
(Q – Q), Q = High
(Q –Q), Q=High
100 350 600 mV
VICM Input Common-Mode Voltage 0.300 1.200 1.500 V
Notes:
1. Differential inputs for LVDS_25 can be placed in banks with VCCO levels that are different from the required level for outputs. Consult the
7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.
Table 10: Complementary Differential SelectIO DC Input and Output Levels (Cont’d)
I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH
V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 12
AC Switching Characteristics
All values represented in this data sheet are based on the speed specifications from the ISE® Design Suite and
Vivado® Design Suite as outlined in Table 12.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance Product Specification
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting
might still occur.
Preliminary Product Specification
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with
this designation are intended to give a better indication of the expected performance of production silicon. The probability
of under-reporting delays is greatly reduced as compared to Advance data.
Production Product Specification
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
Testing of AC Switching Characteristics
Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are
representative of worst-case supply voltage and junction temperature conditions.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Artix-7 FPGAs.
Table 12: Artix-7 FPGA Speed Specification Version By Device
Version In: Typical VCCINT Device
ISE 14.7 Vivado 2018.1 (Table 2)
N/A 1.21 1.0V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T
N/A 1.21 0.95V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T, XC7A100T,
XC7A200T
N/A 1.14 0.9V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T
1.10 1.21 1.0V XC7A100T, XC7A200T
1.07 1.14 0.9V XC7A100T, XC7A200T
N/A 1.15 1.0V XA7A12T, XA7A15T, XA725T, XA7A35T, XA7A50T, XA7A75T
1.07 1.15 1.0V XA7A100T
1.06 1.11 1.0V XQ7A100T, XQ7A200T
N/A 1.11 1.0V XQ7A50T
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 13
Speed Grade Designations
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Artix-7
device on a per speed grade basis.
Production Silicon and Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 14 lists the production released Artix-7 device, speed grade, and the minimum corresponding supported speed
specification version and software revisions. The software and speed specifications listed are the minimum releases required
for production. All subsequent releases of software and speed specifications are valid.
Table 13: Artix-7 Device Speed Grade Designations
Device Speed Grade Designations
Advance Preliminary Production
XC7A12T -3 -2, -1, -1LI (0.95V), and -2LE (0.9V)
XC7A15T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
XC7A25T -3 -2, -1, -1LI (0.95V), and -2LE (0.9V)
XC7A35T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
XC7A50T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
XC7A75T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
XC7A100T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
XC7A200T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V)
XA7A12T -2I, -1I, and -1Q
XA7A15T -2I, -1I, and -1Q
XA7A25T -2I, -1I, and -1Q
XA7A35T -2I, -1I, and -1Q
XA7A50T -2I, -1I, and -1Q
XA7A75T -2I, -1I, and -1Q
XA7A100T -2I, -1I, and -1Q
XQ7A50T -2I, -1I, -1LI (0.95V), and -1M
XQ7A100T -2I, -1I, -1LI (0.95V), and -1M
XQ7A200T -2I, -1I, -1LI (0.95V), and -1M
Table 14: Artix-7 Device Production Software and Speed Specification Release
Device
Speed Grade
1.0V 0.95V 0.9V
-3 -2 -2LE -1 -1Q -1M -1LI -2LE
XC7A12T Vivado tools 2017.4 v1.20 N/A N/A Vivado tools
2017.4 v1.20
Vivado tools
2018.1 v1.14
XC7A15T Vivado tools 2014.4 v1.14 N/A N/A Vivado tools
2014.4 v1.14
Vivado tools
2014.4 v1.10
XC7A25T Vivado tools 2017.4 v1.20 N/A N/A Vivado tools
2017.4 v1.20
Vivado tools
2018.1 v1.14
XC7A35T Vivado tools 2013.4 v1.11 N/A N/A Vivado tools
2014.4 v1.14
Vivado tools
2013.4 v1.08
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 14
Selecting the Correct Speed Grade and Voltage in the Vivado Tools
It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.
To select the 1.0V speed specifications in the Vivado tools, select the Artix-7, XA Artix-7, or Defense Grade Artix-7Q
sub-family, and then select the part name that is the device name followed by the package name followed by the speed
grade. For example, select the xc7a100tfgg676-3 part name for the XC7A100T device in the FGG676 package and -3 (1.0V)
speed grade or select the xc7a100tfgg676-2L part name for the XC7A100T device in the FGG676 package and -2LE (1.0V)
speed grade.
To select the -1LI (0.95V) speed specifications in the Vivado tools, select the Artix-7 sub-family and then select the part
name that is the device name followed by an “i” followed by the package name followed by the speed grade. For example,
select the xc7a100tifgg676-1L part name for the XC7A100T device in the FGG676 package and -1LI (0.95V) speed grade.
The -1LI (0.95V) speed specifications are not supported in the ISE tools.
To select the -2LE (0.9V) speed specifications in the Vivado tools, select the Artix-7 Low Voltage sub-family and then select
the part name that is the device name followed by an “l” followed by the package name followed by the speed grade. For
XC7A50T Vivado tools 2013.4 v1.11 N/A N/A Vivado tools
2014.4 v1.14
Vivado tools
2013.4 v1.08
XC7A75T Vivado tools 2013.3 v1.10 N/A N/A Vivado tools
2014.4 v1.14
Vivado tools
2013.3 v1.07
XC7A100T ISE tools 14.4 or Vivado tools 2012.4 with the
14.4/2012.4 device pack v1.07
N/A N/A Vivado tools
2014.4 v1.14 ISE tools 14.5
or Vivado tools
2013.1 v1.05
XC7A200T ISE tools 14.4 or Vivado tools 2012.4 with the
14.4/2012.4 device pack v1.07
N/A N/A Vivado tools
2014.4 v1.14
XA7A12T N/A Vivado tools
2018.1 v1.15
N/A Vivado tools 2018.1 v1.15 N/A N/A N/A
XA7A15T N/A Vivado tools
2014.4 v1.14
N/A Vivado tools 2014.4 v1.14 N/A N/A N/A
XA7A25T N/A Vivado tools
2018.1 v1.15
N/A Vivado tools 2018.1 v1.15 N/A N/A N/A
XA7A35T N/A Vivado tools
2014.1 v1.09
N/A Vivado tools 2014.1 v1.09 N/A N/A N/A
XA7A50T N/A Vivado tools
2014.1 v1.09
N/A Vivado tools 2014.1 v1.09 N/A N/A N/A
XA7A75T N/A Vivado tools
2014.1 v1.09
N/A Vivado tools 2014.1 v1.09 N/A N/A N/A
XA7A100T N/A ISE tools 14.5
or Vivado tools
2013.1 v1.05
N/A ISE tools 14.5
or Vivado tools
2013.1 v1.05
ISE tools 14.6
or Vivado tools
2013.2 v1.06
N/A N/A N/A
XQ7A50T N/A Vivado tools
2014.2 v1.08
N/A Vivado tools
2014.2 v1.08
N/A Vivado tools
2014.2 v1.08
Vivado tools
2015.4 v1.11
N/A
XQ7A100T N/A ISE tools 14.5
or Vivado tools
2013.1 v1.04
N/A ISE tools 14.5
or Vivado tools
2013.1 v1.04
N/A ISE tools 14.6
or Vivado tools
2013.2 v1.05
Vivado tools
2015.4 v1.11
N/A
XQ7A200T N/A ISE tools 14.5
or Vivado tools
2013.1 v1.04
N/A ISE tools 14.5
or Vivado tools
2013.1 v1.04
N/A ISE tools 14.6
or Vivado tools
2013.2 v1.05
Vivado tools
2015.4 v1.11
N/A
Notes:
1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
Table 14: Artix-7 Device Production Software and Speed Specification Release (Cont’d)
Device
Speed Grade
1.0V 0.95V 0.9V
-3 -2 -2LE -1 -1Q -1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 15
example, select the xc7a100tlfgg676-2L part name for the XC7A100T device in the FGG676 package and -2LE (0.9V) speed
grade.
A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See
Table 14 for the subset of 7 series FPGAs supported in the ISE tools.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Artix-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to
the same guidelines as the AC Switching Characteristics, page 12.
Table 15: Networking Applications Interface Performances
Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) 680 680 600 600 600 Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) 1250 1250 950 950 950 Mb/s
SDR LVDS receiver (SFI-4.1)(1) 680 680 600 600 600 Mb/s
DDR LVDS receiver (SPI-4.2)(1) 1250 1250 950 950 950 Mb/s
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
Table 16: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface
Generator(1)(2)
Memory Standard
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
4:1 Memory Controllers
DDR3 1066(3) 800 800 667 800 800 Mb/s
DDR3L 800 800 667 N/A 667 667 Mb/s
DDR2 800 800 667 533 667 667 Mb/s
2:1 Memory Controllers
DDR3 800 700 620 620 620 620 Mb/s
DDR3L 800 700 620 N/A 620 620 Mb/s
DDR2 800 700 620 533 620 620 Mb/s
LPDDR2 667 667 533 400 533 533 Mb/s
Notes:
1. VREF tracking is required. For more information, see 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
2. When using the internal VREF, the maximum data rate is 800 Mb/s (400 MHz).
3. The maximum PHY rate is 800 Mb/s in the CPG238 package.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 16
IOB Pad Input/Output/3-State
Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based
on standard) and 3-state delays.
•T
IOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
•T
IOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
•T
IOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM
termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used.
Table 17: IOB High Range (HR) Switching Characteristics
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE
LVTTL_S4 1.26 1.34 1.41 1.53 1.41 1.58 3.80 3.93 4.18 4.18 4.18 4.41 3.82 3.96 4.20 4.20 4.20 4.05 ns
LVTTL_S8 1.26 1.34 1.41 1.53 1.41 1.58 3.54 3.66 3.92 3.92 3.92 4.15 3.56 3.69 3.93 3.93 3.93 3.78 ns
LVTTL_S12 1.26 1.34 1.41 1.53 1.41 1.58 3.52 3.65 3.90 3.90 3.90 4.13 3.54 3.68 3.91 3.91 3.91 3.77 ns
LVTTL_S16 1.26 1.34 1.41 1.53 1.41 1.58 3.07 3.19 3.45 3.45 3.45 3.68 3.09 3.22 3.46 3.46 3.46 3.31 ns
LVTTL_S24 1.26 1.34 1.41 1.53 1.41 1.58 3.29 3.41 3.67 3.67 3.67 3.90 3.31 3.44 3.68 3.68 3.68 3.53 ns
LVTTL_F4 1.26 1.34 1.41 1.53 1.41 1.58 3.26 3.38 3.64 3.64 3.64 3.86 3.28 3.41 3.65 3.65 3.65 3.50 ns
LVTTL_F8 1.26 1.34 1.41 1.53 1.41 1.58 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns
LVTTL_F12 1.26 1.34 1.41 1.53 1.41 1.58 2.73 2.85 3.10 3.10 3.10 3.33 2.74 2.88 3.12 3.12 3.12 2.97 ns
LVTTL_F16 1.26 1.34 1.41 1.53 1.41 1.58 2.56 2.68 2.93 2.93 2.93 3.16 2.57 2.71 2.95 2.95 2.95 2.80 ns
LVTTL_F24 1.26 1.34 1.41 1.53 1.41 1.58 2.52 2.65 2.90 3.23 2.90 3.22 2.54 2.68 2.91 3.24 2.91 2.86 ns
LVDS_25 0.73 0.81 0.88 0.89 0.88 0.90 1.29 1.41 1.67 1.67 1.67 1.86 1.31 1.44 1.68 1.68 1.68 1.50 ns
MINI_LVDS_25 0.73 0.81 0.88 0.89 0.88 0.90 1.27 1.40 1.65 1.65 1.65 1.88 1.29 1.43 1.66 1.66 1.66 1.52 ns
BLVDS_25 0.73 0.81 0.88 0.88 0.88 0.90 1.84 1.96 2.21 2.76 2.21 2.44 1.85 1.99 2.23 2.77 2.23 2.08 ns
RSDS_25 (point
to point) 0.73 0.81 0.88 0.89 0.88 0.90 1.27 1.40 1.65 1.65 1.65 1.88 1.29 1.43 1.66 1.66 1.66 1.52 ns
PPDS_25 0.73 0.81 0.88 0.89 0.88 0.90 1.29 1.41 1.67 1.67 1.67 1.88 1.31 1.44 1.68 1.68 1.68 1.52 ns
TMDS_33 0.73 0.81 0.88 0.92 0.88 0.90 1.41 1.54 1.79 1.79 1.79 1.99 1.43 1.57 1.80 1.80 1.80 1.63 ns
PCI33_3 1.24 1.32 1.39 1.52 1.39 1.57 3.10 3.22 3.48 3.48 3.48 3.71 3.12 3.25 3.49 3.49 3.49 3.34 ns
HSUL_12_S 0.67 0.75 0.82 0.88 0.82 0.87 1.81 1.93 2.18 2.18 2.18 2.41 1.82 1.96 2.20 2.20 2.20 2.05 ns
HSUL_12_F 0.67 0.75 0.82 0.88 0.82 0.87 1.29 1.41 1.67 1.67 1.67 1.90 1.31 1.44 1.68 1.68 1.68 1.53 ns
DIFF_HSUL_
12_S 0.68 0.76 0.83 0.86 0.83 0.88 1.81 1.93 2.18 2.18 2.18 2.21 1.82 1.96 2.20 2.20 2.20 1.84 ns
DIFF_HSUL_
12_F 0.68 0.76 0.83 0.86 0.83 0.88 1.29 1.41 1.67 1.67 1.67 1.79 1.31 1.44 1.68 1.68 1.68 1.42 ns
MOBILE_
DDR_S 0.76 0.84 0.91 0.91 0.91 0.96 1.68 1.80 2.06 2.06 2.06 2.24 1.70 1.83 2.07 2.07 2.07 1.88 ns
MOBILE_
DDR_F 0.76 0.84 0.91 0.91 0.91 0.96 1.38 1.51 1.76 1.76 1.76 1.97 1.40 1.54 1.77 1.77 1.77 1.61 ns
DIFF_MOBILE_
DDR_S 0.70 0.78 0.85 0.85 0.85 0.87 1.70 1.82 2.07 2.07 2.07 2.24 1.71 1.85 2.09 2.09 2.09 1.88 ns
DIFF_MOBILE_
DDR_F 0.70 0.78 0.85 0.85 0.85 0.87 1.45 1.57 1.82 1.82 1.82 2.00 1.46 1.60 1.84 1.84 1.84 1.64 ns
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 17
HSTL_I_S 0.67 0.75 0.82 0.86 0.82 0.87 1.62 1.74 1.99 1.99 1.99 2.19 1.63 1.77 2.01 2.01 2.01 1.83 ns
HSTL_II_S 0.65 0.73 0.80 0.86 0.80 0.85 1.41 1.54 1.79 1.79 1.79 1.99 1.43 1.57 1.80 1.81 1.80 1.63 ns
HSTL_I_18_S 0.67 0.75 0.82 0.88 0.82 0.87 1.29 1.41 1.67 1.67 1.67 1.86 1.31 1.44 1.68 1.68 1.68 1.50 ns
HSTL_II_18_S 0.66 0.75 0.81 0.88 0.81 0.87 1.41 1.54 1.79 1.79 1.79 1.97 1.43 1.57 1.80 1.80 1.80 1.61 ns
DIFF_HSTL_I_S 0.68 0.76 0.83 0.86 0.83 0.85 1.59 1.71 1.96 1.96 1.96 2.13 1.60 1.74 1.98 1.98 1.98 1.77 ns
DIFF_HSTL_
II_S 0.68 0.76 0.83 0.86 0.83 0.85 1.51 1.63 1.88 1.88 1.88 2.07 1.52 1.66 1.90 1.90 1.90 1.70 ns
DIFF_HSTL_
I_18_S 0.71 0.79 0.86 0.86 0.86 0.87 1.38 1.51 1.76 1.76 1.76 1.96 1.40 1.54 1.77 1.77 1.77 1.59 ns
DIFF_HSTL_
II_18_S 0.70 0.78 0.85 0.88 0.85 0.87 1.46 1.58 1.84 1.84 1.84 2.00 1.48 1.61 1.85 1.85 1.85 1.64 ns
HSTL_I_F 0.67 0.75 0.82 0.86 0.82 0.87 1.10 1.22 1.48 1.49 1.48 1.69 1.12 1.25 1.49 1.51 1.49 1.33 ns
HSTL_II_F 0.65 0.73 0.80 0.86 0.80 0.85 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
HSTL_I_18_F 0.67 0.75 0.82 0.88 0.82 0.87 1.13 1.26 1.51 1.54 1.51 1.72 1.15 1.29 1.52 1.56 1.52 1.36 ns
HSTL_II_18_F 0.66 0.75 0.81 0.88 0.81 0.87 1.12 1.24 1.49 1.51 1.49 1.71 1.13 1.27 1.51 1.52 1.51 1.34 ns
DIFF_HSTL_I_F 0.68 0.76 0.83 0.86 0.83 0.85 1.18 1.30 1.56 1.56 1.56 1.77 1.20 1.33 1.57 1.57 1.57 1.41 ns
DIFF_HSTL_
II_F 0.68 0.76 0.83 0.86 0.83 0.85 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns
DIFF_HSTL_
I_18_F 0.71 0.79 0.86 0.86 0.86 0.87 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns
DIFF_HSTL_
II_18_F 0.70 0.78 0.85 0.88 0.85 0.87 1.21 1.33 1.59 1.59 1.59 1.77 1.23 1.36 1.60 1.60 1.60 1.41 ns
LVCMOS33_S4 1.26 1.34 1.41 1.52 1.41 1.62 3.80 3.93 4.18 4.18 4.18 4.41 3.82 3.96 4.20 4.20 4.20 4.05 ns
LVCMOS33_S8 1.26 1.34 1.41 1.52 1.41 1.62 3.52 3.65 3.90 3.90 3.90 4.13 3.54 3.68 3.91 3.91 3.91 3.77 ns
LVCMOS33_S12 1.26 1.34 1.41 1.52 1.41 1.62 3.09 3.21 3.46 3.46 3.46 3.69 3.10 3.24 3.48 3.48 3.48 3.33 ns
LVCMOS33_S16 1.26 1.34 1.41 1.52 1.41 1.62 3.40 3.52 3.77 3.78 3.77 4.00 3.42 3.55 3.79 3.79 3.79 3.64 ns
LVCMOS33_F4 1.26 1.34 1.41 1.52 1.41 1.62 3.26 3.38 3.64 3.64 3.64 3.86 3.28 3.41 3.65 3.65 3.65 3.50 ns
LVCMOS33_F8 1.26 1.34 1.41 1.52 1.41 1.62 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns
LVCMOS33_F12 1.26 1.34 1.41 1.52 1.41 1.62 2.56 2.68 2.93 2.93 2.93 3.16 2.57 2.71 2.95 2.95 2.95 2.80 ns
LVCMOS33_F16 1.26 1.34 1.41 1.52 1.41 1.62 2.56 2.68 2.93 3.06 2.93 3.16 2.57 2.71 2.95 3.07 2.95 2.80 ns
LVCMOS25_S4 1.12 1.20 1.27 1.38 1.27 1.43 3.13 3.26 3.51 3.51 3.51 3.72 3.15 3.29 3.52 3.52 3.52 3.36 ns
LVCMOS25_S8 1.12 1.20 1.27 1.38 1.27 1.43 2.88 3.01 3.26 3.26 3.26 3.49 2.90 3.04 3.27 3.27 3.27 3.13 ns
LVCMOS25_S12 1.12 1.20 1.27 1.38 1.27 1.43 2.48 2.60 2.85 2.85 2.85 3.08 2.49 2.63 2.87 2.87 2.87 2.72 ns
LVCMOS25_S16 1.12 1.20 1.27 1.38 1.27 1.43 2.82 2.94 3.20 3.20 3.20 3.43 2.84 2.97 3.21 3.21 3.21 3.06 ns
LVCMOS25_F4 1.12 1.20 1.27 1.38 1.27 1.43 2.74 2.87 3.12 3.12 3.12 3.35 2.76 2.90 3.13 3.13 3.13 2.99 ns
LVCMOS25_F8 1.12 1.20 1.27 1.38 1.27 1.43 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns
LVCMOS25_F12 1.12 1.20 1.27 1.38 1.27 1.43 2.16 2.29 2.54 2.54 2.54 2.77 2.18 2.32 2.55 2.56 2.55 2.41 ns
LVCMOS25_F16 1.12 1.20 1.27 1.38 1.27 1.43 2.01 2.13 2.39 2.63 2.39 2.61 2.03 2.16 2.40 2.65 2.40 2.25 ns
LVCMOS18_S4 0.74 0.83 0.89 0.97 0.89 0.94 1.62 1.74 1.99 1.99 1.99 2.19 1.63 1.77 2.01 2.01 2.01 1.83 ns
LVCMOS18_S8 0.74 0.83 0.89 0.97 0.89 0.94 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns
LVCMOS18_S12 0.74 0.83 0.89 0.97 0.89 0.94 2.18 2.30 2.56 2.56 2.56 2.79 2.20 2.33 2.57 2.57 2.57 2.42 ns
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 18
LVCMOS18_S16 0.74 0.83 0.89 0.97 0.89 0.94 1.52 1.65 1.90 1.90 1.90 2.13 1.54 1.68 1.91 1.91 1.91 1.77 ns
LVCMOS18_S24 0.74 0.83 0.89 0.97 0.89 0.94 1.60 1.72 1.98 2.40 1.98 2.21 1.62 1.75 1.99 2.41 1.99 1.84 ns
LVCMOS18_F4 0.74 0.83 0.89 0.97 0.89 0.94 1.45 1.57 1.82 1.82 1.82 2.05 1.46 1.60 1.84 1.84 1.84 1.69 ns
LVCMOS18_F8 0.74 0.83 0.89 0.97 0.89 0.94 1.68 1.80 2.06 2.06 2.06 2.29 1.70 1.83 2.07 2.07 2.07 1.92 ns
LVCMOS18_F12 0.74 0.83 0.89 0.97 0.89 0.94 1.68 1.80 2.06 2.06 2.06 2.29 1.70 1.83 2.07 2.07 2.07 1.92 ns
LVCMOS18_F16 0.74 0.83 0.89 0.97 0.89 0.94 1.40 1.52 1.77 1.78 1.77 2.00 1.42 1.55 1.79 1.79 1.79 1.64 ns
LVCMOS18_F24 0.74 0.83 0.89 0.97 0.89 0.94 1.34 1.46 1.71 2.28 1.71 1.94 1.35 1.49 1.73 2.29 1.73 1.58 ns
LVCMOS15_S4 0.77 0.86 0.93 0.96 0.93 0.98 2.05 2.18 2.43 2.43 2.43 2.50 2.07 2.21 2.45 2.45 2.45 2.14 ns
LVCMOS15_S8 0.77 0.86 0.93 0.96 0.93 0.98 2.09 2.21 2.46 2.46 2.46 2.69 2.10 2.24 2.48 2.48 2.48 2.33 ns
LVCMOS15_S12 0.77 0.86 0.93 0.96 0.93 0.98 1.59 1.71 1.96 1.96 1.96 2.19 1.60 1.74 1.98 1.98 1.98 1.83 ns
LVCMOS15_S16 0.77 0.86 0.93 0.96 0.93 0.98 1.59 1.71 1.96 1.96 1.96 2.19 1.60 1.74 1.98 1.98 1.98 1.83 ns
LVCMOS15_F4 0.77 0.86 0.93 0.96 0.93 0.98 1.85 1.97 2.23 2.23 2.23 2.27 1.87 2.00 2.24 2.24 2.24 1.91 ns
LVCMOS15_F8 0.77 0.86 0.93 0.96 0.93 0.98 1.60 1.72 1.98 1.98 1.98 2.21 1.62 1.75 1.99 1.99 1.99 1.84 ns
LVCMOS15_F12 0.77 0.86 0.93 0.96 0.93 0.98 1.35 1.47 1.73 1.73 1.73 1.96 1.37 1.50 1.74 1.74 1.74 1.59 ns
LVCMOS15_F16 0.77 0.86 0.93 0.96 0.93 0.98 1.34 1.46 1.71 2.07 1.71 1.94 1.35 1.49 1.73 2.09 1.73 1.58 ns
LVCMOS12_S4 0.87 0.95 1.02 1.19 1.02 1.08 2.57 2.69 2.95 2.95 2.95 3.18 2.59 2.72 2.96 2.96 2.96 2.81 ns
LVCMOS12_S8 0.87 0.95 1.02 1.19 1.02 1.08 2.09 2.21 2.46 2.46 2.46 2.69 2.10 2.24 2.48 2.48 2.48 2.33 ns
LVCMOS12_S12 0.87 0.95 1.02 1.19 1.02 1.08 1.79 1.91 2.17 2.17 2.17 2.40 1.81 1.94 2.18 2.18 2.18 2.03 ns
LVCMOS12_F4 0.87 0.95 1.02 1.19 1.02 1.08 1.98 2.10 2.35 2.35 2.35 2.58 1.99 2.13 2.37 2.37 2.37 2.22 ns
LVCMOS12_F8 0.87 0.95 1.02 1.19 1.02 1.08 1.54 1.66 1.92 1.92 1.92 2.15 1.56 1.69 1.93 1.93 1.93 1.78 ns
LVCMOS12_F12 0.87 0.95 1.02 1.19 1.02 1.08 1.38 1.51 1.76 1.76 1.76 1.97 1.40 1.54 1.77 1.77 1.77 1.61 ns
SSTL135_S 0.67 0.75 0.82 0.88 0.82 0.87 1.35 1.47 1.73 1.73 1.73 1.93 1.37 1.50 1.74 1.74 1.74 1.56 ns
SSTL15_S 0.60 0.68 0.75 0.75 0.75 0.80 1.30 1.43 1.68 1.71 1.68 1.88 1.32 1.46 1.69 1.73 1.69 1.52 ns
SSTL18_I_S 0.67 0.75 0.82 0.86 0.82 0.87 1.67 1.79 2.04 2.04 2.04 2.24 1.68 1.82 2.06 2.06 2.06 1.88 ns
SSTL18_II_S 0.67 0.75 0.82 0.88 0.82 0.85 1.31 1.43 1.68 1.68 1.68 1.91 1.32 1.46 1.70 1.70 1.70 1.55 ns
DIFF_SSTL135_
S0.68 0.76 0.83 0.88 0.83 0.87 1.35 1.47 1.73 1.73 1.73 1.93 1.37 1.50 1.74 1.74 1.74 1.56 ns
DIFF_SSTL15_
S0.68 0.76 0.83 0.88 0.83 0.87 1.30 1.43 1.68 1.71 1.68 1.88 1.32 1.46 1.69 1.73 1.69 1.52 ns
DIFF_SSTL18
_I_S 0.71 0.79 0.86 0.88 0.86 0.87 1.68 1.80 2.06 2.06 2.06 2.24 1.70 1.83 2.07 2.07 2.07 1.88 ns
DIFF_SSTL18
_II_S 0.71 0.79 0.86 0.88 0.86 0.87 1.38 1.51 1.76 1.76 1.76 1.94 1.40 1.54 1.77 1.77 1.77 1.58 ns
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 19
Table 18 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the
output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from
IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the
INTERMDISABLE pin is used.
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 19 shows the test setup parameters used for measuring input delay.
SSTL135_F 0.67 0.75 0.82 0.88 0.82 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
SSTL15_F 0.60 0.68 0.75 0.75 0.75 0.80 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns
SSTL18_I_F 0.67 0.75 0.82 0.86 0.82 0.87 1.12 1.24 1.49 1.53 1.49 1.72 1.13 1.27 1.51 1.54 1.51 1.36 ns
SSTL18_II_F 0.67 0.75 0.82 0.88 0.82 0.85 1.12 1.24 1.49 1.51 1.49 1.71 1.13 1.27 1.51 1.52 1.51 1.34 ns
DIFF_SSTL135
_F 0.68 0.76 0.83 0.88 0.83 0.87 1.12 1.24 1.49 1.49 1.49 1.71 1.13 1.27 1.51 1.51 1.51 1.34 ns
DIFF_SSTL15_F 0.68 0.76 0.83 0.88 0.83 0.87 1.07 1.19 1.45 1.45 1.45 1.68 1.09 1.22 1.46 1.46 1.46 1.31 ns
DIFF_SSTL18_I
_F 0.71 0.79 0.86 0.88 0.86 0.87 1.23 1.35 1.60 1.60 1.60 1.80 1.24 1.38 1.62 1.62 1.62 1.44 ns
DIFF_SSTL18_II
_F 0.71 0.79 0.86 0.88 0.86 0.87 1.21 1.33 1.59 1.59 1.59 1.79 1.23 1.36 1.60 1.60 1.60 1.42 ns
Table 18: IOB 3-state Output Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
TIOTPHZ T input to pad high-impedance 2.06 2.19 2.37 2.37 2.37 2.03 ns
TIOIBUFDISABLE IBUF turn-on time from IBUFDISABLE to O
output
2.11 2.30 2.60 2.60 2.60 2.17 ns
Table 19: Input Delay Measurement Methodology
Description I/O Standard Attribute VL(1) VH(1) VMEAS
(3)(5)
VREF
(2)(4)
LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6
LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75
LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9
LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25
LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65
LVTTL, 3.3V LVTTL 0.1 3.2 1.65
MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9
PCI33, 3.3V PCI33_3 0.1 3.2 1.65
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 VREF –0.5 V
REF +0.5 V
REF 0.60
Table 17: IOB High Range (HR) Switching Characteristics (Cont’d)
I/O Standard
TIOPI TIOOP TIOTP
Units
Speed Grade Speed Grade Speed Grade
1.0V 0.95V 0.9V 1.0V 0.95V 0.9V 1.0V 0.95V 0.9V
-3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE -3 -2/
-2LE -1 -1Q/
-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 20
HSTL, Class I & II, 1.5V HSTL_I, HSTL_II VREF –0.65 V
REF +0.65 V
REF 0.75
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF –0.8 V
REF +0.8 V
REF 0.90
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 VREF –0.5 V
REF +0.5 V
REF 0.60
SSTL, 1.35V SSTL135, SSTL135_R VREF – 0.575 VREF + 0.575 VREF 0.675
SSTL, 1.5V SSTL15, SSTL15_R VREF –0.65 V
REF +0.65 V
REF 0.75
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF –0.8 V
REF +0.8 V
REF 0.90
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 0.9 – 0.125 0.9 + 0.125 0(5)
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 0.6 – 0.125 0.6 + 0.125 0(5)
DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I,
DIFF_HSTL_II
0.75 – 0.125 0.75 + 0.125 0(5)
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18,
DIFF_HSTL_II_18
0.9 – 0.125 0.9 + 0.125 0(5)
DIFF_HSUL, 1.2V DIFF_HSUL_12 0.6 – 0.125 0.6 + 0.125 0(5)
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135,
DIFF_SSTL135_R
0.675 – 0.125 0.675 + 0.125 0(5)
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15,
DIFF_SSTL15_R
0.75 – 0.125 0.75 + 0.125 0(5)
DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I,
DIFF_SSTL18_II
0.9 – 0.125 0.9 + 0.125 0(5)
LVDS_25, 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(5)
BLVDS_25, 2.5V BLVDS_25 1.25 – 0.125 1.25 + 0.125 0(5)
MINI_LVDS_25, 2.5V MINI_LVDS_25 1.25 – 0.125 1.25 + 0.125 0(5)
PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(5)
RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0(5)
TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0(5)
Notes:
1. Input waveform switches between VLand VH.
2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
3. Input voltage level from which measurement starts.
4. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 1.
5. The value given is the differential input voltage.
Table 19: Input Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute VL(1) VH(1) VMEAS
(3)(5)
VREF
(2)(4)
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 21
Output Delay Measurements
Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay
of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the
generalized test setups shown in Figure 1 and Figure 2.
Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction
of propagation delay in any given application can be obtained through IBIS simulation, using this method:
1. Simulate the output driver of choice into the generalized test setup using values from Table 20.
2. Record the time to VMEAS.
3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance
value to represent the load.
4. Record the time to VMEAS.
5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the
PCB trace.
X-Ref Target - Figure 1
Figure 1: Single-Ended Test Setup
X-Ref Target - Figure 2
Figure 2: Differential Test Setup
Table 20: Output Delay Measurement Methodology
Description I/O Standard Attribute RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0
LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
PCI33, 3.3V PCI33_3 25 10 1.65 0
VREF
RREF
VMEAS
(Voltage Level When Taking
Delay Measurement)
CREF
(Probe Capacitance)
FPGA Output
DS181_04_090514
RREF VMEAS
+
CREF
FPGA Output
DS181_05_090514
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 22
HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 VREF 0.6
HSTL, Class I, 1.5V HSTL_I 50 0 VREF 0.75
HSTL, Class II, 1.5V HSTL_II 25 0 VREF 0.75
HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9
HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 VREF 0.6
SSTL12, 1.2V SSTL12 50 0 VREF 0.6
SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 VREF 0.675
SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 VREF 0.75
SSTL (Stub Series Terminated Logic),
Class I & Class II, 1.8V
SSTL18_I, SSTL18_II 50 0 VREF 0.9
DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 VREF 0.9
DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6
DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 VREF 0.75
DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 VREF 0.9
DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 VREF 0.6
DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 VREF 0.675
DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 VREF 0.75
DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9
LVDS, 2.5V LVDS_25 100 0 0(2) 0
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0
Mini LVDS, 2.5V MINI_LVDS_25 100 0 0(2) 0
PPDS_25 PPDS_25 100 0 0(2) 0
RSDS_25 RSDS_25 100 0 0(2) 0
TMDS_33 TMDS_33 50 0 0(2) 3.3
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
Table 20: Output Delay Measurement Methodology (Cont’d)
Description I/O Standard Attribute RREF
(Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 23
Input/Output Logic Switching Characteristics
Table 21: ILOGIC Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold
TICE1CK/
TICKCE1
CE1 pin setup/hold with respect to
CLK
0.48/0.02 0.54/0.02 0.76/0.02 0.76/0.02 0.76/0.02 0.50/–0.07 ns
TISRCK/
TICKSR
SR pin setup/hold with respect to
CLK
0.60/0.01 0.70/0.01 1.13/0.01 1.13/0.01 1.13/0.01 0.88/–0.35 ns
TIDOCK/
TIOCKD
D pin setup/hold with respect to CLK
without Delay
0.01/0.27 0.01/0.29 0.01/0.33 0.01/0.33 0.01/0.33 0.01/0.33 ns
TIDOCKD/
TIOCKDD
DDLY pin setup/hold with respect to
CLK (using IDELAY)
0.02/0.27 0.02/0.29 0.02/0.33 0.02/0.33 0.02/0.33 0.01/0.33 ns
Combinatorial
TIDI D pin to O pin propagation delay, no
Delay
0.11 0.11 0.13 0.13 0.13 0.14 ns
TIDID DDLY pin to O pin propagation delay
(using IDELAY)
0.11 0.12 0.14 0.14 0.14 0.15 ns
Sequential Delays
TIDLO D pin to Q1 pin using flip-flop as a
latch without Delay
0.41 0.44 0.51 0.51 0.51 0.54 ns
TIDLOD DDLY pin to Q1 pin using flip-flop as
a latch (using IDELAY)
0.41 0.44 0.51 0.51 0.51 0.55 ns
TICKQ CLK to Q outputs 0.53 0.57 0.66 0.66 0.66 0.71 ns
TRQ_
ILOGIC
SR pin to OQ/TQ out 0.96 1.08 1.32 1.32 1.32 1.32 ns
TGSRQ_
ILOGIC
Global set/reset to Q outputs 7.60 7.60 10.51 10.51 10.51 11.39 ns
Set/Reset
TRPW_
ILOGIC
Minimum pulse width, SR inputs 0.61 0.72 0.72 0.72 0.72 0.72 ns, Min
Table 22: OLOGIC Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold
TODCK/
TOCKD
D1/D2 pins setup/hold with respect
to CLK
0.67/–0.11 0.71/–0.11 0.84/–0.11 0.84/–0.06 0.84/–0.11 0.64/0.03 ns
TOOCECK/
TOCKOCE
OCE pin setup/hold with respect to
CLK
0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.51/0.58 0.28/0.01 ns
TOSRCK/
TOCKSR
SR pin setup/hold with respect to
CLK
0.37/0.21 0.44/0.21 0.80/0.21 0.80/0.21 0.80/0.21 0.62/–0.25 ns
TOTCK/
TOCKT
T1/T2 pins setup/hold with respect to
CLK
0.69/–0.14 0.73/–0.14 0.89/–0.14 0.89/–0.11 0.89/–0.14 0.66/0.02 ns
TOTCECK/
TOCKTCE
TCE pin setup/hold with respect to
CLK
0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.51/0.01 0.24/0.05 ns
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 24
Input Serializer/Deserializer Switching Characteristics
Combinatorial
TODQ D1 to OQ out or T1 to TQ out 0.83 0.96 1.16 1.16 1.16 1.36 ns
Sequential Delays
TOCKQ CLK to OQ/TQ out 0.47 0.49 0.56 0.56 0.56 0.63 ns
TRQ_OLOGIC SR pin to OQ/TQ out 0.72 0.80 0.95 0.95 0.95 1.12 ns
TGSRQ_OLOGIC Global set/reset to Q outputs 7.60 7.60 10.51 10.51 10.51 11.39 ns
Set/Reset
TRPW_OLOGIC Minimum pulse width, SR inputs 0.64 0.74 0.74 0.74 0.74 0.74 ns,
Min
Table 23: ISERDES Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold for Control Lines
TISCCK_BITSLIP/
TISCKC_BITSLIP
BITSLIP pin setup/hold with
respect to CLKDIV
0.01/0.14 0.02/0.15 0.02/0.17 0.02/0.17 0.02/0.17 0.02/0.21 ns
TISCCK_CE /
TISCKC_CE(2)
CE pin setup/hold with respect to
CLK (for CE1)
0.45/–0.01 0.50/–0.01 0.72/–0.01 0.72/–0.01 0.72/–0.01 0.45/–0.11 ns
TISCCK_CE2 /
TISCKC_CE2(2)
CE pin setup/hold with respect to
CLKDIV (for CE2)
–0.10/0.33 –0.10/0.36 –0.10/0.40 –0.10/0.40 –0.10/0.40 –0.17/0.40 ns
Setup/Hold for Data Lines
TISDCK_D /
TISCKD_D
D pin setup/hold with respect to
CLK
–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19 ns
TISDCK_DDLY /
TISCKD_DDLY
DDLY pin setup/hold with respect
to CLK (using IDELAY)(1) –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.03/0.19 ns
TISDCK_D_DDR /
TISCKD_D_DDR
D pin setup/hold with respect to
CLK at DDR mode
–0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.02/0.17 –0.04/0.19 ns
TISDCK_DDLY_DDR/
TISCKD_DDLY_DDR
D pin setup/hold with respect to
CLK at DDR mode (using
IDELAY)(1)
0.12/0.12 0.14/0.14 0.17/0.17 0.17/0.17 0.17/0.17 0.19/0.19 ns
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.53 0.54 0.66 0.66 0.66 0.67 ns
Propagation Delays
TISDO_DO D input to DO output pin 0.11 0.11 0.13 0.13 0.13 0.14 ns
Notes:
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report.
Table 22: OLOGIC Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 25
Output Serializer/Deserializer Switching Characteristics
Table 24: OSERDES Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup/Hold
TOSDCK_D/
TOSCKD_D
D input setup/hold with respect to
CLKDIV
0.42/0.03 0.45/0.03 0.63/0.03 0.63/0.08 0.63/0.03 0.44/–0.02 ns
TOSDCK_T/
TOSCKD_T(1)
T input setup/hold with respect to
CLK
0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.13 0.88/–0.13 0.66/–0.25 ns
TOSDCK_T2/
TOSCKD_T2(1) T input setup/hold with respect to
CLKDIV
0.31/–0.13 0.34/–0.13 0.39/–0.13 0.39/–0.13 0.39/–0.13 0.46/–0.25 ns
TOSCCK_OCE/
TOSCKC_OCE
OCE input setup/hold with respect
to CLK
0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.51/0.58 0.28/–0.04 ns
TOSCCK_S SR (reset) input setup with respect
to CLKDIV
0.47 0.52 0.85 0.85 0.85 0.70 ns
TOSCCK_TCE/
TOSCKC_TCE
TCE input setup/hold with respect
to CLK
0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.51/0.01 0.24/0.00 ns
Sequential Delays
TOSCKO_OQ Clock to out from CLK to OQ 0.40 0.42 0.48 0.48 0.48 0.54 ns
TOSCKO_TQ Clock to out from CLK to TQ 0.47 0.49 0.56 0.56 0.56 0.63 ns
Combinatorial
TOSDO_TTQ T input to TQ Out 0.83 0.92 1.11 1.11 1.11 1.18 ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 26
Input/Output Delay Switching Characteristics
Table 25: Input/Output Delay Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
IDELAYCTRL
TDLYCCO_RDY Reset to ready for IDELAYCTRL 3.67 3.67 3.67 3.67 3.67 3.67 µs
FIDELAYCTRL_REF Attribute REFCLK
frequency = 200.00(1) 200.00 200.00 200.00 200.00 200.00 200.00 MHz
Attribute REFCLK
frequency = 300.00(1)
300.00 300.00 300.00 300.00 300.00 300.00 MHz
Attribute REFCLK
frequency = 400.00(1)
400.00 400.00 N/A N/A N/A N/A MHz
IDELAYCTRL_REF_
PRECISION REFCLK precision ±10 ±10 ±10 ±10 ±10 ±10 MHz
TIDELAYCTRL_RPW Minimum Reset pulse width 59.28 59.28 59.28 59.28 59.28 59.28 ns
IDELAY
TIDELAYRESOLUTION IDELAY chain delay resolution 1/(32 x 2 x FREFs
TIDELAYPAT_JIT
Pattern dependent period jitter in
delay chain for clock pattern.(2) 000000ps
per tap
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)(3)
±5 ±5 ±5 ±5 ±5 ±5 ps
per tap
Pattern dependent period jitter in
delay chain for random data
pattern (PRBS 23)(4)
±9 ±9 ±9 ±9 ±9 ±9 ps
per tap
TIDELAY_CLK_MAX Maximum frequency of CLK input
to IDELAY
680.00 680.00 600.00 600.00 600.00 520.00 MHz
TIDCCK_CE /
TIDCKC_CE
CE pin setup/hold with respect to
C for IDELAY
0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 0.21/0.16 0.14/0.16 ns
TIDCCK_INC/
TIDCKC_INC
INC pin setup/hold with respect to
C for IDELAY
0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 0.16/0.22 0.10/0.23 ns
TIDCCK_RST/
TIDCKC_RST
RST pin setup/hold with respect
to C for IDELAY
0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 0.18/0.14 0.22/0.19 ns
TIDDO_IDATAIN Propagation delay through
IDELAY
Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE.
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IDELAY tap setting. See the timing report for actual values.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 27
Table 26: IO_FIFO Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
IO_FIFO Clock to Out Delays
TOFFCKO_DO RDCLK to Q outputs 0.55 0.60 0.68 0.68 0.68 0.81 ns
TCKO_FLAGS Clock to IO_FIFO flags 0.55 0.61 0.77 0.77 0.77 0.79 ns
Setup/Hold
TCCK_D/TCKC_D D inputs to WRCLK 0.47/0.02 0.51/0.02 0.58/0.02 0.58/0.18 0.58/0.02 0.76/0.09 ns
TIFFCCK_WREN/
TIFFCKC_WREN
WREN to WRCLK 0.42/–0.01 0.47/–0.01 0.53/–0.01 0.53/–0.01 0.53/–0.01 0.70/–0.05 ns
TOFFCCK_RDEN/
TOFFCKC_RDEN
RDEN to RDCLK 0.53/0.02 0.58/0.02 0.66/0.02 0.66/0.02 0.66/0.02 0.79/–0.02 ns
Minimum Pulse Width
TPWH_IO_FIFO RESET, RDCLK, WRCLK 1.62 2.15 2.15 2.15 2.15 2.15 ns
TPWL_IO_FIFO RESET, RDCLK, WRCLK 1.62 2.15 2.15 2.15 2.15 2.15 ns
Maximum Frequency
FMAX RDCLK and WRCLK 266.67 200.00 200.00 200.00 200.00 200.00 MHz
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 28
CLB Switching Characteristics
Table 27: CLB Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Combinatorial Delays
TILO An – Dn LUT address to A 0.10 0.11 0.13 0.13 0.13 0.15 ns, Max
TILO_2 An – Dn LUT address to
AMUX/CMUX
0.27 0.30 0.36 0.36 0.36 0.41 ns, Max
TILO_3 An – Dn LUT address to BMUX_A 0.42 0.46 0.55 0.55 0.55 0.65 ns, Max
TITO An – Dn inputs to A – D Q outputs 0.94 1.05 1.27 1.27 1.27 1.51 ns, Max
TAXA AX inputs to AMUX output 0.62 0.69 0.84 0.84 0.84 1.01 ns, Max
TAXB AX inputs to BMUX output 0.58 0.66 0.83 0.83 0.83 0.98 ns, Max
TAXC AX inputs to CMUX output 0.60 0.68 0.82 0.82 0.82 0.98 ns, Max
TAXD AX inputs to DMUX output 0.68 0.75 0.90 0.90 0.90 1.08 ns, Max
TBXB BX inputs to BMUX output 0.51 0.57 0.69 0.69 0.69 0.82 ns, Max
TBXD BX inputs to DMUX output 0.62 0.69 0.82 0.82 0.82 0.99 ns, Max
TCXC CX inputs to CMUX output 0.42 0.48 0.58 0.58 0.58 0.69 ns, Max
TCXD CX inputs to DMUX output 0.53 0.59 0.71 0.71 0.71 0.86 ns, Max
TDXD DX inputs to DMUX output 0.52 0.58 0.70 0.70 0.70 0.84 ns, Max
Sequential Delays
TCKO Clock to AQ – DQ outputs 0.40 0.44 0.53 0.53 0.53 0.62 ns, Max
TSHCKO Clock to AMUX – DMUX outputs 0.47 0.53 0.66 0.66 0.66 0.73 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TAS/TAH AN – DN input to CLK on A – D
flip-flops
0.07/0.12 0.09/0.14 0.11/0.18 0.11/0.28 0.11/0.18 0.11/0.22 ns, Min
TDICK/
TCKDI
AX–D
X input to CLK on A – D
flip-flops
0.06/0.19 0.07/0.21 0.09/0.26 0.09/0.35 0.09/0.26 0.09/0.33 ns, Min
AX–D
X input through MUXs and/or
carry logic to CLK on A – D
flip-flops
0.59/0.08 0.66/0.09 0.81/0.11 0.81/0.20 0.81/0.11 0.97/0.15 ns, Min
TCECK_CLB/
TCKCE_CLB
CE input to CLK on A – D flip-flops 0.15/0.00 0.17/0.00 0.21/0.01 0.21/0.13 0.21/0.01 0.34/–0.01 ns, Min
TSRCK/
TCKSR
SR input to CLK on A – D flip-flops 0.38/0.03 0.43/0.04 0.53/0.05 0.53/0.18 0.53/0.05 0.62/0.19 ns, Min
Set/Reset
TSRMIN SR input minimum pulse width 0.52 0.78 1.04 1.04 1.04 0.95 ns, Min
TRQ Delay from SR input to AQ – DQ
flip-flops
0.53 0.59 0.71 0.71 0.71 0.83 ns, Max
TCEO Delay from CE input to AQ – DQ
flip-flops
0.52 0.58 0.70 0.70 0.70 0.83 ns, Max
FTOG Toggle frequency (for export
control)
1412 1286 1098 1098 1098 1098 MHz
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 29
CLB Distributed RAM Switching Characteristics (SLICEM Only)
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 28: CLB Distributed RAM Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Sequential Delays
TSHCKO Clock to A – B outputs 0.98 1.09 1.32 1.32 1.32 1.54 ns, Max
TSHCKO_1 Clock to AMUX – BMUX outputs 1.37 1.53 1.86 1.86 1.86 2.18 ns, Max
Setup and Hold Times Before/After Clock CLK
TDS_LRAM/
TDH_LRAM
A – D inputs to CLK 0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 0.72/0.35 0.96/0.40 ns, Min
TAS_LRAM/
TAH_LRAM
Address An inputs to clock 0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 0.37/0.70 0.43/0.71 ns, Min
Address An inputs through MUXs
and/or carry logic to clock
0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 0.94/0.26 1.11/0.31 ns, Min
TWS_LRAM/
TWH_LRAM
WE input to clock 0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 0.53/0.17 0.62/0.13 ns, Min
TCECK_LRAM/
TCKCE_LRAM
CE input to CLK 0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 0.53/0.17 0.63/0.12 ns, Min
Clock CLK
TMPW_LRAM Minimum pulse width 1.05 1.131.251.251.251.61ns, Min
TMCP Minimum clock period 2.10 2.26 2.50 2.50 2.50 3.21 ns, Min
Notes:
1. TSHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.
Table 29: CLB Shift Register Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Sequential Delays
TREG Clock to A – D outputs 1.19 1.33 1.61 1.61 1.61 1.89 ns, Max
TREG_MUX Clock to AMUX – DMUX output 1.58 1.77 2.15 2.15 2.15 2.53 ns, Max
TREG_M31 Clock to DMUX output via M31
output
1.12 1.23 1.46 1.46 1.46 1.68 ns, Max
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG/
TWH_SHFREG
WE input 0.37/0.10 0.41/0.12 0.51/0.17 0.51/0.17 0.51/0.17 0.59/0.13 ns, Min
TCECK_SHFREG/
TCKCE_SHFREG
CE input to CLK 0.37/0.10 0.42/0.11 0.52/0.17 0.52/0.17 0.52/0.17 0.60/0.12 ns, Min
TDS_SHFREG/
TDH_SHFREG
A – D inputs to CLK 0.33/0.34 0.37/0.37 0.44/0.43 0.44/0.44 0.44/0.43 0.54/0.55 ns, Min
Clock CLK
TMPW_SHFREG Minimum pulse width 0.77 0.86 0.98 0.98 0.98 1.22 ns, Min
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
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Product Specification 30
Block RAM and FIFO Switching Characteristics
Table 30: Block RAM and FIFO Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and
TRCKO_DO_REG(1)
Clock CLK to DOUT
output (without output
register)(2)(3)
1.85 2.13 2.46 2.46 2.46 2.87 ns, Max
Clock CLK to DOUT
output (with output
register)(4)(5)
0.64 0.74 0.89 0.89 0.89 1.02 ns, Max
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT
output with ECC (without
output register)(2)(3)
2.77 3.04 3.84 3.84 3.84 5.30 ns, Max
Clock CLK to DOUT
output with ECC (with
output register)(4)(5)
0.73 0.81 0.94 0.94 0.94 1.11 ns, Max
TRCKO_DO_CASCOUT and
TRCKO_DO_CASCOUT_REG
Clock CLK to DOUT
output with cascade
(without output register)(2)
2.61 2.88 3.30 3.30 3.30 3.76 ns, Max
Clock CLK to DOUT
output with cascade (with
output register)(4)
1.16 1.28 1.46 1.46 1.46 1.56 ns, Max
TRCKO_FLAGS Clock CLK to FIFO flags
outputs(6)
0.76 0.87 1.05 1.05 1.05 1.14 ns, Max
TRCKO_POINTERS Clock CLK to FIFO
pointers outputs(7)
0.94 1.02 1.15 1.15 1.15 1.30 ns, Max
TRCKO_PARITY_ECC Clock CLK to ECCPARITY
in ECC encode only mode
0.78 0.85 0.94 0.94 0.94 1.10 ns, Max
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR
(without output register)
2.56 2.81 3.55 3.55 3.55 4.90 ns, Max
Clock CLK to BITERR
(with output register)
0.68 0.76 0.89 0.89 0.89 1.05 ns, Max
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR
output with ECC (without
output register)
0.75 0.88 1.07 1.07 1.07 1.15 ns, Max
Clock CLK to RDADDR
output with ECC (with
output register)
0.84 0.93 1.08 1.08 1.08 1.29 ns, Max
Setup and Hold Times Before/After Clock CLK
TRCCK_ADDRA/
TRCKC_ADDRA
ADDR inputs(8) 0.45/0.31 0.49/0.33 0.57/0.36 0.57/0.52 0.57/0.36 0.77/0.45 ns, Min
TRDCK_DI_WF_NC/
TRCKD_DI_WF_NC
Data input setup/hold time
when block RAM is
configured in
WRITE_FIRST or
NO_CHANGE mode(9)
0.58/0.60 0.65/0.63 0.74/0.67 0.74/0.67 0.74/0.67 0.92/0.76 ns, Min
TRDCK_DI_RF/
TRCKD_DI_RF
Data input setup/hold time
when block RAM is
configured in
READ_FIRST mode(9)
0.20/0.29 0.22/0.34 0.25/0.41 0.25/0.50 0.25/0.41 0.29/0.38 ns, Min
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 31
TRDCK_DI_ECC/
TRCKD_DI_ECC
DIN inputs with block RAM
ECC in standard mode(9) 0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 0.63/0.50 0.78/0.54 ns, Min
TRDCK_DI_ECCW/
TRCKD_DI_ECCW
DIN inputs with block RAM
ECC encode only(9)
0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 1.17/0.50 1.38/0.48 ns, Min
TRDCK_DI_ECC_FIFO/
TRCKD_DI_ECC_FIFO
DIN inputs with FIFO ECC
in standard mode(9) 1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 1.32/0.64 1.55/0.77 ns, Min
TRCCK_INJECTBITERR/
TRCKC_INJECTBITERR
Inject single/double bit
error in ECC mode
0.58/0.35 0.64/0.37 0.74/0.40 0.74/0.52 0.74/0.40 0.92/0.48 ns, Min
TRCCK_EN/TRCKC_EN Block RAM enable (EN)
input
0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 0.45/0.23 0.57/0.26 ns, Min
TRCCK_REGCE/
TRCKC_REGCE
CE input of output register 0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 0.36/0.16 0.40/0.19 ns, Min
TRCCK_RSTREG/
TRCKC_RSTREG
Synchronous RSTREG
input
0.29/0.07 0.32/0.07 0.35/0.07 0.35/0.17 0.35/0.07 0.41/0.07 ns, Min
TRCCK_RSTRAM/
TRCKC_RSTRAM
Synchronous RSTRAM
input
0.32/0.42 0.34/0.43 0.36/0.46 0.36/0.57 0.36/0.46 0.40/0.47 ns, Min
TRCCK_WEA/
TRCKC_WEA
Write enable (WE) input
(block RAM only)
0.44/0.18 0.48/0.19 0.54/0.20 0.54/0.42 0.54/0.20 0.64/0.23 ns, Min
TRCCK_WREN/
TRCKC_WREN
WREN FIFO inputs 0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 0.47/0.43 0.77/0.44 ns, Min
TRCCK_RDEN/
TRCKC_RDEN
RDEN FIFO inputs 0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 0.43/0.43 0.71/0.50 ns, Min
Reset Delays
TRCO_FLAGS Reset RST to FIFO
flags/pointers(10)
0.90 0.98 1.10 1.10 1.10 1.25 ns, Max
TRREC_RST/
TRREM_RST
FIFO reset recovery and
removal timing(11) 1.87/–0.81 2.07/–0.81 2.37/–0.81 2.37/–0.58 2.37/–0.81 2.44/–0.71 ns, Max
Maximum Frequency
FMAX_BRAM_WF_NC Block RAM (write first and
no change modes) when
not in SDP RF mode
509.68 460.83 388.20 388.20 388.20 315.66 MHz
FMAX_BRAM_RF_
PERFORMANCE
Block RAM (read first,
performance mode) when
in SDP RF mode but no
address overlap between
port A and port B
509.68 460.83 388.20 388.20 388.20 315.66 MHz
FMAX_BRAM_RF_
DELAYED_WRITE
Block RAM (read first,
delayed write mode) when
in SDP RF mode and
there is possibility of
overlap between port A
and port B addresses
447.63 404.53 339.67 339.67 339.67 268.96 MHz
Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 32
FMAX_CAS_WF_NC Block RAM cascade (write
first, no change mode)
when cascade but not in
RF mode
467.07 418.59 345.78 345.78 345.78 273.30 MHz
FMAX_CAS_RF_
PERFORMANCE
Block RAM cascade (read
first, performance mode)
when in cascade with RF
mode and no possibility of
address overlap/one port
is disabled
467.07 418.59 345.78 345.78 345.78 273.30 MHz
FMAX_CAS_RF_
DELAYED_WRITE
When in cascade RF
mode and there is a
possibility of address
overlap between port A
and port B
405.35 362.19 297.35 297.35 297.35 226.60 MHz
FMAX_FIFO FIFO in all modes without
ECC
509.68 460.83 388.20 388.20 388.20 315.66 MHz
FMAX_ECC Block RAM and FIFO in
ECC configuration
410.34 365.10 297.53 297.53 297.53 215.38 MHz
Notes:
1. The timing report shows all of these parameters as TRCKO_DO.
2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.
9. These parameters include both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
Table 30: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 33
DSP48E1 Switching Characteristics
Table 31: DSP48E1 Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_A_AREG/
TDSPCKD_A_AREG
A input to A register CLK 0.26/
0.12
0.30/
0.13
0.37/
0.14
0.37/
0.28
0.37/
0.14
0.45/
0.14
ns
TDSPDCK_B_BREG/
TDSPCKD_B_BREG
B input to B register CLK 0.33/
0.15
0.38/
0.16
0.45/
0.18
0.45/
0.25
0.45/
0.18
0.60/
0.19
ns
TDSPDCK_C_CREG/
TDSPCKD_C_CREG
C input to C register CLK 0.17/
0.17
0.20/
0.19
0.24/
0.21
0.24/
0.26
0.24/
0.21
0.34/
0.29
ns
TDSPDCK_D_DREG/
TDSPCKD_D_DREG
D input to D register CLK 0.25/
0.25
0.32/
0.27
0.42/
0.27
0.42/
0.42
0.42/
0.27
0.54/
0.23
ns
TDSPDCK_ACIN_AREG/
TDSPCKD_ACIN_AREG
ACIN input to A register CLK 0.23/
0.12
0.27/
0.13
0.32/
0.14
0.32/
0.17
0.32/
0.14
0.36/
0.14
ns
TDSPDCK_BCIN_BREG/
TDSPCKD_BCIN_BREG
BCIN input to B register CLK 0.25/
0.15
0.29/
0.16
0.36/
0.18
0.36/
0.18
0.36/
0.18
0.41/
0.19
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, B}_MREG_MULT/
TDSPCKD_{A, B}_MREG_MULT
{A, B} input to M register CLK
using multiplier
2.40/
–0.01
2.76/
–0.01
3.29/
–0.01
3.29/
–0.01
3.29/
–0.01
4.31/
–0.07
ns
TDSPDCK_{A, D}_ADREG/
TDSPCKD_{A, D}_ADREG
{A, D} input to AD register CLK 1.29/
–0.02
1.48/
–0.02
1.76/
–0.02
1.76/
–0.02
1.76/
–0.02
2.29/
–0.27
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, B}_PREG_MULT/
TDSPCKD_{A, B} _PREG_MULT
{A, B} input to P register CLK
using multiplier
4.02/
–0.28
4.60/
–0.28
5.48/
–0.28
5.48/
–0.28
5.48/
–0.28
6.95/
–0.48
ns
TDSPDCK_D_PREG_MULT/
TDSPCKD_D_PREG_MULT
D input to P register CLK using
multiplier
3.93/
–0.73
4.50/
–0.73
5.35/
–0.73
5.35/
–0.73
5.35/
–0.73
6.73/
–1.68
ns
TDSPDCK_{A, B} _PREG/
TDSPCKD_{A, B} _PREG
A or B input to P register CLK
not using multiplier
1.73/
–0.28
1.98/
–0.28
2.35/
–0.28
2.35/
–0.28
2.35/
–0.28
2.80/
–0.48
ns
TDSPDCK_C_PREG/
TDSPCKD_C_PREG
C input to P register CLK not
using multiplier
1.54/
–0.26
1.76/
–0.26
2.10/
–0.26
2.10/
–0.26
2.10/
–0.26
2.54/
–0.45
ns
TDSPDCK_PCIN_PREG/
TDSPCKD_PCIN_PREG
PCIN input to P register CLK 1.32/
–0.15
1.51/
–0.15
1.80/
–0.15
1.80/
–0.15
1.80/
–0.15
2.13/
–0.25
ns
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA;CEB}_{AREG;BREG}/
TDSPCKD_{CEA;CEB}_{AREG;BREG}
{CEA; CEB} input to {A; B}
register CLK
0.35/
0.06
0.42/
0.08
0.52/
0.11
0.52/
0.11
0.52/
0.11
0.64/
0.11
ns
TDSPDCK_CEC_CREG/
TDSPCKD_CEC_CREG
CEC input to C register CLK 0.28/
0.10
0.34/
0.11
0.42/
0.13
0.42/
0.13
0.42/
0.13
0.49/
0.16
ns
TDSPDCK_CED_DREG/
TDSPCKD_CED_DREG
CED input to D register CLK 0.36/
–0.03
0.43/
–0.03
0.52/
–0.03
0.52/
–0.03
0.52/
–0.03
0.68/
0.14
ns
TDSPDCK_CEM_MREG/
TDSPCKD_CEM_MREG
CEM input to M register CLK 0.17/
0.18
0.21/
0.20
0.27/
0.23
0.27/
0.23
0.27/
0.23
0.45/
0.29
ns
TDSPDCK_CEP_PREG/
TDSPCKD_CEP_PREG
CEP input to P register CLK 0.36/
0.01
0.43/
0.01
0.53/
0.01
0.53/
0.01
0.53/
0.01
0.63/
0.00
ns
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 34
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/
TDSPCKD_{RSTA; RSTB}_{AREG; BREG}
{RSTA, RSTB} input to {A, B}
register CLK
0.41/
0.11
0.46/
0.13
0.55/
0.15
0.55/
0.24
0.55/
0.15
0.63/
0.40
ns
TDSPDCK_RSTC_CREG/
TDSPCKD_RSTC_CREG
RSTC input to C register CLK 0.07/
0.10
0.08/
0.11
0.09/
0.12
0.09/
0.25
0.09/
0.12
0.13/
0.11
ns
TDSPDCK_RSTD_DREG/
TDSPCKD_RSTD_DREG
RSTD input to D register CLK 0.44/
0.07
0.50/
0.08
0.59/
0.09
0.59/
0.09
0.59/
0.09
0.67/
0.08
ns
TDSPDCK_RSTM_MREG/
TDSPCKD_RSTM_MREG
RSTM input to M register CLK 0.21/
0.22
0.23/
0.24
0.27/
0.28
0.27/
0.28
0.27/
0.28
0.28/
0.35
ns
TDSPDCK_RSTP_PREG/
TDSPCKD_RSTP_PREG
RSTP input to P register CLK 0.27/
0.01
0.30/
0.01
0.35/
0.01
0.35/
0.03
0.35/
0.01
0.43/
0.00
ns
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output
using multiplier
3.79 4.35 5.18 5.18 5.18 6.61 ns
TDSPDO_D_P_MULT D input to P output using
multiplier
3.72 4.26 5.07 5.07 5.07 6.41 ns
TDSPDO_B_P B input to P output not using
multiplier
1.53 1.75 2.08 2.08 2.08 2.48 ns
TDSPDO_C_P C input to P output 1.33 1.53 1.82 1.82 1.82 2.22 ns
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT, BCOUT}
output
0.55 0.63 0.74 0.74 0.74 0.87 ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to
CARRYCASCOUT output using
multiplier
4.06 4.65 5.54 5.54 5.54 7.03 ns
TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT
output using multiplier
3.97 4.54 5.40 5.40 5.40 6.81 ns
TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to
CARRYCASCOUT output not
using multiplier
1.77 2.03 2.41 2.41 2.41 2.88 ns
TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT
output
1.58 1.81 2.15 2.15 2.15 2.62 ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT ACIN input to P output using
multiplier
3.65 4.19 5.00 5.00 5.00 6.40 ns
TDSPDO_ACIN_P ACIN input to P output not using
multiplier
1.37 1.57 1.88 1.88 1.88 2.44 ns
TDSPDO_ACIN_ACOUT ACIN input to ACOUT output 0.38 0.44 0.53 0.53 0.53 0.63 ns
TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to
CARRYCASCOUT output using
multiplier
3.90 4.47 5.33 5.33 5.33 6.79 ns
TDSPDO_ACIN_CARRYCASCOUT ACIN input to
CARRYCASCOUT output not
using multiplier
1.61 1.85 2.21 2.21 2.21 2.84 ns
TDSPDO_PCIN_P PCIN input to P output 1.11 1.28 1.52 1.52 1.52 1.82 ns
TDSPDO_PCIN_CARRYCASCOUT PCIN input to
CARRYCASCOUT output
1.36 1.56 1.85 1.85 1.85 2.21 ns
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 35
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG CLK PREG to P output 0.33 0.37 0.44 0.44 0.44 0.54 ns
TDSPCKO_CARRYCASCOUT_PREG CLK PREG to
CARRYCASCOUT output
0.52 0.59 0.69 0.69 0.69 0.84 ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG CLK MREG to P output 1.68 1.93 2.31 2.31 2.31 2.73 ns
TDSPCKO_CARRYCASCOUT_MREG CLK MREG to
CARRYCASCOUT output
1.92 2.21 2.64 2.64 2.64 3.12 ns
TDSPCKO_P_ADREG_MULT CLK ADREG to P output using
multiplier
2.72 3.10 3.69 3.69 3.69 4.60 ns
TDSPCKO_CARRYCASCOUT_ADREG_
MULT
CLK ADREG to
CARRYCASCOUT output using
multiplier
2.96 3.38 4.02 4.02 4.02 4.99 ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT CLK AREG to P output using
multiplier
3.94 4.51 5.37 5.37 5.37 6.84 ns
TDSPCKO_P_BREG CLK BREG to P output not using
multiplier
1.64 1.87 2.22 2.22 2.22 2.65 ns
TDSPCKO_P_CREG CLK CREG to P output not
using multiplier
1.69 1.93 2.30 2.30 2.30 2.81 ns
TDSPCKO_P_DREG_MULT CLK DREG to P output using
multiplier
3.91 4.48 5.32 5.32 5.32 6.77 ns
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG;
BREG}
CLK (ACOUT, BCOUT) to {A,B}
register output
0.64 0.73 0.87 0.87 0.87 1.02 ns
TDSPCKO_CARRYCASCOUT_{AREG,
BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
4.19 4.79 5.70 5.70 5.70 7.24 ns
TDSPCKO_CARRYCASCOUT_ BREG CLK BREG to
CARRYCASCOUT output not
using multiplier
1.88 2.15 2.55 2.55 2.55 3.04 ns
TDSPCKO_CARRYCASCOUT_
DREG_MULT
CLK DREG to
CARRYCASCOUT output using
multiplier
4.16 4.76 5.65 5.65 5.65 7.17 ns
TDSPCKO_CARRYCASCOUT_ CREG CLK CREG to
CARRYCASCOUT output
1.94 2.21 2.63 2.63 2.63 3.20 ns
Maximum Frequency
FMAX With all registers used 628.93 550.66 464.25 464.25 464.25 363.77 MHz
FMAX_PATDET With pattern detector 531.63 465.77 392.93 392.93 392.93 310.08 MHz
FMAX_MULT_NOMREG Two register multiply without
MREG
349.28 305.62 257.47 257.47 257.47 210.44 MHz
FMAX_MULT_NOMREG_PATDET Two register multiply without
MREG with pattern detect
317.26 277.62 233.92 233.92 233.92 191.28 MHz
FMAX_PREADD_MULT_NOADREG Without ADREG 397.30 346.26 290.44 290.44 290.44 223.26 MHz
FMAX_PREADD_MULT_NOADREG_
PATDET
Without ADREG with pattern
detect
397.30 346.26 290.44 290.44 290.44 223.26 MHz
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 36
Clock Buffers and Networks
FMAX_NOPIPELINEREG Without pipeline registers
(MREG, ADREG)
260.01 227.01 190.69 190.69 190.69 150.13 MHz
FMAX_NOPIPELINEREG_PATDET Without pipeline registers
(MREG, ADREG) with pattern
detect
241.72 211.15 177.43 177.43 177.43 140.10 MHz
Table 32: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
TBCCCK_CE/
TBCCKC_CE(1)
CE pins setup/hold 0.12/0.39 0.13/0.40 0.16/0.41 0.16/0.83 0.16/0.41 0.31/0.67 ns
TBCCCK_S/
TBCCKC_S(1) S pins setup/hold 0.12/0.39 0.13/0.40 0.16/0.41 0.16/0.83 0.16/0.41 0.31/0.67 ns
TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O 0.08 0.09 0.10 0.10 0.10 0.14 ns
Maximum Frequency
FMAX_BUFG Global clock tree (BUFG) 628.00 628.00 464.00 464.00 464.00 394.00 MHz
Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 33: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
TBIOCKO_O Clock to out delay from I to O 1.11 1.26 1.54 1.54 1.54 1.56 ns
Maximum Frequency
FMAX_BUFIO I/O clock tree (BUFIO) 680.00 680.00 600.00 600.00 600.00 600.00 MHz
Table 34: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
TBRCKO_O Clock to out delay from I to O 0.64 0.76 0.99 0.99 0.99 1.24 ns
TBRCKO_O_BYP Clock to out delay from I to O with
Divide Bypass attribute set
0.34 0.39 0.52 0.52 0.52 0.72 ns
TBRDO_O Propagation delay from CLR to O 0.81 0.85 1.09 1.09 1.09 0.96 ns
Table 31: DSP48E1 Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 37
Maximum Frequency
FMAX_BUFR(1) Regional clock tree (BUFR) 420.00 375.00 315.00 315.00 315.00 315.00 MHz
Notes:
1. The maximum input frequency to the BUFR and BUFMR is the BUFIO FMAX frequency.
Table 35: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
TBHCKO_O BUFH delay from I to O 0.10 0.11 0.13 0.13 0.13 0.16 ns
TBHCCK_CE/
TBHCKC_CE CE pin setup and hold 0.19/0.13 0.22/0.15 0.28/0.21 0.28/0.42 0.28/0.21 0.35/0.25 ns
Maximum Frequency
FMAX_BUFH Horizontal clock buffer (BUFH) 628.00 628.00 464.00 464.00 464.00 394.00 MHz
Table 36: Duty Cycle Distortion and Clock-Tree Skew
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
TDCD_CLK Global clock tree duty-cycle
distortion(1)
All 0.20 0.20 0.20 N/A 0.20 0.25 ns
TCKSKEW Global clock tree skew(2) XC7A12T 0.26 0.26 0.26 N/A 0.26 0.33 ns
XC7A15T 0.26 0.26 0.26 N/A 0.26 0.33 ns
XC7A25T 0.26 0.26 0.26 N/A 0.26 0.33 ns
XC7A35T 0.26 0.26 0.26 N/A 0.26 0.33 ns
XC7A50T 0.26 0.26 0.26 N/A 0.26 0.33 ns
XC7A75T 0.27 0.33 0.36 N/A 0.36 0.48 ns
XC7A100T 0.27 0.33 0.36 N/A 0.36 0.48 ns
XC7A200T 0.40 0.48 0.54 N/A 0.54 0.69 ns
XA7A12T N/A 0.26 0.26 0.26 N/A N/A ns
XA7A15T N/A 0.26 0.26 0.26 N/A N/A ns
XA7A25T N/A 0.26 0.26 0.26 N/A N/A ns
XA7A35T N/A 0.26 0.26 0.26 N/A N/A ns
XA7A50T N/A 0.26 0.26 0.26 N/A N/A ns
XA7A75T N/A 0.33 0.36 0.36 N/A N/A ns
XA7A100T N/A 0.33 0.36 0.36 N/A N/A ns
XQ7A50T N/A 0.26 0.26 0.26 0.26 N/A ns
XQ7A100T N/A 0.33 0.36 0.36 0.36 N/A ns
XQ7A200T N/A 0.48 0.54 0.54 0.54 N/A ns
TDCD_BUFIO I/O clock tree duty cycle distortion All 0.14 0.14 0.14 0.14 0.14 0.14 ns
Table 34: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 38
MMCM Switching Characteristics
TBUFIOSKEW I/O clock tree skew across one
clock region
All 0.03 0.03 0.03 0.03 0.03 0.03 ns
TDCD_BUFR Regional clock tree duty cycle
distortion
All 0.18 0.18 0.18 0.18 0.18 0.18 ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to
calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer
tools to evaluate clock skew specific to your application.
Table 37: MMCM Specification
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
MMCM_FINMAX Maximum input clock frequency 800.00 800.00 800.00 800.00 800.00 MHz
MMCM_FINMIN Minimum input clock frequency 10.00 10.00 10.00 10.00 10.00 MHz
MMCM_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max
MMCM_FINDUTY Allowable input duty cycle:
10—49 MHz
25 25 25 25 25 %
Allowable input duty cycle:
50—199 MHz
30 30 30 30 30 %
Allowable input duty cycle:
200—399 MHz
35 35 35 35 35 %
Allowable input duty cycle:
400—499 MHz
40 40 40 40 40 %
Allowable input duty cycle: > 500 MHz 45 45 45 45 45 %
MMCM_FMIN_PSCLK Minimum dynamic phase-shift clock
frequency
0.01 0.01 0.01 0.01 0.01 MHz
MMCM_FMAX_PSCLK Maximum dynamic phase-shift clock
frequency
550.00 500.00 450.00 450.00 450.00 MHz
MMCM_FVCOMIN Minimum MMCM VCO frequency 600.00 600.00 600.00 600.00 600.00 MHz
MMCM_FVCOMAX Maximum MMCM VCO frequency 1600.00 1440.00 1200.00 1200.00 1200.00 MHz
MMCM_FBANDWIDTH Low MMCM bandwidth at typical(1) 1.00 1.00 1.00 1.00 1.00 MHz
High MMCM bandwidth at typical(1) 4.00 4.00 4.00 4.00 4.00 MHz
MMCM_TSTATPHAOFFSET Static phase offset of the MMCM
outputs(2)
0.12 0.12 0.12 0.12 0.12 ns
MMCM_TOUTJITTER MMCM output jitter Note 3
MMCM_TOUTDUTY MMCM output clock duty-cycle
precision(4) 0.20 0.20 0.20 0.20 0.25 ns
MMCM_TLOCKMAX MMCM maximum lock time 100.00 100.00 100.00 100.00 100.00 µs
MMCM_FOUTMAX MMCM maximum output frequency 800.00 800.00 800.00 800.00 800.00 MHz
MMCM_FOUTMIN MMCM minimum output frequency(5)(6) 4.69 4.69 4.69 4.69 4.69 MHz
Table 36: Duty Cycle Distortion and Clock-Tree Skew (Cont’d)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1Q/-1M -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 39
MMCM_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max
MMCM_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 5.00 ns
MMCM_FPFDMAX Maximum frequency at the phase
frequency detector
550.00 500.00 450.00 450.00 450.00 MHz
MMCM_FPFDMIN Minimum frequency at the phase
frequency detector
10.00 10.00 10.00 10.00 10.00 MHz
MMCM_TFBDELAY Maximum delay in the feedback path 3 ns Max or one CLKIN cycle
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN/
TMMCMCKD_PSEN
Setup and hold of phase-shift enable 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
TMMCMDCK_PSINCDEC/
TMMCMCKD_PSINCDEC
Setup and hold of phase-shift
increment/decrement
1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns
TMMCMCKO_PSDONE Phase shift clock-to-out of PSDONE 0.59 0.68 0.81 0.81 0.78 ns
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
TMMCMDCK_DADDR/
TMMCMCKD_DADDR
DADDR setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TMMCMDCK_DI/
TMMCMCKD_DI
DI setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TMMCMDCK_DEN/
TMMCMCKD_DEN
DEN setup/hold 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 2.40/0.00 ns, Min
TMMCMDCK_DWE/
TMMCMCKD_DWE
DWE setup/hold 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TMMCMCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.99 0.99 ns, Max
FDCK DCLK frequency 200.00 200.00 200.00 200.00 100.00 MHz, Max
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
6. When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.
Table 37: MMCM Specification (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 40
PLL Switching Characteristics
Table 38: PLL Specification
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
PLL_FINMAX Maximum input clock frequency 800.00 800.00 800.00 800.00 800.00 MHz
PLL_FINMIN Minimum input clock frequency 19.00 19.00 19.00 19.00 19.00 MHz
PLL_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max
PLL_FINDUTY Allowable input duty cycle: 19—49 MHz 25 25 25 25 25 %
Allowable input duty cycle: 50—199 MHz 30 30 30 30 30 %
Allowable input duty cycle: 200—399 MHz 35 35 35 35 35 %
Allowable input duty cycle: 400—499 MHz 40 40 40 40 40 %
Allowable input duty cycle: >500 MHz 45 45 45 45 45 %
PLL_FVCOMIN Minimum PLL VCO frequency 800.00 800.00 800.00 800.00 800.00 MHz
PLL_FVCOMAX Maximum PLL VCO frequency 2133.00 1866.00 1600.00 1600.00 1600.00 MHz
PLL_FBANDWIDTH Low PLL bandwidth at typical(1) 1.00 1.00 1.00 1.00 1.00 MHz
High PLL bandwidth at typical(1) 4.00 4.00 4.00 4.00 4.00 MHz
PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs(2) 0.12 0.12 0.12 0.12 0.12 ns
PLL_TOUTJITTER PLL output jitter Note 3
PLL_TOUTDUTY PLL output clock duty-cycle precision(4) 0.20 0.20 0.20 0.20 0.25 ns
PLL_TLOCKMAX PLL maximum lock time 100.00 100.00 100.00 100.00 100.00 µs
PLL_FOUTMAX PLL maximum output frequency 800.00 800.00 800.00 800.00 800.00 MHz
PLL_FOUTMIN PLL minimum output frequency(5) 6.25 6.25 6.25 6.25 6.25 MHz
PLL_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max
PLL_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 5.00 ns
PLL_FPFDMAX Maximum frequency at the phase
frequency detector
550.00 500.00 450.00 450.00 450.00 MHz
PLL_FPFDMIN Minimum frequency at the phase
frequency detector
19.00 19.00 19.00 19.00 19.00 MHz
PLL_TFBDELAY Maximum delay in the feedback path 3 ns Max or one CLKIN cycle
Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK
TPLLDCK_DADDR/
TPLLCKD_DADDR
Setup and hold of D address 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TPLLDCK_DI/
TPLLCKD_DI
Setup and hold of D input 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TPLLDCK_DEN/
TPLLCKD_DEN
Setup and hold of D enable 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 2.40/0.00 ns, Min
TPLLDCK_DWE/
TPLLCKD_DWE
Setup and hold of D write enable 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00 ns, Min
TPLLCKO_DRDY CLK to out of DRDY 0.65 0.72 0.99 0.99 0.99 ns, Max
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 41
Device Pin-to-Pin Output Parameter Guidelines
FDCK DCLK frequency 200.00 200.00 200.00 200.00 100.00 MHz, Max
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
4. Includes global clock buffer.
5. Calculated as FVCO/128 assuming output duty cycle is 50%.
Table 39: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOF Clock-capable clock input and OUTFF at
pins/banks closest to the BUFGs without
MMCM/PLL (near clock region)(2)
XC7A12T 4.97 5.55 6.44 N/A 6.44 7.38 ns
XC7A15T 5.10 5.70 6.61 N/A 6.61 7.56 ns
XC7A25T 4.97 5.55 6.44 N/A 6.44 7.38 ns
XC7A35T 5.10 5.70 6.61 N/A 6.61 7.56 ns
XC7A50T 5.10 5.70 6.61 N/A 6.61 7.56 ns
XC7A75T 5.14 5.74 6.72 N/A 6.72 7.62 ns
XC7A100T 5.14 5.74 6.72 N/A 6.72 7.62 ns
XC7A200T 5.47 6.11 7.16 N/A 7.16 8.08 ns
XA7A12T N/A 5.55 6.44 6.44 N/A N/A ns
XA7A15T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A25T N/A 5.55 6.44 6.44 N/A N/A ns
XA7A35T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A50T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A75T N/A 5.74 6.72 6.72 N/A N/A ns
XA7A100T N/A 5.74 6.72 6.72 N/A N/A ns
XQ7A50T N/A 5.70 6.61 6.61 6.61 N/A ns
XQ7A100T N/A 5.74 6.72 6.72 6.72 N/A ns
XQ7A200T N/A 6.11 7.16 7.16 7.16 N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475).
Table 38: PLL Specification (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 42
Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1)
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.
TICKOFFAR Clock-capable clock input and OUTFF
at pins/banks farthest from the BUFGs
without MMCM/PLL (far clock region)(2)
XC7A12T 4.97 5.55 6.44 N/A 6.44 7.38 ns
XC7A15T 5.10 5.70 6.61 N/A 6.61 7.57 ns
XC7A25T 4.97 5.55 6.44 N/A 6.44 7.38 ns
XC7A35T 5.10 5.70 6.61 N/A 6.61 7.57 ns
XC7A50T 5.10 5.70 6.61 N/A 6.61 7.57 ns
XC7A75T 5.38 6.01 7.02 N/A 7.02 7.94 ns
XC7A100T 5.38 6.01 7.02 N/A 7.02 7.94 ns
XC7A200T 6.17 6.89 8.05 N/A 8.05 9.03 ns
XA7A12T N/A 5.55 6.44 6.44 N/A N/A ns
XA7A15T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A25T N/A 5.55 6.44 6.44 N/A N/A ns
XA7A35T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A50T N/A 5.70 6.61 6.61 N/A N/A ns
XA7A75T N/A 6.01 7.02 7.02 N/A N/A ns
XA7A100T N/A 6.01 7.02 7.02 N/A N/A ns
XQ7A50T N/A 5.70 6.61 6.61 6.61 N/A ns
XQ7A100T N/A 6.01 7.02 7.02 7.02 N/A ns
XQ7A200T N/A 6.89 8.05 8.05 8.05 N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475).
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 43
Table 41: Clock-Capable Clock Input to Output Delay With MMCM
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.
TICKOFMMCMCC Clock-capable clock input and
OUTFF with MMCM
XC7A12T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A15T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A25T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A35T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A50T 1.00 1.00 1.00 N/A 1.00 1.78 ns
XC7A75T 1.00 1.00 1.00 N/A 1.00 1.79 ns
XC7A100T 1.00 1.00 1.00 N/A 1.00 1.79 ns
XC7A200T 1.01 1.02 1.04 N/A 1.04 1.84 ns
XA7A12T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A15T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A25T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A35T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A50T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A75T N/A 1.00 1.00 1.00 N/A N/A ns
XA7A100T N/A 1.00 1.00 1.00 N/A N/A ns
XQ7A50T N/A 1.00 1.00 1.00 1.00 N/A ns
XQ7A100T N/A 1.00 1.00 1.00 1.00 N/A ns
XQ7A200T N/A 1.02 1.04 1.04 1.04 N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 44
Table 42: Clock-Capable Clock Input to Output Delay With PLL
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.
TICKOFPLLCC Clock-capable clock input and
OUTFF with PLL
XC7A12T 0.83 0.83 0.83 N/A 0.83 1.38 ns
XC7A15T 0.82 0.82 0.82 N/A 0.82 1.39 ns
XC7A25T 0.83 0.83 0.83 N/A 0.83 1.38 ns
XC7A35T 0.82 0.82 0.82 N/A 0.82 1.39 ns
XC7A50T 0.82 0.82 0.82 N/A 0.82 1.39 ns
XC7A75T 0.82 0.82 0.82 N/A 0.82 1.40 ns
XC7A100T 0.82 0.82 0.82 N/A 0.82 1.40 ns
XC7A200T 0.81 0.81 0.81 N/A 0.81 1.45 ns
XA7A12T N/A 0.83 0.83 0.83 N/A N/A ns
XA7A15T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A25T N/A 0.83 0.83 0.83 N/A N/A ns
XA7A35T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A50T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A75T N/A 0.82 0.82 0.82 N/A N/A ns
XA7A100T N/A 0.82 0.82 0.82 N/A N/A ns
XQ7A50T N/A 0.82 0.82 0.82 0.82 N/A ns
XQ7A100T N/A 0.82 0.82 0.82 0.82 N/A ns
XQ7A200T N/A 0.81 0.81 0.81 0.81 N/A ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
Table 43: Pin-to-Pin, Clock-to-Out using BUFIO
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.
TICKOFCS Clock to out of I/O clock 5.01 5.61 6.64 6.64 6.64 7.32 ns
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 45
Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted.
Table 44: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSFD/
TPHFD
Full delay (legacy delay
or default delay)
global clock input and
IFF(2) without
MMCM/PLL with
ZHOLD_DELAY on HR
I/O banks
XC7A12T 2.49/–0.37 2.67/–0.37 3.12/–0.37 N/A 3.12/–0.37 5.13/–0.54 ns
XC7A15T 2.47/–0.29 2.65/–0.29 3.10/–0.29 N/A 3.10/–0.29 5.10/–0.44 ns
XC7A25T 2.49/–0.37 2.67/–0.37 3.12/–0.37 N/A 3.12/–0.37 5.13/–0.54 ns
XC7A35T 2.47/–0.29 2.65/–0.29 3.10/–0.29 N/A 3.10/–0.29 5.10/–0.44 ns
XC7A50T 2.47/–0.29 2.65/–0.29 3.10/–0.29 N/A 3.10/–0.29 5.10/–0.44 ns
XC7A75T 2.69/–0.34 2.89/–0.34 3.34/–0.34 N/A 3.34/–0.34 5.66/–0.51 ns
XC7A100T 2.69/–0.34 2.89/–0.34 3.34/–0.34 N/A 3.34/–0.34 5.66/–0.51 ns
XC7A200T 3.03/–0.36 3.27/–0.36 3.79/–0.36 N/A 3.79/–0.36 6.66/–0.55 ns
XA7A12T N/A 2.67/–0.37 3.12/–0.37 3.12/–0.37 N/A N/A ns
XA7A15T N/A 2.65/–0.29 3.10/–0.29 3.10/–0.29 N/A N/A ns
XA7A25T N/A 2.67/–0.37 3.12/–0.37 3.12/–0.37 N/A N/A ns
XA7A35T N/A 2.65/–0.29 3.10/–0.29 3.10/–0.29 N/A N/A ns
XA7A50T N/A 2.65/–0.29 3.10/–0.29 3.10/–0.29 N/A N/A ns
XA7A75T N/A 2.89/–0.34 3.34/–0.34 3.34/–0.34 N/A N/A ns
XA7A100T N/A 2.89/–0.34 3.34/–0.34 3.34/–0.34 N/A N/A ns
XQ7A50T N/A 2.65/–0.29 3.10/–0.29 3.10/–0.29 3.10/–0.29 N/A ns
XQ7A100T N/A 2.89/–0.34 3.34/–0.34 3.34/–0.34 3.34/–0.34 N/A ns
XQ7A200T N/A 3.27/–0.36 3.79/–0.36 3.79/–0.36 3.79/–0.36 N/A ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global
clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input
signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 46
Table 45: Clock-Capable Clock Input Setup and Hold With MMCM
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)
TPSMMCMCC/
TPHMMCMCC
No delay clock-
capable clock input
and IFF(2) with
MMCM
XC7A12T 2.37/–0.61 2.69/–0.61 3.21/–0.61 N/A 3.21/–0.61 2.00/–0.47 ns
XC7A15T 2.46/–0.62 2.80/–0.62 3.35/–0.62 N/A 3.35/–0.62 2.14/–0.48 ns
XC7A25T 2.37/–0.61 2.69/–0.61 3.21/–0.61 N/A 3.21/–0.61 2.00/–0.47 ns
XC7A35T 2.46/–0.62 2.80/–0.62 3.35/–0.62 N/A 3.35/–0.62 2.14/–0.48 ns
XC7A50T 2.46/–0.62 2.80/–0.62 3.35/–0.62 N/A 3.35/–0.62 2.14/–0.48 ns
XC7A75T 2.47/–0.62 2.81/–0.62 3.36/–0.62 N/A 3.36/–0.62 2.15/–0.48 ns
XC7A100T 2.47/–0.62 2.81/–0.62 3.36/–0.62 N/A 3.36/–0.62 2.15/–0.48 ns
XC7A200T 2.59/–0.63 2.95/–0.63 3.52/–0.63 N/A 3.52/–0.63 2.32/–0.51 ns
XA7A12T N/A 2.69/–0.61 3.21/–0.61 3.21/–0.61 N/A N/A ns
XA7A15T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 N/A N/A ns
XA7A25T N/A 2.69/–0.61 3.21/–0.61 3.21/–0.61 N/A N/A ns
XA7A35T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 N/A N/A ns
XA7A50T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 N/A N/A ns
XA7A75T N/A 2.81/–0.62 3.36/–0.62 3.36/–0.62 N/A N/A ns
XA7A100T N/A 2.81/–0.62 3.36/–0.62 3.36/–0.62 N/A N/A ns
XQ7A50T N/A 2.80/–0.62 3.35/–0.62 3.35/–0.62 3.35/–0.62 N/A ns
XQ7A100T N/A 2.81/–0.62 3.36/–0.62 3.36/–0.62 3.36/–0.62 N/A ns
XQ7A200T N/A 2.95/–0.63 3.52/–0.63 3.52/–0.63 3.52/–0.63 N/A ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 47
Table 46: Clock-Capable Clock Input Setup and Hold With PLL
Symbol Description Device
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)
TPSPLLCC/
TPHPLLCC
No delay clock-capable
clock input and IFF(2)
with PLL
XC7A12T 2.68/–0.19 3.04/–0.19 3.64/–0.19 N/A 3.64/–0.19 2.32/–0.57 ns
XC7A15T 2.77/–0.20 3.15/–0.20 3.77/–0.20 N/A 3.77/–0.20 2.46/–0.59 ns
XC7A25T 2.68/–0.19 3.04/–0.19 3.64/–0.19 N/A 3.64/–0.19 2.32/–0.57 ns
XC7A35T 2.77/–0.20 3.15/–0.20 3.77/–0.20 N/A 3.77/–0.20 2.46/–0.59 ns
XC7A50T 2.77/–0.20 3.15/–0.20 3.77/–0.20 N/A 3.77/–0.20 2.46/–0.59 ns
XC7A75T 2.78/–0.20 3.15/–0.20 3.78/–0.20 N/A 3.78/–0.20 2.47/–0.59 ns
XC7A100T 2.78/–0.20 3.15/–0.20 3.78/–0.20 N/A 3.78/–0.20 2.47/–0.59 ns
XC7A200T 2.91/–0.21 3.29/–0.21 3.94/–0.21 N/A 3.94/–0.21 2.64/–0.62 ns
XA7A12T N/A 3.04/–0.19 3.64/–0.19 3.64/–0.19 N/A N/A ns
XA7A15T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 N/A N/A ns
XA7A25T N/A 3.04/–0.19 3.64/–0.19 3.64/–0.19 N/A N/A ns
XA7A35T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 N/A N/A ns
XA7A50T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 N/A N/A ns
XA7A75T N/A 3.15/–0.20 3.78/–0.20 3.78/–0.20 N/A N/A ns
XA7A100T N/A 3.15/–0.20 3.78/–0.20 3.78/–0.20 N/A N/A ns
XQ7A50T N/A 3.15/–0.20 3.77/–0.20 3.77/–0.20 3.77/–0.20 N/A ns
XQ7A100T N/A 3.15/–0.20 3.78/–0.20 3.78/–0.20 3.78/–0.20 N/A ns
XQ7A200T N/A 3.29/–0.21 3.94/–0.21 3.94/–0.21 3.94/–0.21 N/A ns
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global
clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input flip-flop or latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 47: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.
TPSCS/TPHCS Setup and hold of I/O clock –0.38/1.31 –0.38/1.46 –0.38/1.76 –0.38/1.76 –0.38/1.76 –0.16/1.89 ns
Table 48: Sample Window
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
TSAMP Sampling error at receiver pins(1) 0.59 0.64 0.70 0.70 0.70 0.70 ns
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 48
Additional Package Parameter Guidelines
The parameters in this section provide the necessary values for calculating timing budgets for Artix-7 FPGA clock transmitter
and receiver data-valid windows.
TSAMP_BUFIO Sampling error at receiver pins using
BUFIO(2) 0.35 0.40 0.46 0.46 0.46 0.46 ns
Notes:
1. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 49: Package Skew
Symbol Description Device Package Value Units
TPKGSKEW Package skew(1) XC7A12T CPG238 55 ps
CSG325 76 ps
XC7A15T CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
FTG256 98 ps
FGG484 97 ps
XC7A25T CPG238 55 ps
CSG325 76 ps
XC7A35T CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
FTG256 98 ps
FGG484 97 ps
XC7A50T CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
FTG256 98 ps
FGG484 97 ps
XC7A75T CSG324 113 ps
FTG256 120 ps
FGG484 144 ps
FGG676 153 ps
Table 48: Sample Window (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1M/-1Q -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 49
TPKGSKEW Package skew(1) XC7A100T CSG324 113 ps
FTG256 120 ps
FGG484 144 ps
FGG676 153 ps
XC7A200T SBG484 111 ps
FBG484 109 ps
FBG676 121 ps
FFG1156 151 ps
XA7A12T CSG325 76 ps
CPG238 55 ps
XA7A15T CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
XA7A25T CSG325 76 ps
CPG238 55 ps
XA7A35T CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
XA7A50T CPG236 48 ps
CSG324 104 ps
CSG325 142 ps
XA7A75T CSG324 113 ps
FGG484 144 ps
XA7A100T CSG324 113 ps
FGG484 144 ps
XQ7A50T CS325 142 ps
FG484 97 ps
XQ7A100T CS324 113 ps
FG484 144 ps
XQ7A200T RS484 111 ps
RB484 109 ps
RB676 121 ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die
pad to ball.
2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.
Table 49: Package Skew (Cont’d)
Symbol Description Device Package Value Units
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 50
GTP Transceiver Specifications
GTP Transceiver DC Input and Output Levels
Table 50 summarizes the DC output specifications of the GTP transceivers in Artix-7 FPGAs. Consult 7 Series FPGAs GTP
Transceiver User Guide (UG482) for further details.
Table 50: GTP Transceiver DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
DVPPOUT Differential peak-to-peak output
voltage(1)
Transmitter output swing is set to
maximum setting
1000 – mV
VCMOUTDC DC common mode output
voltage
Equation based VMGTAVTT –DV
PPOUT/4 mV
ROUT Differential output resistance 100 Ω
VCMOUTAC Common mode output voltage: AC coupled 1/2 VMGTAVTT mV
TOSKEW
Transmitter output pair (TXP and TXN) intra-pair skew
(FF, FB, SB packages)
10 ps
Transmitter output pair (TXP and TXN) intra-pair skew
(FG, FT, CS, CP packages)
12 ps
DVPPIN Differential peak-to-peak input
voltage
External AC coupled 150 2000 mV
VIN Single-ended input voltage(2) DC coupled VMGTAVTT = 1.2V –200 VMGTAVTT mV
VCMIN Common mode input voltage DC coupled VMGTAVTT = 1.2V 2/3 VMGTAVTT –mV
RIN Differential input resistance 100 Ω
CEXT Recommended external AC coupling capacitor(3) 100 – nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in 7 Series FPGAs GTP Transceiver User Guide
(UG482) and can result in values lower than reported in this table.
2. Voltage measured at the pin referenced to ground.
3. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 3
Figure 3: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 4
Figure 4: Differential Peak-to-Peak Voltage
0
+V P
N
ds181_01_062014
Single-Ended
Peak-to-Peak
Voltage
0
+V
–V
P–N
ds181_02_062014
Differential
Peak-to-Peak
Voltage
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 51
Note: In Figure 4, differential peak-to-peak voltage = single-ended peak-to-peak voltage x 2.
Table 51 summarizes the DC specifications of the clock input of the GTP transceiver. Consult 7 Series FPGAs GTP Transceiver
User Guide (UG482) for further details.
GTP Transceiver Switching Characteristics
Consult 7 Series FPGAs GTP Transceiver User Guide (UG482) for further information.
Table 51: GTP Transceiver Clock DC Input Level Specification
Symbol DC Parameter Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 350 2000 mV
RIN Differential input resistance 100 Ω
CEXT Required external AC coupling capacitor 100 nF
Table 52: GTP Transceiver Performance
Symbol Description Output
Divider
Speed Grade
Units
-3 (1.0V) -2 (1.0V)
-2LE (1.0V)
-1 (1.0V)
-1LI (0.95V)
-1Q (1.0V)
-1M (1.0V)
-2LE (0.9V)
Package Type
FF
FB
SB
FG
FT
CS
CP
FF
FB
SB
RB
RS
FG
FT
CS
CP
FF
FB
SB
RB
RS
FG
FT
CS
CP
FF
FB
SB
FG
FT
CS
CP
FGTPMAX Maximum GTP transceiver data rate 6.6 6.25 6.6 6.25 3.75 3.75 3.75 3.75 Gb/s
FGTPMIN Minimum GTP transceiver data rate 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.500 Gb/s
FGTPRANGE PLL line rate range
1 3.2–6.6 3.2–6.6 3.2–3.75 3.2–3.75 Gb/s
2 1.6–3.3 1.6–3.3 1.6–3.2 1.6–3.2 Gb/s
4 0.8–1.65 0.8–1.65 0.8–1.6 0.8–1.6 Gb/s
8 0.5–0.825 0.5–0.825 0.5–0.8 0.5–0.8 Gb/s
FGTPPLLRANGE GTP transceiver PLL frequency
range
1.6–3.3 1.6–3.3 1.6–3.3 1.6–3.3 GHz
Table 53: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
FGTPDRPCLK GTPDRPCLK maximum frequency 175 175 156 156 125 MHz
Table 54: GTP Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequency range 60 660 MHz
TRCLK Reference clock rise time 20% – 80% 200 ps
TFCLK Reference clock fall time 80% – 20% 200 ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 60 %
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 52
X-Ref Target - Figure 5
Figure 5: Reference Clock Timing Parameters
Table 55: GTP Transceiver PLL/Lock Time Adaptation
Symbol Description Conditions All Speed Grades Units
Min Typ Max
TLOCK Initial PLL lock 1 ms
TDLOCK Clock recovery phase acquisition and
adaptation time.
After the PLL is locked to the
reference clock, this is the time it
takes to lock the clock data
recovery (CDR) to the data
present at the input.
50,000 2.3 x106UI
Table 56: GTP Transceiver User Clock Switching Characteristics(1)
Symbol Description Conditions
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
FTXOUT TXOUTCLK maximum frequency 412.500 412.500 234.375 234.375 234.375 MHz
FRXOUT RXOUTCLK maximum frequency 412.500 412.500 234.375 234.375 234.375 MHz
FTXIN TXUSRCLK maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
FRXIN RXUSRCLK maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
FTXIN2 TXUSRCLK2 maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
FRXIN2 RXUSRCLK2 maximum frequency 16-bit data path 412.500 412.500 234.375 234.375 234.375 MHz
Notes:
1. Clocking must be implemented as described in 7 Series FPGAs GTP Transceiver User Guide (UG482).
ds181_03_062811
80%
20%
T
FCLK
T
RCLK
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 53
Table 57: GTP Transceiver Transmitter Switching Characteristics
Symbol Description Condition Min Typ Max Units
FGTPTX Serial data rate range 0.500 FGTPMAX Gb/s
TRTX TX rise time 20%–80% 50 ps
TFTX TX fall time 80%–20% 50 ps
TLLSKEW TX lane-to-lane skew(1) 500 ps
VTXOOBVDPP Electrical idle amplitude 20 mV
TTXOOBTRANSITION Electrical idle transition time 140 ns
TJ6.6 Total Jitter(2)(3)
6.6 Gb/s 0.30 UI
DJ6.6 Deterministic Jitter(2)(3) 0.15 UI
TJ5.0 Total Jitter(2)(3)
5.0 Gb/s 0.30 UI
DJ5.0 Deterministic Jitter(2)(3) 0.15 UI
TJ4.25 Total Jitter(2)(3)
4.25 Gb/s 0.30 UI
DJ4.25 Deterministic Jitter(2)(3) 0.15 UI
TJ3.75 Total Jitter(2)(3)
3.75 Gb/s 0.30 UI
DJ3.75 Deterministic Jitter(2)(3) 0.15 UI
TJ3.2 Total Jitter(2)(3)
3.20 Gb/s(4) ––0.2UI
DJ3.2 Deterministic Jitter(2)(3) ––0.1UI
TJ3.2L Total Jitter(2)(3)
3.20 Gb/s(5) 0.32 UI
DJ3.2L Deterministic Jitter(2)(3) 0.16 UI
TJ2.5 Total Jitter(2)(3)
2.5 Gb/s(6) 0.20 UI
DJ2.5 Deterministic Jitter(2)(3) 0.08 UI
TJ1.25 Total Jitter(2)(3)
1.25 Gb/s(7) 0.15 UI
DJ1.25 Deterministic Jitter(2)(3) 0.06 UI
TJ500 Total Jitter(2)(3)
500 Mb/s ––0.1UI
DJ500 Deterministic Jitter(2)(3) 0.03 UI
Notes:
1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTP Quad).
2. Using PLL[0/1]_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. All jitter values are based on a bit-error ratio of 1e-12.
4. PLL frequency at 3.2 GHz and TXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and TXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and TXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and TXOUT_DIV = 4.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 54
Table 58: GTP Transceiver Receiver Switching Characteristics
Symbol Description Min Typ Max Units
FGTPRX Serial data rate RX oversampler not enabled 0.500 FGTPMAX Gb/s
TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data 10 ns
RXOOBVDPP OOB detect threshold peak-to-peak 60 150 mV
RXSST Receiver spread-spectrum
tracking(1) Modulated @ 33 kHz –5000 5000 ppm
RXRL Run length (CID) 512 UI
RXPPMTOL Data/REFCLK PPM offset tolerance –1250 1250 ppm
SJ Jitter Tolerance(2)
JT_SJ6.6 Sinusoidal Jitter(3) 6.6 Gb/s 0.44 UI
JT_SJ5.0 Sinusoidal Jitter(3) 5.0 Gb/s 0.44 UI
JT_SJ4.25 Sinusoidal Jitter(3) 4.25 Gb/s 0.44 UI
JT_SJ3.75 Sinusoidal Jitter(3) 3.75 Gb/s 0.44 UI
JT_SJ3.2 Sinusoidal Jitter(3) 3.2 Gb/s(4) 0.45 – UI
JT_SJ3.2L Sinusoidal Jitter(3) 3.2 Gb/s(5) 0.45 – UI
JT_SJ2.5 Sinusoidal Jitter(3) 2.5 Gb/s(6) 0.5 – UI
JT_SJ1.25 Sinusoidal Jitter(3) 1.25 Gb/s(7) 0.5 – UI
JT_SJ500 Sinusoidal Jitter(3) 500 Mb/s 0.4 UI
SJ Jitter Tolerance with Stressed Eye(2)
JT_TJSE3.2 Total Jitter with Stressed Eye(8) 3.2 Gb/s 0.70 UI
JT_TJSE6.6 6.6 Gb/s 0.70 UI
JT_SJSE3.2 Sinusoidal Jitter with Stressed
Eye(8)
3.2 Gb/s 0.1 UI
JT_SJSE6.6 6.6 Gb/s 0.1 UI
Notes:
1. Using RXOUT_DIV = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 1e–12.
3. The frequency of the injected sinusoidal jitter is 10 MHz.
4. PLL frequency at 3.2 GHz and RXOUT_DIV = 2.
5. PLL frequency at 1.6 GHz and RXOUT_DIV = 1.
6. PLL frequency at 2.5 GHz and RXOUT_DIV = 2.
7. PLL frequency at 2.5 GHz and RXOUT_DIV = 4.
8. Composite jitter.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 55
GTP Transceiver Protocol Jitter Characteristics
For Table 59 through Table 63, the 7 Series FPGAs GTP Transceiver User Guide (UG482) contains recommended settings for
optimal usage of protocol specific characteristics.
Table 59: Gigabit Ethernet Protocol Characteristics
Description Line Rate (Mb/s) Min Max Units
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ) 1250 0.24 UI
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance 1250 0.749 UI
Table 60: XAUI Protocol Characteristics
Description Line Rate (Mb/s) Min Max Units
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ) 3125 0.35 UI
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance 3125 0.65 UI
Table 61: PCI Express Protocol Characteristics(1)
Standard Description Line Rate (Mb/s) Min Max Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1 Total transmitter jitter 2500 0.25 UI
PCI Express Gen 2 Total transmitter jitter 5000 0.25 UI
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1 Total receiver jitter tolerance 2500 0.65 UI
PCI Express Gen 2(2) Receiver inherent timing error 5000 0.40 – UI
Receiver inherent deterministic timing error 0.30 UI
Notes:
1. Tested per card electromechanical (CEM) methodology.
2. Using common REFCLK.
Table 62: CEI-6G Protocol Characteristics
Description Line Rate (Mb/s) Interface Min Max Units
CEI-6G Transmitter Jitter Generation
Total transmitter jitter(1) 4976–6375 CEI-6G-SR 0.3 UI
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance(1) 4976–6375 CEI-6G-SR 0.6 UI
Notes:
1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 56
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
www.xilinx.com/products/technology/pci-express.html
Table 63: CPRI Protocol Characteristics
Description Line Rate (Mb/s) Min Max Units
CPRI Transmitter Jitter Generation
Total transmitter jitter
614.4 0.35 UI
1228.8 0.35 UI
2457.6 0.35 UI
3072.0 0.35 UI
4915.2 0.3 UI
6144.0 0.3 UI
CPRI Receiver Frequency Jitter Tolerance
Total receiver jitter tolerance
614.4 0.65 – UI
1228.8 0.65 – UI
2457.6 0.65 – UI
3072.0 0.65 – UI
4915.2(1) 0.60 – UI
6144.0(1) 0.60 – UI
Notes:
1. Tested to CEI-6G-SR.
Table 64: Maximum Performance for PCI Express Designs
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz
FUSERCLK User clock maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz
FUSERCLK2 User clock 2 maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz
FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 250.00 250.00 MHz
Notes:
1. Refer to PG054, 7 Series FPGAs Integrated Block for PCI Express Product Guide for specific supported core configurations.
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 57
XADC Specifications
Table 65: XADC Specifications
Parameter Symbol Comments/Conditions Min Typ Max Units
VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, –55°C Tj 125°C, Typical values at Tj=+40°C
ADC Accuracy(1)
Resolution 12 – Bits
Integral Nonlinearity(2) INL –40°C Tj100°C – – ±2 LSBs
–55°C Tj< –40°C; 100°C < Tj125°C – – ±3 LSBs
Differential Nonlinearity DNL No missing codes, guaranteed monotonic ±1 LSBs
Offset Error Unipolar –40°C Tj100°C – – ±8 LSBs
–55°C Tj< –40°C; 100°C < Tj125°C – ±12 LSBs
Bipolar –55°C Tj125°C – – ±4 LSBs
Gain Error ––±0.5 %
Offset Matching – – 4 LSBs
Gain Matching ––0.3 %
Sample Rate –– 1 MS/s
Signal to Noise Ratio(2) SNR FSAMPLE = 500KS/s, FIN =20kHz 60 – dB
RMS Code Noise External 1.25V reference 2 LSBs
On-chip reference 3 LSBs
Total Harmonic Distortion(2) THD FSAMPLE = 500KS/s, FIN =20kHz 70 – dB
Analog Inputs(3)
ADC Input Ranges Unipolar operation 0 1 V
Bipolar operation –0.5 +0.5 V
Unipolar common mode range (FS input) 0 +0.5 V
Bipolar common mode range (FS input) +0.5 +0.6 V
Maximum External Channel Input Ranges Adjacent analog channels set within these
ranges should not corrupt measurements on
adjacent channels
–0.1 – VCCADC V
Auxiliary Channel Full
Resolution Bandwidth
FRBW 250 – kHz
On-Chip Sensors
Temperature Sensor Error –40°C Tj100°C – ±4 °C
–55°C Tj< –40°C; 100°C < Tj125°C – ±6 °C
Supply Sensor Error –40°C Tj100°C – ±1 %
–55°C Tj< –40°C; 100°C < Tj125°C – ±2 %
Conversion Rate(4)
Conversion Time - Continuous tCONV Number of ADCCLK cycles 26 32 Cycles
Conversion Time - Event tCONV Number of CLK cycles 21 Cycles
DRP Clock Frequency DCLK DRP clock frequency 8 250 MHz
ADC Clock Frequency ADCCLK Derived from DCLK 1 26 MHz
DCLK Duty Cycle 40 – 60 %
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 58
Configuration Switching Characteristics
XADC Reference(5)
External Reference VREFP Externally supplied reference voltage 1.20 1.25 1.30 V
On-Chip Reference Ground VREFP pin to AGND,
–40°C Tj100°C
1.2375 1.25 1.2625 V
Ground VREFP pin to AGND,
–55°C Tj< –40°C; 100°C < Tj125°C
1.225 1.25 1.275 V
Notes:
1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature
is enabled.
2. Only specified for bitstream option XADCEnhancedLinearity = ON.
3. See the ADC chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for a
detailed description.
4. See the Timing chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for
a detailed description.
5. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted.
Table 66: Configuration Switching Characteristics
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
Power-up Timing Characteristics
TPL(1) Program latency 5.00 5.00 5.00 5.00 5.00 ms, Max
TPOR(1) Power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50 10/50 ms, Min/Max
Power-on reset (1 ms ramp rate time) 10/35 10/35 10/35 10/35 10/35 ms, Min/Max
TPROGRAM Program pulse width 250.00 250.00 250.00 250.00 250.00 ns, Min
CCLK Output (Master Mode)
TICCK Master CCLK output delay 150.00 150.00 150.00 150.00 150.00 ns, Min
TMCCKL Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max
TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max
FMCCK Master CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
Master CCLK frequency for AES encrypted x16 50.00 50.00 50.00 50.00 35.00 MHz, Max
FMCCK_START Master CCLK frequency at start of configuration 3.00 3.00 3.00 3.00 3.00 MHz, Typ
FMCCKTOL Frequency tolerance, master mode with respect
to nominal CCLK
±50 ±50 ±50 ±50 ±50 %, Max
CCLK Input (Slave Modes)
TSCCKL Slave CCLK clock minimum Low time 2.50 2.50 2.50 2.50 2.50 ns, Min
TSCCKH Slave CCLK clock minimum High time 2.50 2.50 2.50 2.50 2.50 ns, Min
FSCCK Slave CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
EMCCLK Input (Master Mode)
TEMCCKL External master CCLK Low time 2.50 2.50 2.50 2.50 2.50 ns, Min
TEMCCKH External master CCLK High time 2.50 2.50 2.50 2.50 2.50 ns, Min
FEMCCK External master CCLK frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
Table 65: XADC Specifications (Cont’d)
Parameter Symbol Comments/Conditions Min Typ Max Units
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 59
Internal Configuration Access Port
FICAPCK Internal configuration access port (ICAPE2)
clock frequency
100.00 100.00 100.00 100.00 70.00 MHz, Max
Master/Slave Serial Mode Programming Switching
TDCCK/
TCCKD
DIN setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min
TCCO DOUT clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max
SelectMAP Mode Programming Switching
TSMDCCK/
TSMCCKD
D[31:00] setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min
TSMCSCCK/
TSMCCKCS
CSI_B setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00 ns, Min
TSMWCCK/
TSMCCKW
RDWR_B setup/hold 10.00/0.00 10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00 ns, Min
TSMCKCSO CSO_B clock to out (330 Ω pull-up resistor
required)
7.00 7.00 7.00 7.00 8.00 ns, Max
TSMCO D[31:00] clock to out in readback 8.00 8.00 8.00 8.00 10.00 ns, Max
FRBCCK Readback frequency 100.00 100.00 100.00 100.00 70.00 MHz, Max
Boundary-Scan Port Timing Specifications
TTAPTCK/
TTCKTAP
TMS and TDI setup/hold 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00 ns, Min
TTCKTDO TCK falling edge to TDO output 7.00 7.00 7.00 7.00 8.50 ns, Max
FTCK TCK frequency 66.00 66.00 66.00 66.00 50.00 MHz, Max
BPI Flash Master Mode Programming Switching
TBPICCO(2) A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,
ADV_B clock to out
8.50 8.50 8.50 8.50 10.00 ns, Max
TBPIDCC/
TBPICCD
D[15:00] setup/hold 4.00/0.00 4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00 ns, Min
SPI Flash Master Mode Programming Switching
TSPIDCC/
TSPICCD
D[03:00] setup/hold 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00 ns, Min
TSPICCM MOSI clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max
TSPICCFC FCS_B clock to out 8.00 8.00 8.00 8.00 9.00 ns, Max
STARTUPE2 Ports
TUSRCCLKO STARTUPE2 USRCCLKO input to CCLK output 0.50/6.00 0.50/6.70 0.50/7.50 0.50/7.50 0.50/7.50 ns,
Min/Max
FCFGMCLK STARTUPE2 CFGMCLK output frequency 65.00 65.00 65.00 65.00 65.00 MHz, Typ
FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency
tolerance
±50 ±50 ±50 ±50 ±50 %, Max
Table 66: Configuration Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 60
eFUSE Programming Conditions
Table 67 lists the programming conditions specifically for eFUSE. For more information, see 7 Series FPGA Configuration User
Guide (UG470).
Revision History
The following table shows the revision history for this document:
Device DNA Access Port
FDNACK DNA access port (DNA_PORT) 100.00 100.00 100.00 100.00 70.00 MHz, Max
Notes:
1. To support longer delays in configuration, use the design solutions described in 7 Series FPGA Configuration User Guide (UG470).
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Table 67: eFUSE Programming Conditions(1)
Symbol Description Min Typ Max Units
IFS VCCAUX supply current 115 mA
TjTemperature range 15 125 °C
Notes:
1. The FPGA must not be configured during eFUSE programming.
Date Version Description
09/26/2011 1.0 Initial Xilinx release.
11/07/2011 1.1 Revised the VOCM specification in Table 11. Updated the AC Switching Characteristics based upon the
ISE 13.3 software v1.02 speed specification throughout document including Table 13 and Table 14.
Added MMCM_TFBDELAY while adding MMCM_ to the symbol names of a few specifications in
Table 37 and PLL to the symbol names in Table 38. In Table 39 through Table 46, updated the pin-to-
pin description with the SSTL15 standard. Updated units in Table 46.
02/13/2012 1.2 Updated the Artix-7 family of devices listed throughout the entire data sheet. Updated the AC Switching
Characteristics based upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00
for the -2L speed grade.
Updated summary description on page 1. In Table 2, revised VCCO for the 3.3V HR I/O banks and
updated Tj. Updated the notes in Table 5. Added MGTAVCC and MGTAVTT power supply ramp times
to Table 7. Rearranged Table 8, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12,
SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I,
DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 9 and Table 10. Revised the
specifications in Table 11. Revised VIN in Table 50. Updated the eFUSE Programming Conditions
section and removed the endurance table. Added the table. Revised FTXIN and FRXIN in Table 56.
Revised ICCADC and updated Note 1 in Table 65. Revised DDR LVDS transmitter data width in
Table 15. Removed notes from Table 27 as they are no longer applicable. Updated specifications in
Table 66. Updated Note 1 in Table 36.
Table 66: Configuration Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units1.0V 0.95V 0.9V
-3 -2/-2LE -1 -1LI -2LE
Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
DS181 (v1.24) April 4, 2018 www.xilinx.com
Product Specification 61
06/01/2012 1.3 Reorganized entire data sheet including adding Table 43 and Table 47.
Updated TSOL in Table 1. Updated IBATT and added RIN_TERM to Table 3. Updated Power-On/Off Power
Supply Sequencing section with regards to GTP transceivers. In Table 8, updated many parameters
including SSTL135 and SSTL135_R. Removed VOX column and added DIFF_HSUL_12 to Table 10.
Updated VOL in Table 11. Updated Table 15 and removed notes 2 and 3. Updated Table 16.
Updated the AC Switching Characteristics based upon the ISE 14.1 software v1.03 for the -3, -2, -2L
(1.0V), -1, and v1.01 for the -2L (0.9V) speed specifications throughout the document.
In Table 30, updated Reset Delays section including Note 10 and Note 11. In Table 56, replaced
FTXOUT with FGLK. Updated many of the XADC specifications in Table 65 and added Note 2. Updated
and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from
Table 66 to Table 37 and Table 38.
09/20/2012 1.4 In Table 1, updated the descriptions, changed VIN and Note 2, and added Note 4. In Table 2, changed
descriptions and notes. Updated parameters in Table 3. Added Table 4. Revised the Power-On/Off
Power Supply Sequencing section. Updated standards and specifications in Table 8, Table 9, and
Table 10. Removed the XC7A350T device from data sheet.
Updated the AC Switching Characteristics section to the ISE 14.2 speed specifications throughout the
document. Updated the IOB Pad Input/Output/3-State discussion and changed Table 18 by adding
TIOIBUFDISABLE. Removed many of the combinatorial delay specifications and TCINCK/TCKCIN from
Table 27.Changed FPFDMAX conditions in Table 37 and Table 38. Updated the GTP Transceiver
Specifications section, moved the GTP Transceiver DC characteristics section to the overall DC
Characteristics section, and added the GTP Transceiver Protocol Jitter Characteristics section. In
Table 65, updated Note 1. In Table 66, updated TPOR.
02/01/2013 1.5 Updated the AC Switching Characteristics based upon the 14.4/2012.4 device pack for ISE 14.4 and
Vivado 2012.4, both at v1.07 for the -3, -2, -2L (1.0V), -1 speed specifications, and v1.05 for the -2L
(0.9V) speed specifications throughout the document. Production changes to Table 13 and Table 14
for -3, -2, -2L (1.0V), -1 speed specifications.
Revised IDCIN and IDCOUT and added Note 5 in Table 1. Added Note 2 to Table 2. Updated Table 5.
Added minimum current specifications to Table 6. Removed SSTL12 and HSTL_I_12 from Table 8.
Removed DIFF_SSTL12 from Table 10. Updated Table 13. Added a 2:1 memory controller section to
Table 16. Updated Note 1 in Table 34. Revised Table 36. Updated Note 1 and Note 2 in Table 49.
Updated DVPPIN in Table 50. Updated VIDIFF in Table 51. Removed TLOCK and TPHASE and revised
FGCLK in Table 54. Updated TDLOCK in Table 55. Updated Table 56. In Table 57, updated TRTX, TFTX,
VTXOOBVDPP , and revised Note 1 through Note 7. In Table 58, updated RXSST and RXPPMTOL and
revised Note 4 through Note 7. In Table 63, revised and added Note 1.
Revised the maximum external channel input ranges in Table 65. In Table 66, revised FMCCK and
added the Internal Configuration Access Port section.
04/17/2013 1.6 Updated the AC Switching Characteristics based upon v1.07 of the ISE 14.5 and Vivado 2013.1 for the
-3, -2, -2L (1.0V), and -1 speed specifications, and v1.05 for the -2L (0.9V) speed specifications.
Production changes to Table 13 and Table 14 for -2L (0.9V) speed specifications.