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K64F Sub-Family Datasheet

NXP USA Inc.

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Datasheet

Kinetis K64F Sub-Family Data
Sheet
120 MHz ARM® Cortex®-M4-based Microcontroller with FPU
The K64 product family members are optimized for cost-sensitive
applications requiring low-power, USB/Ethernet connectivity, and
up to 256 KB of embedded SRAM. These devices share the
comprehensive enablement and scalability of the Kinetis family.
This product offers:
Run power consumption down to 250 μA/MHz. Static
power consumption down to 5.8 μA with full state retention
and 5 μs wakeup. Lowest Static mode down to 339 nA
USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO
Vreg, with USB device crystal-less operation
10/100 Mbit/s Ethernet MAC with MII and RMII interfaces
Performance
Up to 120 MHz ARM® Cortex®-M4 core with DSP
instructions and floating point unit
Memories and memory interfaces
Up to 1 MB program flash memory and 256 KB RAM
Upto 128 KB FlexNVM and 4 KB FlexRAM on devices
with FlexMemory
FlexBus external bus interface
System peripherals
Multiple low-power modes, low-leakage wake-up unit
Memory protection unit with multi-master protection
16-channel DMA controller
External watchdog monitor and software watchdog
Security and integrity modules
Hardware CRC module
Hardware random-number generator
Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
128-bit unique identification (ID) number per chip
Analog modules
Two 16-bit SAR ADCs
Two 12-bit DACs
Three analog comparators (CMP)
Voltage reference
Communication interfaces
Ethernet controller with MII and RMII interface
USB full-/low-speed On-the-Go controller
Controller Area Network (CAN) module
Three SPI modules
Three I2C modules. Support for up to 1 Mbit/s
Six UART modules
Secure Digital Host Controller (SDHC)
I2S module
Timers
Two 8-channel Flex-Timers (PWM/Motor control)
Two 2-channel FlexTimers (PWM/Quad decoder)
IEEE 1588 timers
32-bit PITs and 16-bit low-power timers
Real-time clock
Programmable delay block
Clocks
3 to 32 MHz and 32 kHz crystal oscillator
PLL, FLL, and multiple internal oscillators
48 MHz Internal Reference Clock (IRC48M)
Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): –40 to 105°C
MK64FN1M0Vxx12
MK64FX512Vxx12
121 XFBGA
8 x 8 x 0.5 mm Pitch
0.65 mm
144 LQFP
20 x 20 x 1.6 mm Pitch
0.5 mm
144 MAPBGA
13 x 13 x 1.46 mm
Pitch 1 mm
100 QFP
14 x 14 x 1.7 mm Pitch
0.5 mm
NXP Semiconductors K64P144M120SF5
Data Sheet: Technical Data Rev. 7, 10/2016
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information1
Part Number Memory Maximum number of I\O's
Flash SRAM (KB)
MK64FX512VLL12 512 KB 256 66
MK64FN1M0VLL12 1 MB 256 66
MK64FX512VDC12 512 KB 256 83
MK64FN1M0VDC12 1 MB 256 83
MK64FX512VLQ12 512 KB 256 100
MK64FN1M0VLQ12 1 MB 256 100
MK64FX512VMD12 512 KB 256 100
MK64FN1M0VMD12 1 MB 256 100
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type Description Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Solution Advisor
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K60PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K64P144M120SF5RM 1
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
K64P144M120SF51
Package
drawing
Package dimensions are provided in package drawings. MAPBGA 144-pin:
98ASA00222D1
LQFP 144-pin:
98ASS23177W1
LQFP 100-pin:
98ASS23308W1
XFBGA 121-pin:
98ASA00595D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Memories and Memory Interfaces
Program
flash RAM
12-bit DAC
x2
6-bit DAC
x3
CRC
Analog Timers Communication InterfacesSecurity
and Integrity
SPI
x3
FlexMemory
Clocks
Frequency-
Core
Debug
interfaces DSP
Interrupt
controller
comparator
x3
Analog
Voltage
reference
Secure
Digital
Low power
timer
Human-Machine
Interface (HMI)
GPIO
System
protection
Memory
DMA
Internal
watchdogs
and external
Low-leakage
wakeup
locked loop
Serial
programming
interface
Phase-
locked loop
reference
Internal
clocks
Programmable
delay block
timers
interrupt
Periodic
External
bus
real-time
Independent
clock
oscillators
Low/high
frequency
UART
x6
®
Cortex™-M4ARM
Kinetis K64 Family
USB charger
detect
USB voltage
regulator
USB OTG
LS/FS
USB LS/FS
transceiver
IS
2
Floating-
point unit
x3
IC
2
Timers
x2 (8ch)
x2 (2ch)
CAN
x1
IEEE 1588
Timers
Ethernet
IEEE 1588
Hardware
encryption
number
Random
generator
16-bit ADC
x2
Figure 1. K64 block diagram
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements.....6
2.2.2 LVD and POR operating requirements............. 8
2.2.3 Voltage and current operating behaviors.......... 8
2.2.4 Power mode transition operating behaviors......10
2.2.5 Power consumption operating behaviors.......... 11
2.2.6 EMC radiated emissions operating behaviors...16
2.2.7 Designing with radiated emissions in mind....... 17
2.2.8 Capacitance attributes...................................... 17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications............................... 17
2.3.2 General switching specifications....................... 18
2.4 Thermal specifications.....................................................19
2.4.1 Thermal operating requirements....................... 19
2.4.2 Thermal attributes............................................. 20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 Debug trace timing specifications..................... 21
3.1.2 JTAG electricals................................................ 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications........................................... 25
3.3.2 IRC48M specifications...................................... 27
3.3.3 Oscillator electrical specifications..................... 28
3.3.4 32 kHz oscillator electrical characteristics.........30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash (FTFE) electrical specifications............... 31
3.4.2 EzPort switching specifications......................... 36
3.4.3 Flexbus switching specifications....................... 36
3.5 Security and integrity modules........................................ 39
3.6 Analog............................................................................. 39
3.6.1 ADC electrical specifications.............................40
3.6.2 CMP and 6-bit DAC electrical specifications.....44
3.6.3 12-bit DAC electrical characteristics................. 46
3.6.4 Voltage reference electrical specifications........ 49
3.7 Timers..............................................................................50
3.8 Communication interfaces............................................... 50
3.8.1 Ethernet switching specifications...................... 51
3.8.2 USB electrical specifications............................. 53
3.8.3 USB DCD electrical specifications.................... 53
3.8.4 USB VREG electrical specifications..................54
3.8.5 CAN switching specifications............................ 54
3.8.6 DSPI switching specifications (limited voltage
range)................................................................55
3.8.7 DSPI switching specifications (full voltage
range)................................................................56
3.8.8 Inter-Integrated Circuit Interface (I2C) timing....58
3.8.9 UART switching specifications.......................... 60
3.8.10 SDHC specifications......................................... 60
3.8.11 I2S switching specifications.............................. 61
4 Dimensions............................................................................. 67
4.1 Obtaining package dimensions....................................... 67
5 Pinout......................................................................................67
5.1 K64 Signal Multiplexing and Pin Assignments.................67
5.2 Unused analog interfaces................................................75
5.3 K64 Pinouts..................................................................... 76
6 Ordering parts......................................................................... 81
6.1 Determining valid orderable parts....................................81
7 Part identification.....................................................................82
7.1 Description.......................................................................82
7.2 Format............................................................................. 82
7.3 Fields............................................................................... 82
7.4 Example...........................................................................83
8 Terminology and guidelines.................................................... 83
8.1 Definitions........................................................................83
8.2 Examples.........................................................................84
8.3 Typical-value conditions.................................................. 84
8.4 Relationship between ratings and operating
requirements....................................................................85
8.5 Guidelines for ratings and operating requirements..........85
9 Revision History...................................................................... 86
4Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free 260 °C 2
Solder temperature, leaded 245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level 3 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
-500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Ratings
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 5
NXP Semiconductors
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current 185 mA
VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V
VDRTC_WAKEU
P
RTC Wakeup input voltage –0.3 VBAT + 0.3 V
VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VREGIN USB regulator input –0.3 6.0 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
General
6Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
VIH Input high voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
V
V
VIL Input low voltage
2.7 V ≤ VDD ≤ 3.6 V
1.7 V ≤ VDD ≤ 2.7 V
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICDIO Digital pin negative DC injection current — single pin
• VIN < VSS-0.3V -5 — mA
1
IICAIO Analog2, EXTAL, and XTAL pin DC injection current
— single pin
• VIN < VSS-0.3V (Negative current injection)
• VIN > VDD+0.3V (Positive current injection)
-5
+5
mA
3
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection
-25
+25
mA
VODPU Open drain pullup voltage level VDD VDD V4
VRAM VDD voltage required to retain RAM 1.2 V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-
VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative
injection currents.
4. Open drain outputs must be pulled to VDD.
General
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 7
NXP Semiconductors
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— 80 — mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— 60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — high drive strength
Table continues on the next page...
General
8Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
V
V
Output high voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
V
V
IOHT Output high current total for all ports 100 mA
VOH_RTC_WA
KEUP
Output high voltage — high drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
VBAT – 0.5
VBAT – 0.5
V
V
Output high voltage — low drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
VBAT – 0.5
VBAT – 0.5
V
V
IOH_RTC_WAK
EUP
Output high current total for RTC_WAKEUP pins 100 mA
VOL Output low voltage — high drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
0.5
0.5
V
V
Output low voltage — low drive strength
2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
0.5
0.5
V
V
IOLT Output low current total for all ports 100 mA
VOL_RTC_WA
KEUP
Output low voltage — high drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
0.5
0.5
V
V
Output low voltage — low drive strength
2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
0.5
0.5
V
V
IOL_RTC_WAK
EUP
Output low current total for RTC_WAKEUP pins 100 mA
IIN Input leakage current (per pin) for full temperature
range
1 μA 1
IIN Input leakage current (per pin) at 25°C 0.025 μA 1
IIN_RTC_WAK
EUP
Input leakage current (per RTC_WAKEUP pin) for full
temperature range
1 μA
IIN_RTC_WAK
EUP
Input leakage current (per RTC_WAKEUP pin) at
25°C
0.025 μA
Table continues on the next page...
General
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 9
NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Max. Unit Notes
IOZ Hi-Z (off-state) leakage current (per pin) 0.25 μA
IOZ_RTC_WAK
EUP
Hi-Z (off-state) leakage current (per RTC_WAKEUP
pin)
0.25 μA
RPU Internal pullup resistors (except RTC_WAKEUP pins) 20 50 2
RPD Internal pulldown resistors (except RTC_WAKEUP
pins)
20 50 kΩ 3
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSxRUN recovery times in the following table
assume this clock configuration:
CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol Description Min. Max. Unit Notes
tPOR After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
300 μs
VLLS0 RUN 156 μs
VLLS1 RUN 156 μs
VLLS2 RUN 78 μs
VLLS3 RUN 78 μs
LLS RUN 4.8 μs
VLPS RUN 4.5 μs
STOP RUN 4.5 μs
General
10 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current See note mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
@ 3.0V
31.1
31
36.65
36.75
mA
mA
2
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
@ 3.0V
@ 25°C
@ 105°C
42.7
40
48.33
48.35
41.60
51.50
mA
mA
mA
3, 4
IDD_WAIT Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
— 17.9 — mA 2
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
6.9 — mA 5
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
1.0 — mA 6
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
1.7 — mA 7
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
— 0.678 — mA 8
IDD_STOP Stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.49
1.18
3.0
1.24
4.3
12.5
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
57
291
927.3
139.31
679.33
1869.85
μA
μA
μA
IDD_LLS Low leakage stop mode current at 3.0 V 9
Table continues on the next page...
General
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 11
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
@ –40 to 25°C
@ 70°C
@ 105°C
5.8
26.7
114.9
10.48
47.99
196.49
μA
μA
μA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
4.4
21
90.2
5.54
36.46
150.17
μA
μA
μA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
2.1
6.84
29.4
2.34
10.36
46.74
μA
μA
μA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.817
3.97
21.3
0.86
5.77
33.99
μA
μA
μA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ –40 to 25°C
@ 70°C
@ 105°C
0.52
3.67
21.20
0.62
5.7
34.9
μA
μA
μA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ –40 to 25°C
@ 70°C
@ 105°C
0.339
3.36
20.3
0.412
4.2
29.9
μA
μA
μA
IDD_VBAT Average current with RTC and 32 kHz disabled
@ 1.8 V
@ –40 to 25°C
@ 70°C
@ 105°C
@ 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.16
0.55
2.5
0.18
0.66
2.92
0.19
0.72
3.68
0.21
0.86
4.30
μA
μA
μA
μA
μA
μA
Table continues on the next page...
General
12 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_VBAT Average current when CPU is not accessing
RTC registers
@ 1.8 V
@ –40 to 25°C
@ 70°C
@ 105°C
@ 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C
0.59
1.0
3.0
0.71
1.22
3.5
0.70
1.30
4.42
0.84
1.59
5.15
μA
μA
μA
μA
μA
μA
10
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 Mhz FlexBus clock, and 20 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus clock, 30 MHz Flexbus clock, and 20 MHz flash clock. MCG configured
for PEE mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Data reflects devices with 256 KB of RAM.
10. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
Table continues on the next page...
General
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 13
NXP Semiconductors
Table 7. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
STOP
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
nA
I48MIRC 48 Mhz internal reference clock 350 350 350 350 350 350 µA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42 42 42 42 42 42 µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
General
14 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFE
Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash
Run Mode Current Consumption vs Core Frequency
All Peripheral Clk Gates
ALLOFF
ALLON
Clk Ratio
Core-Bus-
Flaxbus-Flash
Core Freq (MHz)
Current Consumption on VDD (A)
40.00E-03
000.00E+00
10.00E-03
15.00E-03
20.00E-03
25.00E-03
30.00E-03
35.00E-03
5.00E-03
'1-1-1
1
'1-1-1
2
'1-1-1
4
'1-1-1
6.25
'1-1-1
12.5
'1-1-1
25
'1-2-3
75
'1-1-2
50
'1-2-4
100
'1-2-5
120
Figure 3. Run mode supply current vs. core frequency
General
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 15
NXP Semiconductors
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
144 LQFP
VRE1 Radiated emissions voltage, band 1 0.15–50 16 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 22 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 21 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 16 dBμV
VRE_IEC IEC level 0.15–1000 L 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
General
16 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins 7 pF
CIN_D Input capacitance: digital pins 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock 120 MHz
System and core clock when Full Speed USB in
operation
20 — MHz
fENET System and core clock when ethernet in operation
10 Mbps
100 Mbps
5
50
MHz
fBUS Bus clock 60 MHz
FB_CLK FlexBus clock 50 MHz
fFLASH Flash clock 25 MHz
Table continues on the next page...
General
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 17
NXP Semiconductors
Table 10. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fLPTMR LPTMR clock 25 MHz
VLPR mode1
fSYS System and core clock 4 MHz
fBUS Bus clock 4 MHz
FB_CLK FlexBus clock 4 MHz
fFLASH Flash clock 0.8 MHz
fERCLK External reference clock 16 MHz
fLPTMR_pin LPTMR clock 25 MHz
fLPTMR_ERCLK LPTMR external reference clock 16 MHz
fFlexCAN_ERCLK FlexCAN external reference clock 8 MHz
fI2S_MCLK I2S master clock 12.5 MHz
fI2S_BCLK I2S bit clock 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, timers, and I2C signals.
Table 11. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
50 — ns 3
External reset pulse width (digital glitch filter disabled) 100 ns 3
Mode select (EZP_CS) hold time after reset
deassertion
2 Bus clock
cycles
Port rise and fall time (high drive strength) - 3 V
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
8
6
18
ns
ns
ns
4
Table continues on the next page...
General
18 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 11. General switching specifications (continued)
Symbol Description Min. Max. Unit Notes
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
12 ns
Port rise and fall time (high drive strength) - 5 V
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
6
4
24
14
ns
ns
ns
ns
4
Port rise and fall time (low drive strength) - 3 V
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
12
6
24
16
ns
ns
ns
ns
5
Port rise and fall time (low drive strength) - 5 V
Slew disabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
Slew enabled
1.71 ≤ VDD ≤ 2.7V
2.7 ≤ VDD ≤ 3.6V
17
10
36
20
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 25 pF load
5. 15 pF load
2.4 Thermal specifications
General
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 19
NXP Semiconductors
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature1–40 105 °C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 13. Thermal attributes
Board type Symbol Descriptio
n
144 LQFP 144
MAPBGA
121
XFBGA
100 LQFP Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
51 38.1 33.3 51 °C/W 1
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
43 21.6 21.1 39 °C/W 1
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
42 30.8 26.2 41 °C/W 1
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
36 18 17.8 32 °C/W 1
— RθJB Thermal
resistance,
junction to
board
30 16.5 16.3 24 °C/W 2
— RθJC Thermal
resistance,
11 8.9 12 11 °C/W 3
Table continues on the next page...
General
20 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 13. Thermal attributes (continued)
Board type Symbol Descriptio
n
144 LQFP 144
MAPBGA
121
XFBGA
100 LQFP Unit Notes
junction to
case
ΨJT Thermal
characteriza
tion
parameter,
junction to
package top
outside
center
(natural
convection)
2 0.9 0.2 2 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 14. Debug trace operating behaviors
Symbol Description Min. Max. Unit
Tcyc Clock period Frequency dependent MHz
Twl Low pulse width 2 ns
Twh High pulse width 2 ns
TrClock and data rise time 3 ns
TfClock and data fall time 3 ns
TsData setup 1.5 ns
ThData hold 1 ns
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 21
NXP Semiconductors
TRACECLK
Tr
Twh
Tf
Tcyc
Twl
Figure 5. TRACE_CLKOUT specifications
Th
Ts Ts Th
TRACE_CLKOUT
TRACE_D[3:0]
Figure 6. Trace data specifications
3.1.2 JTAG electricals
Table 15. JTAG limited voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
J1 TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
0
0
10
25
50
MHz
J2 TCLK cycle period 1/J1 ns
J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
20
10
ns
ns
ns
J4 TCLK rise and fall times 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 ns
J6 Boundary scan input data hold time after TCLK rise 2.6 ns
J7 TCLK low to boundary scan output data valid 25 ns
J8 TCLK low to boundary scan output high-Z 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 ns
J10 TMS, TDI input data hold time after TCLK rise 1 ns
Table continues on the next page...
Peripheral operating requirements and behaviors
22 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 15. JTAG limited voltage range electricals (continued)
Symbol Description Min. Max. Unit
J11 TCLK low to TDO data valid 17 ns
J12 TCLK low to TDO high-Z 17 ns
J13 TRST assert time 100 ns
J14 TRST setup time (negation) to TCLK high 8 ns
Table 16. JTAG full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 TCLK frequency of operation
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
0
0
0
10
20
40
MHz
J2 TCLK cycle period 1/J1 ns
J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug
50
25
12.5
ns
ns
ns
J4 TCLK rise and fall times 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 ns
J6 Boundary scan input data hold time after TCLK rise 0 ns
J7 TCLK low to boundary scan output data valid 25 ns
J8 TCLK low to boundary scan output high-Z 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 ns
J10 TMS, TDI input data hold time after TCLK rise 2.9 ns
J11 TCLK low to TDO data valid 22.1 ns
J12 TCLK low to TDO high-Z 22.1 ns
J13 TRST assert time 100 ns
J14 TRST setup time (negation) to TCLK high 8 ns
J2
J3 J3
J4 J4
TCLK (input)
Figure 7. Test clock input timing
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 23
NXP Semiconductors
J7
J8
J7
J5 J6
Input data valid
Output data valid
Output data valid
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Figure 8. Boundary scan (JTAG) timing
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
TCLK
TDI/TMS
TDO
TDO
TDO
Figure 9. Test Access Port timing
Peripheral operating requirements and behaviors
24 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
J14
J13
TCLK
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 17. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 39.0625 kHz
Iints Internal reference (slow clock) current 20 µA
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
± 0.3 ± 0.6 %fdco 1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
± 0.2 ± 0.5 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
± 0.5 ± 2 %fdco 1 , 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
± 0.3 ± 1 %fdco 1
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
4 — MHz
fintf_t Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3 5 MHz
Iintf Internal reference (fast clock) current 25 µA
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 25
NXP Semiconductors
Table 17. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— kHz
FLL
ffll_ref FLL reference frequency range 31.25 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS=01)
1280 × ffll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × ffll_ref
80 83.89 100 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
23.99 MHz 5, 6
Mid range (DRS=01)
1464 × ffll_ref
— 47.97 — MHz
Mid-high range (DRS=10)
2197 × ffll_ref
— 71.99 — MHz
High range (DRS=11)
2929 × ffll_ref
— 95.98 — MHz
Jcyc_fll FLL period jitter
• fDCO = 48 MHz
• fDCO = 98 MHz
180
150
ps
tfll_acquire FLL target frequency acquisition time 1 ms 7
PLL
fvco VCO operating frequency 48.0 120 MHz
Ipll PLL operating current
PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 48)
— 1060 — µA 8
Ipll PLL operating current
PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
= 2 MHz, VDIV multiplier = 24)
— 600 — µA 8
fpll_ref PLL reference frequency range 2.0 4.0 MHz
Jcyc_pll PLL period jitter (RMS)
• fvco = 48 MHz
• fvco = 120 MHz
120
80
ps
ps
9
Jacc_pll PLL accumulated jitter over 1µs (RMS) 9
Table continues on the next page...
Peripheral operating requirements and behaviors
26 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 17. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
fvco = 48 MHz
• fvco = 120 MHz
1350
600
ps
ps
Dlock Lock entry frequency tolerance ± 1.49 ± 2.98 %
Dunl Lock exit frequency tolerance ± 4.47 ± 5.97 %
tpll_lock Lock detector detection time 150 × 10-6
+ 1075(1/
fpll_ref)
s10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 IRC48M specifications
Table 18. IRC48M specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
IDD48M Supply current 400 500 μA
firc48m Internal reference frequency 48 MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over full
temperature
Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
± 0.5
± 0.5
± 1.5
± 2.0
%firc48m
1
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
± 0.5
± 1.5
%firc48m
1
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 27
NXP Semiconductors
Table 18. IRC48M specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over 0 to 85 °C
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
± 0.5
± 1.0
%firc48m
1
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
over voltage and temperature
± 0.1 %fhost 2
Jcyc_irc48m Period Jitter (RMS) 35 150 ps
tirc48mst Startup time 2 3 μs 3
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean ± 3 sigma)
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by setting USB_CLK_RECOVER_IRC_EN[IRC_EN]=1.
3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz
500
200
300
950
1.2
1.5
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high-gain mode (HGO=1)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz
25
400
500
2.5
3
4
μA
μA
μA
mA
mA
mA
1
Table continues on the next page...
Peripheral operating requirements and behaviors
28 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 19. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
CxEXTAL load capacitance 2, 3
CyXTAL load capacitance 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 —
Feedback resistor — high-frequency, low-power
mode (HGO=0)
— — —
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 —
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — —
Series resistor — low-frequency, high-gain
mode (HGO=1)
— 200 —
Series resistor — high-frequency, low-power
mode (HGO=0)
— — —
Series resistor — high-frequency, high-gain
mode (HGO=1)
0
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 29
NXP Semiconductors
3.3.3.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 32 MHz
fec_extal Input clock frequency (external clock mode) 50 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 750 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1 32 kHz oscillator DC electrical specifications
Table 21. 32kHz oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit
VBAT Supply voltage 1.71 3.6 V
RFInternal feedback resistor 100
Table continues on the next page...
Peripheral operating requirements and behaviors
30 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 21. 32kHz oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
Cpara Parasitical capacitance of EXTAL32 and
XTAL32
5 7 pF
Vpp1Peak-to-peak amplitude of oscillation 0.6 V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.4.2 32 kHz oscillator frequency specifications
Table 22. 32 kHz oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal 32.768 kHz
tstart Crystal start-up time 1000 ms 1
fec_extal32 Externally provided input clock frequency 32.768 kHz 2
vec_extal32 Externally provided input clock amplitude 700 VBAT mV 2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
3.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 23. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm8 Program Phrase high-voltage time 7.5 18 μs
thversscr Erase Flash Sector high-voltage time 13 113 ms 1
thversblk128k Erase Flash Block high-voltage time for 128 KB 104 904 ms 1
thversblk512k Erase Flash Block high-voltage time for 512 KB 416 3616 ms 1
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 31
NXP Semiconductors
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1blk128k
trd1blk512k
Read 1s Block execution time
128 KB data flash
512 KB program flash
0.5
1.8
ms
ms
trd1sec4k Read 1s Section execution time (4 KB flash) 100 μs 1
tpgmchk Program Check execution time 95 μs 1
trdrsrc Read Resource execution time 40 μs 1
tpgm8 Program Phrase execution time 90 150 μs
tersblk128k
tersblk512k
Erase Flash Block execution time
128 KB data flash
512 KB program flash
110
435
925
3700
ms
ms
2
tersscr Erase Flash Sector execution time 15 115 ms 2
tpgmsec1k Program Section execution time (1KB flash) 5 ms
trd1allx
trd1alln
Read 1s All Blocks execution time
FlexNVM devices
Program flash only devices
2.2
3.4
ms
ms
trdonce Read Once execution time 30 μs 1
tpgmonce Program Once execution time 70 μs
tersall Erase All Blocks execution time 870 7400 ms 2
tvfykey Verify Backdoor Access Key execution time 30 μs 1
tswapx01
tswapx02
tswapx04
tswapx08
Swap Control execution time
control code 0x01
control code 0x02
control code 0x04
control code 0x08
200
70
70
150
150
30
μs
μs
μs
μs
tpgmpart32k
tpgmpart128k
Program Partition for EEPROM execution time
32 KB FlexNVM
128 KB FlexNVM
70
75
ms
ms
tsetramff
tsetram32k
tsetram64k
tsetram128k
Set FlexRAM Function execution time:
Control Code 0xFF
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
70
0.8
1.3
2.4
1.2
1.9
3.1
μs
ms
ms
ms
Table continues on the next page...
Peripheral operating requirements and behaviors
32 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 24. Flash command timing specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
teewr8bers Byte-write to erased FlexRAM location
execution time
175 275 μs 3
teewr8b32k
teewr8b64k
teewr8b128k
Byte-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
385
475
650
1700
2000
2350
μs
μs
μs
teewr16bers 16-bit write to erased FlexRAM location
execution time
175 275 μs
teewr16b32k
teewr16b64k
teewr16b128k
16-bit write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
385
475
650
1700
2000
2350
μs
μs
μs
teewr32bers 32-bit write to erased FlexRAM location
execution time
360 550 μs
teewr32b32k
teewr32b64k
teewr32b128k
32-bit write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup
630
810
1200
2000
2250
2650
μs
μs
μs
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
3.4.1.3 Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage flash
programming operation
3.5 7.5 mA
IDD_ERS Average current adder during high voltage flash
erase operation
1.5 4.0 mA
3.4.1.4 Reliability specifications
Table 26. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 years
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 33
NXP Semiconductors
Table 26. NVM reliability specifications (continued)
Symbol Description Min. Typ.1Max. Unit Notes
tnvmretp1k Data retention after up to 1 K cycles 20 100 years
nnvmcycp Cycling endurance 10 K 50 K cycles 2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles 5 50 years
tnvmretd1k Data retention after up to 1 K cycles 20 100 years
nnvmcycd Cycling endurance 10 K 50 K cycles 2
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance 5 50 years
tnvmretee10 Data retention up to 10% of write endurance 20 100 years
nnvmcycee Cycling endurance for EEPROM backup 20 K 50 K cycles 2
nnvmwree16
nnvmwree128
nnvmwree512
nnvmwree2k
nnvmwree4k
Write endurance
EEPROM backup to FlexRAM ratio = 16
EEPROM backup to FlexRAM ratio = 128
EEPROM backup to FlexRAM ratio = 512
EEPROM backup to FlexRAM ratio = 2,048
EEPROM backup to FlexRAM ratio = 4,096
140 K
1.26 M
5 M
20 M
40 M
400 K
3.2 M
12.8 M
50 M
100 M
writes
writes
writes
writes
writes
3
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the
cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values
assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
3.4.1.5 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Peripheral operating requirements and behaviors
34 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Writes_subsystem = × Write_efficiency × n
EEPROM – 2 × EEESPLIT × EEESIZE
EEESPLIT × EEESIZE nvmcycee
where
Writes_subsystem — minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
EEPROM — allocated FlexNVM for each EEPROM subsystem based on
DEPART; entered with the Program Partition command
EEESPLIT — FlexRAM split factor for subsystem; entered with the Program
Partition command
EEESIZE — allocated FlexRAM based on DEPART; entered with the Program
Partition command
Write_efficiency —
0.25 for 8-bit writes to FlexRAM
0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycee — EEPROM-backup cycling endurance
16/32-bit
8-bit
Ratio of EEPROM Backup to FlexRAM
Average Writes per FlexRAM Location
Figure 11. EEPROM backup writes to FlexRAM
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 35
NXP Semiconductors
3.4.2 EzPort switching specifications
Table 27. EzPort switching specifications
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
EP1 EZP_CK frequency of operation (all commands except
READ)
— fSYS/2 MHz
EP1a EZP_CK frequency of operation (READ command) fSYS/8 MHz
EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns
EP3 EZP_CS input valid to EZP_CK high (setup) 5 ns
EP4 EZP_CK high to EZP_CS input invalid (hold) 5 ns
EP5 EZP_D input valid to EZP_CK high (setup) 2 ns
EP6 EZP_CK high to EZP_D input invalid (hold) 5 ns
EP7 EZP_CK low to EZP_Q output valid 18 ns
EP8 EZP_CK low to EZP_Q output invalid (hold) 0 ns
EP9 EZP_CS negation to EZP_Q tri-state 12 ns
EP2
EP3 EP4
EP5 EP6
EP7 EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 12. EzPort Timing Diagram
Peripheral operating requirements and behaviors
36 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
3.4.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 28. Flexbus limited voltage range switching specifications
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation FB_CLK MHz
FB1 Clock period 20 ns
FB2 Address, data, and control output valid 11.5 ns 1
FB3 Address, data, and control output hold 0.5 ns 1
FB4 Data and FB_TA input setup 8.5 ns 2
FB5 Data and FB_TA input hold 0.5 ns 2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 29. Flexbus full voltage range switching specifications
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V
Frequency of operation FB_CLK MHz
FB1 Clock period 1/FB_CLK ns
FB2 Address, data, and control output valid 13.5 ns 1
FB3 Address, data, and control output hold 0 ns 1
FB4 Data and FB_TA input setup 15.5 ns 2
FB5 Data and FB_TA input hold 0.5 ns 2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 37
NXP Semiconductors
Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB3
FB5
FB4
FB4
FB5
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
FB_TSIZ[1:0]
FB2
Read Timing Parameters
electricals_read.svg
S0 S1 S2 S3 S0
S0 S1 S2 S3 S0
Figure 13. FlexBus read timing diagram
Peripheral operating requirements and behaviors
38 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB1
FB3
FB4
FB5
FB2
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
FB_TSIZ[1:0]
Write Timing Parameters
electricals_write.svg
Figure 14. FlexBus write timing diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 39
NXP Semiconductors
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 30 and Table 31 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1 16-bit ADC operating conditions
Table 30. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage VREFL — VREFH V
CADIN Input
capacitance
16-bit mode
8-bit / 10-bit / 12-bit
modes
8
4
10
5
pF
RADIN Input series
resistance
2 5 kΩ
RAS Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
5
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 18.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
818.330
ksps
5
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037
461.467
ksps
5
Peripheral operating requirements and behaviors
40 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 15. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 1.7 mA 3
fADACK
ADC asynchronous
clock source
ADLPC = 1, ADHSC = 0
ADLPC = 1, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 41
NXP Semiconductors
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
TUE Total unadjusted
error
12-bit modes
<12-bit modes
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
12-bit modes
<12-bit modes
±0.7
±0.2
–1.1 to
+1.9
–0.3 to
0.5
LSB45
INL Integral non-linearity 12-bit modes
<12-bit modes
±1.0
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error 12-bit modes
<12-bit modes
–4
–1.4
–5.4
–1.8
LSB4VADIN = VDDA5
EQQuantization error 16-bit modes
≤13-bit modes
–1 to 0
±0.5
LSB4
ENOB Effective number of
bits
16-bit differential mode
Avg = 32
Avg = 4
16-bit single-ended mode
Avg = 32
Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
bits
bits
bits
bits
6
SINAD Signal-to-noise plus
distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
Avg = 32
16-bit single-ended mode
Avg = 32
-94
-85
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
Avg = 32
16-bit single-ended mode
Avg = 32
82
78
95
90
dB
dB
7
EIL Input leakage error IIn × RAS mV IIn = leakage
current
(refer to the
MCU's
voltage and
Table continues on the next page...
Peripheral operating requirements and behaviors
42 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Table 31. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 8
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV 8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
12.30
12.00
1 2 3 4 5 6 7 8 9 10 1211
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
Figure 16. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 43
NXP Semiconductors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
14.00
13.75
13.25
13.00
12.75
12.50
12.00
11.75
11.50
11.25
11.00
1 2 3 4 5 6 7 8 9 10 1211
Averaging of 4 samples
Averaging of 32 samples
13.50
12.25
Figure 17. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) 20 μA
VAIN Analog input voltage VSS – 0.3 VDD V
VAIO Analog input offset voltage 20 mV
VHAnalog comparator hysteresis1
CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11
5
10
20
30
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 V
VCMPOl Output low 0.5 V
tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) 7 μA
INL 6-bit DAC integral non-linearity –0.5 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 0.3 LSB
Peripheral operating requirements and behaviors
44 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
00
01
10
HYSTCTR
Setting
0.1
10
11
Vin level (V)
CMP Hystereris (V)
3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.05
0
0.01
0.02
0.03
0.08
0.07
0.06
0.04
Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 45
NXP Semiconductors
00
01
10
HYSTCTR
Setting
10
11
0.1 3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.1
0
0.02
0.04
0.06
0.18
0.14
0.12
0.08
0.16
Vin level (V)
CMP Hysteresis (V)
Figure 19. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 33. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance 100 pF 2
ILOutput load current 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Peripheral operating requirements and behaviors
46 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
3.6.3.2 12-bit DAC operating behaviors
Table 34. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode 150 μA
IDDA_DACH
P
Supply current — high-speed mode 700 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
— 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— ±1 LSB 4
VOFFSET Offset error ±0.4 ±0.8 %FSR 5
EGGain error ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 90 dB
TCO Temperature coefficient offset voltage 3.7 μV/C 6
TGE Temperature coefficient gain error 0.000421 %FSR/C
ACOffset aging coefficient 100 μV/yr
Rop Output resistance (load = 3 kΩ) 250 Ω
SR Slew rate -80hF7Fh80h
High power (SPHP)
Low power (SPLP)
1.2
0.05
1.7
0.12
V/μs
CT Channel to channel cross talk -80 dB
BW 3dB bandwidth
High power (SPHP)
Low power (SPLP)
550
40
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 47
NXP Semiconductors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 20. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
48 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 21. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 35. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
TATemperature Operating temperature
range of the device
°C —
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 49
NXP Semiconductors
Table 36. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature= 25 °C
1.192 1.195 1.198 V 1
Vout Voltage reference output with user trim at
nominal VDDA and temperature= 25 °C
1.1945 1.195 1.1955 V 1
Vstep Voltage reference trim step 0.5 mV 1
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range)
2 15 mV 1
Ibg Bandgap only current 60 80 µA 1
Ilp Low-power buffer current 180 360 uA 1
Ihp High-power buffer current 480 960 mA 1
ΔVLOAD Load regulation
current = ± 1.0 mA
200
µV 1, 2
Tstup Buffer startup time 100 µs
Tchop_osc_st
up
Internal bandgap start-up delay with chop
oscillator enabled
35 ms
Vvdrift Voltage drift (Vmax -Vmin across the full voltage
range)
0.5 2 mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 37. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 50 °C
Table 38. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vout Voltage reference output with factory trim 1.173 1.225 V
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Peripheral operating requirements and behaviors
50 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
3.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
3.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range
of transceiver devices.
Table 39. MII signal switching specifications
Symbol Description Min. Max. Unit
RXCLK frequency 25 MHz
MII1 RXCLK pulse width high 35% 65% RXCLK
period
MII2 RXCLK pulse width low 35% 65% RXCLK
period
MII3 RXD[3:0], RXDV, RXER to RXCLK setup 5 ns
MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 ns
TXCLK frequency 25 MHz
MII5 TXCLK pulse width high 35% 65% TXCLK
period
MII6 TXCLK pulse width low 35% 65% TXCLK
period
MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 ns
MII8 TXCLK to TXD[3:0], TXEN, TXER valid 25 ns
MII7MII8
Valid data
Valid data
Valid data
MII6 MII5
TXCLK (input)
TXD[n:0]
TXEN
TXER
Figure 22. RMII/MII transmit signal timing diagram
Peripheral operating requirements and behaviors
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NXP Semiconductors
MII2 MII1
MII4MII3
Valid data
Valid data
Valid data
RXCLK (input)
RXD[n:0]
RXDV
RXER
Figure 23. RMII/MII receive signal timing diagram
3.8.1.2 RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range
of transceiver devices.
Table 40. RMII signal switching specifications
Num Description Min. Max. Unit
EXTAL frequency (RMII input clock RMII_CLK) 50 MHz
RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK
period
RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK
period
RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 ns
RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 ns
RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 ns
RMII8 RMII_CLK to TXD[1:0], TXEN valid 15 ns
3.8.1.3 MDIO serial management timing specifications
Table 41. MDIO serial management channel signal timing
Num Characteristic Symbol Min Max Unit
E10 MDC cycle time tMDC 400 — ns
E11 MDC pulse width 40 60 % tMDC
E12 MDC to MDIO output valid 375 ns
E13 MDC to MDIO output invalid 25 ns
E14 MDIO input to MDC setup 10 ns
E15 MDIO input to MDC hold 0 ns
Peripheral operating requirements and behaviors
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NXP Semiconductors
E11
E10
E11
E12
Valid Data
E13
E14 E15
Valid Data
MDC (Output)
MDIO (Output)
MDIO (Input)
Figure 24. MDIO serial management channel timing diagram
3.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-
date standards, visit usb.org.
NOTE
The MCGPLLCLK meets the USB jitter and signaling rate
specifications for certification with the use of an external
clock/crystal for both Device and Host modes.
The MCGFLLCLK does not meet the USB jitter or
signaling rate specifications for certification.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the
USB clock recovery mode is enabled. It does not meet the
USB signaling rate specifications for certification in Host
mode operation.
3.8.3 USB DCD electrical specifications
Table 42. USB0 DCD electrical specifications
Symbol Description Min. Typ. Max. Unit
VDP_SRC USB_DP source voltage (up to 250 μA) 0.5 0.7 V
VLGC Threshold voltage for logic high 0.8 2.0 V
Table continues on the next page...
Peripheral operating requirements and behaviors
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NXP Semiconductors
Table 42. USB0 DCD electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
IDP_SRC USB_DP source current 7 10 13 μA
IDM_SINK USB_DM sink current 50 100 150 μA
RDM_DWN D- pulldown resistance for data pin contact detect 14.25 24.8
VDAT_REF Data detect voltage 0.25 0.33 0.4 V
3.8.4 USB VREG electrical specifications
Table 43. USB VREG electrical specifications
Symbol Description Min. Typ.1Max. Unit Notes
VREGIN Input supply voltage 2.7 5.5 V
IDDon Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
125 186 μA
IDDstby Quiescent current — Standby mode, load
current equal zero
1.1 10 μA
IDDoff Quiescent current — Shutdown mode
VREGIN = 5.0 V and temperature=25 °C
Across operating voltage and temperature
650
4
nA
μA
ILOADrun Maximum load current — Run mode 120 mA
ILOADstby Maximum load current — Standby mode 1 mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
Run mode
Standby mode
3
2.1
3.3
2.8
3.6
3.6
V
V
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1 — 3.6 V 2
COUT External output capacitor 1.76 2.2 8.16 μF
ESR External output capacitor equivalent series
resistance
1 100 mΩ
ILIM Short circuit current 290 mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.8.5 CAN switching specifications
See General switching specifications.
Peripheral operating requirements and behaviors
54 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
3.8.6 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 44. Master mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation 30 MHz
DS1 DSPI_SCK output cycle time 2 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
2
— ns 1
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
2
— ns 2
DS5 DSPI_SCK to DSPI_SOUT valid 8.5 ns
DS6 DSPI_SCK to DSPI_SOUT invalid −2 ns
DS7 DSPI_SIN to DSPI_SCK input setup 15 ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 25. DSPI classic SPI timing — master mode
Peripheral operating requirements and behaviors
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NXP Semiconductors
Table 45. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
Frequency of operation 151MHz
DS9 DSPI_SCK input cycle time 4 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid 10 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 ns
DS13 DSPI_SIN to DSPI_SCK input setup 2 ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 ns
DS15 DSPI_SS active to DSPI_SOUT driven 14 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven 14 ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 26. DSPI classic SPI timing — slave mode
Peripheral operating requirements and behaviors
56 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
3.8.7 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 46. Master mode DSPI timing (full voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V 1
Frequency of operation 15 MHz
DS1 DSPI_SCK output cycle time 4 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid 10 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 ns
DS7 DSPI_SIN to DSPI_SCK input setup 21 ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 27. DSPI classic SPI timing — master mode
Table 47. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Table continues on the next page...
Peripheral operating requirements and behaviors
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Table 47. Slave mode DSPI timing (full voltage range) (continued)
Num Description Min. Max. Unit
Frequency of operation 7.5 MHz
DS9 DSPI_SCK input cycle time 8 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid 23.5 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 ns
DS13 DSPI_SIN to DSPI_SCK input setup 4 ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 ns
DS15 DSPI_SS active to DSPI_SOUT driven 21 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven 19 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 28. DSPI classic SPI timing — slave mode
3.8.8 Inter-Integrated Circuit Interface (I2C) timing
Table 48. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 4001kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 0.6 µs
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 0.6 µs
Data hold time for I2C bus devices tHD; DAT 023.453040.92µs
Table continues on the next page...
Peripheral operating requirements and behaviors
58 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
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Table 48. I 2C timing (continued)
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
Data set-up time tSU; DAT 2505— 1003, 6— ns
Rise time of SDA and SCL signals tr 1000 20 +0.1Cb7300 ns
Fall time of SDA and SCL signals tf 300 20 +0.1Cb6300 ns
Set-up time for STOP condition tSU; STO 4 0.6 µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
Table 49. I 2C 1 Mbps timing
Characteristic Symbol Minimum Maximum Unit
SCL Clock Frequency fSCL 0 11MHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA 0.26 µs
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 µs
Data hold time for I2C bus devices tHD; DAT 0 µs
Data set-up time tSU; DAT 50 ns
Rise time of SDA and SCL signals tr20 +0.1Cb, 2120 ns
Fall time of SDA and SCL signals tf20 +0.1Cb2120 ns
Set-up time for STOP condition tSU; STO 0.26 µs
Bus free time between STOP and START
condition
tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by
the input filter
tSP 0 50 ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins
across the full voltage range.
Peripheral operating requirements and behaviors
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NXP Semiconductors
2. Cb = total capacitance of the one bus line in pF.
SDA
HD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
SCL
Figure 29. Timing definition for devices on the I2C bus
3.8.9 UART switching specifications
See General switching specifications.
3.8.10 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 50. SDHC switching specifications
Num Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Card input clock
SD1 fpp Clock frequency (low speed) 0 400 kHz
fpp Clock frequency (SD\SDIO full speed\high speed) 0 25\50 MHz
fpp Clock frequency (MMC full speed\high speed) 0 20\50 MHz
fOD Clock frequency (identification mode) 0 400 kHz
SD2 tWL Clock low time 7 ns
SD3 tWH Clock high time 7 ns
SD4 tTLH Clock rise time 3 ns
SD5 tTHL Clock fall time 3 ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6 tOD SDHC output delay (output valid) -5 8.3 ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7 tISU SDHC input setup time 5.5 ns
SD8 tIH SDHC input hold time 0 ns
Peripheral operating requirements and behaviors
60 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
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SD2SD3 SD1
SD6
SD8
SD7
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 30. SDHC timing
3.8.11 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] =
0, RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or
the frame sync (I2S_FS) shown in the figures below.
Table 51. I2S master mode timing
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
S1 I2S_MCLK cycle time 40 ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_BCLK cycle time 80 ns
S4 I2S_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_BCLK to I2S_FS output valid 15 ns
S6 I2S_BCLK to I2S_FS output invalid 0 ns
S7 I2S_BCLK to I2S_TXD valid 15 ns
S8 I2S_BCLK to I2S_TXD invalid 0 ns
S9 I2S_RXD/I2S_FS input setup before I2S_BCLK 17 ns
S10 I2S_RXD/I2S_FS input hold after I2S_BCLK 0 ns
Peripheral operating requirements and behaviors
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S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Figure 31. I2S timing — master mode
Table 52. I2S slave mode timing
Num Description Min. Max. Unit
Operating voltage 2.7 3.6 V
S11 I2S_BCLK cycle time (input) 80 ns
S12 I2S_BCLK pulse width high/low (input) 45% 55% MCLK period
S13 I2S_FS input setup before I2S_BCLK 5 ns
S14 I2S_FS input hold after I2S_BCLK 2 ns
S15 I2S_BCLK to I2S_TXD/I2S_FS output valid 19.5 ns
S16 I2S_BCLK to I2S_TXD/I2S_FS output invalid 0 ns
S17 I2S_RXD setup before I2S_BCLK 5 ns
S18 I2S_RXD hold after I2S_BCLK 2 ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid121 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
62 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
S19
Figure 32. I2S timing — slave modes
3.8.11.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 53. I2S/SAI master mode timing
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 40 ns
S2 I2S_MCLK (as an input) pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
15 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1 — ns
S7 I2S_TX_BCLK to I2S_TXD valid 15 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
22.5 — ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 63
NXP Semiconductors
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 33. I2S/SAI timing — master modes
Table 54. I2S/SAI slave mode timing
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
7 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid 25.5 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 3 ns
S17 I2S_RXD setup before I2S_RX_BCLK 5.8 ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1 25 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
64 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 34. I2S/SAI timing — slave modes
3.8.11.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 55. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 62.5 ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
45 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid 45 ns
S8 I2S_TX_BCLK to I2S_TXD invalid ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45 — ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
Peripheral operating requirements and behaviors
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 65
NXP Semiconductors
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 35. I2S/SAI timing — master modes
Table 56. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
11 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 ns
S17 I2S_RXD setup before I2S_RX_BCLK 30 ns
S18 I2S_RXD hold after I2S_RX_BCLK 11 ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Peripheral operating requirements and behaviors
66 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 36. I2S/SAI timing — slave modes
4Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
100-pin LQFP 98ASS23308W
121-pin XFBGA 98ASA00595D
144-pin LQFP 98ASS23177W
144-pin MAPBGA 98ASA00222D
5 Pinout
Dimensions
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 67
NXP Semiconductors
5.1 K64 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
— L5 — TAMPER0/
RTC_
WAKEUP_
B
TAMPER0/
RTC_
WAKEUP_
B
A1 100 PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_
FLT1
SPI1_SIN
A10 — PTD8
/
x_LL
WU_
P24
I2C0_SCL UART5_
RX
FB_A16 x_LLWU_
P24
A9 PTD9 I2C0_SDA UART5_TX FB_A17
B1 — PTD1
0
UART5_
RTS_b
FB_A18
C2 — PTD1
1/
x_LL
WU_
P25
SPI2_
PCS0
UART5_
CTS_b
SDHC0_
CLKIN
FB_A19 x_LLWU_
P25
C1 — PTD1
2
SPI2_SCK FTM3_
FLT0
SDHC0_
D4
FB_A20
D2 — PTD1
3
SPI2_
SOUT
SDHC0_
D5
FB_A21
D1 — PTD1
4
SPI2_SIN SDHC0_
D6
FB_A22
E1 — PTD1
5
SPI2_
PCS1
SDHC0_
D7
FB_A23
A11 — NC
— NC
— NC
K3 — NC
H4 — NC
1 D3 1 ADC1_
SE4a
ADC1_
SE4a
PTE0 SPI1_
PCS1
UART1_TX SDHC0_
D1
TRACE_
CLKOUT
I2C1_SDA RTC_
CLKOUT
2 D2 2 ADC1_
SE5a
ADC1_
SE5a
PTE1/
LLWU_P0
SPI1_
SOUT
UART1_
RX
SDHC0_
D0
TRACE_
D3
I2C1_SCL SPI1_SIN LLWU_P0
3 D1 3 ADC0_
DP2/
ADC1_
SE6a
ADC0_
DP2/
ADC1_
SE6a
PTE2/
LLWU_P1
SPI1_SCK UART1_
CTS_b
SDHC0_
DCLK
TRACE_
D2
LLWU_P1
Pinout
68 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
4 E4 4 ADC0_
DM2/
ADC1_
SE7a
ADC0_
DM2/
ADC1_
SE7a
PTE3 SPI1_SIN UART1_
RTS_b
SDHC0_
CMD
TRACE_
D1
SPI1_
SOUT
5 E5 — VDD VDD
6 F6 — VSS VSS
7 E3 5 DISABLED PTE4/
LLWU_P2
SPI1_
PCS0
UART3_TX SDHC0_
D3
TRACE_
D0
LLWU_P2
8 E2 6 DISABLED PTE5 SPI1_
PCS2
UART3_
RX
SDHC0_
D2
FTM3_CH0
9 E1 7 DISABLED PTE6/
x_LLWU_
P16
SPI1_
PCS3
UART3_
CTS_b
I2S0_
MCLK
FTM3_CH1 USB_
SOF_OUT
x_LLWU_
P16
10 F4 — DISABLED PTE7 UART3_
RTS_b
I2S0_
RXD0
FTM3_CH2
11 F3 — DISABLED PTE8 I2S0_
RXD1
UART5_TX I2S0_RX_
FS
FTM3_CH3
12 F2 — DISABLED PTE9/
x_LLWU_
P17
I2S0_TXD1 UART5_
RX
I2S0_RX_
BCLK
FTM3_CH4 x_LLWU_
P17
13 F1 — DISABLED PTE10/
x_LLWU_
P18
UART5_
CTS_b
I2S0_TXD0 FTM3_CH5 x_LLWU_
P18
14 G4 — DISABLED PTE11 UART5_
RTS_b
I2S0_TX_
FS
FTM3_CH6
15 G3 — DISABLED PTE12 I2S0_TX_
BCLK
FTM3_CH7
16 E6 8 VDD VDD
17 F7 9 VSS VSS
18 H3 — VSS VSS
19 H1 10 USB0_DP USB0_DP
20 H2 11 USB0_DM USB0_DM
21 G1 12 VOUT33 VOUT33
22 G2 13 VREGIN VREGIN
23 J1 14 ADC0_DP1 ADC0_DP1
24 J2 15 ADC0_
DM1
ADC0_
DM1
25 K1 16 ADC1_DP1 ADC1_DP1
26 K2 17 ADC1_
DM1
ADC1_
DM1
27 L1 18 ADC0_
DP0/
ADC1_DP3
ADC0_
DP0/
ADC1_DP3
Pinout
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 69
NXP Semiconductors
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
28 L2 19 ADC0_
DM0/
ADC1_
DM3
ADC0_
DM0/
ADC1_
DM3
29 M1 20 ADC1_
DP0/
ADC0_DP3
ADC1_
DP0/
ADC0_DP3
30 M2 21 ADC1_
DM0/
ADC0_
DM3
ADC1_
DM0/
ADC0_
DM3
31 H5 22 VDDA VDDA
32 G5 23 VREFH VREFH
33 G6 24 VREFL VREFL
34 H6 25 VSSA VSSA
35 K3 — ADC1_
SE16/
CMP2_IN2/
ADC0_
SE22
ADC1_
SE16/
CMP2_IN2/
ADC0_
SE22
36 J3 — ADC0_
SE16/
CMP1_IN2/
ADC0_
SE21
ADC0_
SE16/
CMP1_IN2/
ADC0_
SE21
37 M3 26 VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
38 L3 27 DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
39 L4 — DAC1_
OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_
SE23
DAC1_
OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_
SE23
40 M7 28 XTAL32 XTAL32
41 M6 29 EXTAL32 EXTAL32
42 L6 30 VBAT VBAT
43 — VDD VDD
44 — VSS VSS
Pinout
70 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
45 M4 31 ADC0_
SE17
ADC0_
SE17
PTE24 UART4_TX I2C0_SCL EWM_
OUT_b
46 K5 32 ADC0_
SE18
ADC0_
SE18
PTE25/
x_LLWU_
P21
UART4_
RX
I2C0_SDA EWM_IN x_LLWU_
P21
47 K4 33 DISABLED PTE26 ENET_
1588_
CLKIN
UART4_
CTS_b
RTC_
CLKOUT
USB_
CLKIN
48 J4 — DISABLED PTE27 UART4_
RTS_b
49 H4 — DISABLED PTE28
50 J5 34 JTAG_
TCLK/
SWD_CLK/
EZP_CLK
PTA0 UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5 JTAG_
TCLK/
SWD_CLK
EZP_CLK
51 J6 35 JTAG_TDI/
EZP_DI
PTA1 UART0_
RX
FTM0_CH6 JTAG_TDI EZP_DI
52 K6 36 JTAG_
TDO/
TRACE_
SWO/
EZP_DO
PTA2 UART0_TX FTM0_CH7 JTAG_
TDO/
TRACE_
SWO
EZP_DO
53 K7 37 JTAG_
TMS/
SWD_DIO
PTA3 UART0_
RTS_b
FTM0_CH0 JTAG_
TMS/
SWD_DIO
54 L7 38 NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1 NMI_b LLWU_P3 EZP_CS_b
55 M8 39 DISABLED PTA5 USB_
CLKIN
FTM0_CH2 RMII0_
RXER/
MII0_
RXER
CMP2_
OUT
I2S0_TX_
BCLK
JTAG_
TRST_b
56 E7 40 VDD VDD
57 G7 41 VSS VSS
58 J7 — DISABLED PTA6 FTM0_CH3 CLKOUT TRACE_
CLKOUT
59 J8 — ADC0_
SE10
ADC0_
SE10
PTA7 FTM0_CH4 TRACE_
D3
60 K8 — ADC0_
SE11
ADC0_
SE11
PTA8 FTM1_CH0 FTM1_
QD_PHA
TRACE_
D2
61 L8 DISABLED PTA9 FTM1_CH1 MII0_RXD3 FTM1_
QD_PHB
TRACE_
D1
62 M9 — DISABLED PTA10/
x_LLWU_
P22
FTM2_CH0 MII0_RXD2 FTM2_
QD_PHA
TRACE_
D0
x_LLWU_
P22
63 L9 — DISABLED PTA11/
x_LLWU_
P23
FTM2_CH1 MII0_
RXCLK
I2C2_SDA FTM2_
QD_PHB
x_LLWU_
P23
Pinout
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 71
NXP Semiconductors
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
64 K9 42 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 RMII0_
RXD1/
MII0_RXD1
I2C2_SCL I2S0_TXD0 FTM1_
QD_PHA
65 J9 43 CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 RMII0_
RXD0/
MII0_RXD0
I2C2_SDA I2S0_TX_
FS
FTM1_
QD_PHB
LLWU_P4
66 L10 44 DISABLED PTA14 SPI0_
PCS0
UART0_TX RMII0_
CRS_DV/
MII0_
RXDV
I2C2_SCL I2S0_RX_
BCLK
I2S0_TXD1
67 L11 45 DISABLED PTA15 SPI0_SCK UART0_
RX
RMII0_
TXEN/
MII0_TXEN
I2S0_
RXD0
68 K10 46 DISABLED PTA16 SPI0_
SOUT
UART0_
CTS_b/
UART0_
COL_b
RMII0_
TXD0/
MII0_TXD0
I2S0_RX_
FS
I2S0_
RXD1
69 K11 47 ADC1_
SE17
ADC1_
SE17
PTA17 SPI0_SIN UART0_
RTS_b
RMII0_
TXD1/
MII0_TXD1
I2S0_
MCLK
70 E8 48 VDD VDD
71 G8 49 VSS VSS
72 M12 50 EXTAL0 EXTAL0 PTA18 FTM0_
FLT2
FTM_
CLKIN0
EXTAL0
73 M11 51 XTAL0 XTAL0 PTA19 FTM1_
FLT0
FTM_
CLKIN1
LPTMR0_
ALT1
LPTMR0_
ALT1
74 L12 52 RESET_b RESET_b RESET_b
75 K12 — DISABLED PTA24 MII0_TXD2 FB_A29
76 J12 — DISABLED PTA25 MII0_
TXCLK
FB_A28
77 J11 — DISABLED PTA26 MII0_TXD3 FB_A27
78 J10 — DISABLED PTA27 MII0_CRS FB_A26
79 H12 — DISABLED PTA28 MII0_TXER FB_A25
80 H11 — DISABLED PTA29 MII0_COL FB_A24
81 H10 53 ADC0_
SE8/
ADC1_SE8
ADC0_
SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 RMII0_
MDIO/
MII0_MDIO
FTM1_
QD_PHA
LLWU_P5
82 H9 54 ADC0_
SE9/
ADC1_SE9
ADC0_
SE9/
ADC1_SE9
PTB1 I2C0_SDA FTM1_CH1 RMII0_
MDC/
MII0_MDC
FTM1_
QD_PHB
83 G12 55 ADC0_
SE12
ADC0_
SE12
PTB2 I2C0_SCL UART0_
RTS_b
ENET0_
1588_
TMR0
FTM0_
FLT3
84 G11 56 ADC0_
SE13
ADC0_
SE13
PTB3 I2C0_SDA UART0_
CTS_b/
ENET0_
1588_
TMR1
FTM0_
FLT0
Pinout
72 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
UART0_
COL_b
85 G10 — ADC1_
SE10
ADC1_
SE10
PTB4 ENET0_
1588_
TMR2
FTM1_
FLT0
86 G9 — ADC1_
SE11
ADC1_
SE11
PTB5 ENET0_
1588_
TMR3
FTM2_
FLT0
87 F12 — ADC1_
SE12
ADC1_
SE12
PTB6 FB_AD23
88 F11 — ADC1_
SE13
ADC1_
SE13
PTB7 FB_AD22
89 F10 — DISABLED PTB8 UART3_
RTS_b
FB_AD21
90 F9 57 DISABLED PTB9 SPI1_
PCS1
UART3_
CTS_b
FB_AD20
91 E12 58 ADC1_
SE14
ADC1_
SE14
PTB10 SPI1_
PCS0
UART3_
RX
FB_AD19 FTM0_
FLT1
92 E11 59 ADC1_
SE15
ADC1_
SE15
PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_
FLT2
93 H7 60 VSS VSS
94 F5 61 VDD VDD
95 E10 62 DISABLED PTB16 SPI1_
SOUT
UART0_
RX
FTM_
CLKIN0
FB_AD17 EWM_IN
96 E9 63 DISABLED PTB17 SPI1_SIN UART0_TX FTM_
CLKIN1
FB_AD16 EWM_
OUT_b
97 D12 64 DISABLED PTB18 CAN0_TX FTM2_CH0 I2S0_TX_
BCLK
FB_AD15 FTM2_
QD_PHA
98 D11 65 DISABLED PTB19 CAN0_RX FTM2_CH1 I2S0_TX_
FS
FB_OE_b FTM2_
QD_PHB
99 D10 66 DISABLED PTB20 SPI2_
PCS0
FB_AD31 CMP0_
OUT
100 D9 67 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_
OUT
101 C12 68 DISABLED PTB22 SPI2_
SOUT
FB_AD29 CMP2_
OUT
102 C11 69 DISABLED PTB23 SPI2_SIN SPI0_
PCS5
FB_AD28
103 B12 70 ADC0_
SE14
ADC0_
SE14
PTC0 SPI0_
PCS4
PDB0_
EXTRG
USB_
SOF_OUT
FB_AD14 I2S0_TXD1
104 B11 71 ADC0_
SE15
ADC0_
SE15
PTC1/
LLWU_P6
SPI0_
PCS3
UART1_
RTS_b
FTM0_CH0 FB_AD13 I2S0_TXD0 LLWU_P6
105 A12 72 ADC0_
SE4b/
CMP1_IN0
ADC0_
SE4b/
CMP1_IN0
PTC2 SPI0_
PCS2
UART1_
CTS_b
FTM0_CH1 FB_AD12 I2S0_TX_
FS
Pinout
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 73
NXP Semiconductors
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
106 A11 73 CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_
PCS1
UART1_
RX
FTM0_CH2 CLKOUT/
CLKOUT
I2S0_TX_
BCLK
LLWU_P7
107 H8 74 VSS VSS
108 75 VDD VDD
109 A9 76 DISABLED PTC4/
LLWU_P8
SPI0_
PCS0
UART1_TX FTM0_CH3 FB_AD11 CMP1_
OUT
LLWU_P8
110 D8 77 DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_
RXD0
FB_AD10 CMP0_
OUT
FTM0_CH2 LLWU_P9/
LPTMR0_
ALT2
111 C8 78 CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_
SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9 I2S0_
MCLK
LLWU_P10
112 B8 79 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_
SOF_OUT
I2S0_RX_
FS
FB_AD8
113 A8 80 ADC1_
SE4b/
CMP0_IN2
ADC1_
SE4b/
CMP0_IN2
PTC8 FTM3_CH4 I2S0_
MCLK
FB_AD7
114 D7 81 ADC1_
SE5b/
CMP0_IN3
ADC1_
SE5b/
CMP0_IN3
PTC9 FTM3_CH5 I2S0_RX_
BCLK
FB_AD6 FTM2_
FLT0
115 C7 82 ADC1_
SE6b
ADC1_
SE6b
PTC10 I2C1_SCL FTM3_CH6 I2S0_RX_
FS
FB_AD5
116 B7 83 ADC1_
SE7b
ADC1_
SE7b
PTC11/
LLWU_P11
I2C1_SDA FTM3_CH7 I2S0_
RXD1
FB_RW_b LLWU_P11
117 A7 84 DISABLED PTC12 UART4_
RTS_b
FB_AD27 FTM3_
FLT0
118 D6 85 DISABLED PTC13 UART4_
CTS_b
FB_AD26
119 C6 86 DISABLED PTC14 UART4_
RX
FB_AD25
120 B6 87 DISABLED PTC15 UART4_TX FB_AD24
121 88 VSS VSS
122 89 VDD VDD
123 A6 90 DISABLED PTC16 UART3_
RX
ENET0_
1588_
TMR0
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_
BLS15_8_
b
124 D5 91 DISABLED PTC17 UART3_TX ENET0_
1588_
TMR1
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_
0_b
125 C5 92 DISABLED PTC18 UART3_
RTS_b
ENET0_
1588_
TMR2
FB_TBST_
b/
FB_CS2_b/
FB_BE15_
Pinout
74 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
144
QFP
144
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9
8_BLS23_
16_b
126 B5 — DISABLED PTC19 UART3_
CTS_b
ENET0_
1588_
TMR3
FB_CS3_b/
FB_BE7_
0_BLS31_
24_b
FB_TA_b
127 A5 93 DISABLED PTD0/
LLWU_P12
SPI0_
PCS0
UART2_
RTS_b
FTM3_CH0 FB_ALE/
FB_CS1_b/
FB_TS_b
LLWU_P12
128 D4 94 ADC0_
SE5b
ADC0_
SE5b
PTD1 SPI0_SCK UART2_
CTS_b
FTM3_CH1 FB_CS0_b
129 C4 95 DISABLED PTD2/
LLWU_P13
SPI0_
SOUT
UART2_
RX
FTM3_CH2 FB_AD4 I2C0_SCL LLWU_P13
130 B4 96 DISABLED PTD3 SPI0_SIN UART2_TX FTM3_CH3 FB_AD3 I2C0_SDA
131 A4 97 DISABLED PTD4/
LLWU_P14
SPI0_
PCS1
UART0_
RTS_b
FTM0_CH4 FB_AD2 EWM_IN SPI1_
PCS0
LLWU_P14
132 A3 98 ADC0_
SE6b
ADC0_
SE6b
PTD5 SPI0_
PCS2
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5 FB_AD1 EWM_
OUT_b
SPI1_SCK
133 A2 99 ADC0_
SE7b
ADC0_
SE7b
PTD6/
LLWU_P15
SPI0_
PCS3
UART0_
RX
FTM0_CH6 FB_AD0 FTM0_
FLT0
SPI1_
SOUT
LLWU_P15
134 M10 — VSS VSS
135 F8 — VDD VDD
5.2 Unused analog interfaces
Table 57. Unused analog interfaces
Module name Pins Recommendation if unused
ADC ADC0_DP1, ADC0_DM1, ADC1_DP1,
ADC1_DM1, ADC0_DP0/ADC1_DP3,
ADC0_DM0/ADC1_DM3, ADC1_DP0/
ADC0_DP3, ADC1_DM0/ADC0_DM3,
ADC1_SE16/ADC0_SE22,
ADC0_SE16/ADC0_SE21,
ADC1_SE18
Ground
DAC 1DAC0_OUT, DAC1_OUT Float
USB VREGIN, USB0_GND, VOUT332Connect VREGIN and VOUT33
together and tie to ground through a 10
kΩ resistor. Do not tie directly to
ground, as this causes a latch-up risk.
USB0_DM, USB0_DP Float
1. Unused DAC signals do not apply to all parts. See the Pinout section for details.
2. USB0_VBUS and USB0_GND are board level signals
Pinout
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 75
NXP Semiconductors
5.3 K64 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
76 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
75
74
73
60
59
58
57
56
55
54
53
52
51
72
71
70
69
68
67
66
65
64
63
62
61
25
24
23
22
21
40
39
38
37
50
49
48
47
46
45
44
43
42
41
36
35
34
33
32
31
30
29
28
27
26
99
79
78
77
76
98
97
96
95
94
93
92
91
90
89
88
80
81
82
83
84
85
86
87
100
108 VDD
107
106
105
104
103
102
101
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
PTB23
PTB22
116 PTC11/LLWU_P11
115
114
113
112
111
110
109
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
124 PTC17
123
122
121
120
119
118
117
PTC16
VDD
VSS
PTC15
PTC14
PTC13
PTC12
132 PTD5
131
130
129
128
127
126
125
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC19
PTC18
140 PTD11
139
138
137
136
135
134
133
PTD10
PTD9
PTD8
PTD7
VDD
VSS
PTD6/LLWU_P15
144
143
142
141
PTD15
PTD14
PTD13
PTD12
PTB20
PTA28
PTA27
PTA26
PTA25
PTB19
PTB18
PTB17
PTB16
VDD
VSS
PTB11
PTB10
PTB9
PTB8
PTB7
PTA29
PTB0/LLWU_P5
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB21
PTA24
RESET_b
PTA19
PTA18
VSS
VDD
PTA17
PTA16
PTA15
PTA14
PTA13/LLWU_P4
PTA12
PTA11
PTA10
PTA9
PTA8
PTA7
PTA6
VSS
VDD
PTA5
PTA4/LLWU_P3
PTA3
PTA2
PTA1
PTA0
PTE28
PTE27
PTE26
PTE25
PTE24
VSS
VDD
VBAT
EXTAL32
XTAL32
DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
USB0_DM
USB0_DP
VSS
VSS
VDD
PTE12
PTE11
PTE10
PTE9
PTE8
PTE7
PTE6
PTE5
PTE4/LLWU_P2
VSS
VDD
PTE3
PTE2/LLWU_P1
PTE1/LLWU_P0
PTE0
ADC1_DP1
ADC0_DM1
ADC0_DP1
VREGIN
VOUT33
ADC0_SE16/CMP1_IN2/ADC0_SE21
ADC1_SE16/CMP2_IN2/ADC0_SE22
VSSA
VREFL
VREFH
VDDA
ADC1_DM0/ADC0_DM3
ADC1_DP0/ADC0_DP3
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
ADC1_DM1
Figure 37. 144 LQFP Pinout Diagram
Pinout
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 77
NXP Semiconductors
1 2 3456789
123456789
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
10
K
K
10
11
11
LL
12
12
M
MPTA18
PTC8 PTC4/
LLWU_P8 NC PTC3/
LLWU_P7 PTC2
PTA1 PTA6PTA0PTE27
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
PTE26 PTE25 PTA2 PTA3 PTA8
PTA7
VSSVSSVSSAVDDAPTE28VSSUSB0_DM
ADC0_DM1
ADC1_DM1
ADC0_DM0/
ADC1_DM3
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
RTC_
WAKEUP_B VBAT PTA4/
LLWU_P3 PTA9 PTA11
PTA12
PTA13/
LLWU_P4
PTB1
PTA27
PTB0/
LLWU_P5
PTB4PTB5VSSVSSVREFLVREFHPTE11PTE12VREGINVOUT33
USB0_DP
ADC0_DP1
ADC1_DP1
ADC0_DP0/
ADC1_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS
PTA16
PTA14
PTB3
PTA29
PTA26
PTA17
PTA15
PTA19
RESET_b
PTA24
PTA25
PTA28
PTB2
PTB6PTB7PTB8PTB9VDD
VDD PTB17 PTB16 PTB10PTB11
PTB19 PTB18
PTB22PTB23NC
PTB20PTB21
PTC5/
LLWU_P9
PTD8
PTC6/
LLWU_P10
PTC7 PTD9 NC PTC1/
LLWU_P6 PTC0
VSS VSS
VDDVDD
PTC13 PTC9
PTC11/
LLWU_P11
PTC10
PTC19 PTC15
PTC14PTC18
PTD2/
LLWU_P13
PTD3PTD10
PTD13
PTE0 PTD1 PTC17
VDD
VDDPTE7
PTE3
PTE4/
LLWU_P2
PTE8PTE9PTE10
PTE6 PTE5
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTD15 PTD14
PTD11PTD12
PTC12PTC16
PTD0/
LLWU_P12
PTD4/
LLWU_P14
PTD5
PTD6/
LLWU_P15
PTD7
Figure 38. 144 MAPBGA Pinout Diagram
Pinout
78 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
1
A PTD7
B PTD10
C PTD12
D PTD14
E PTD15
F USB0_DP
G VOUT33
H ADC0_DP1
J ADC1_DP1
KADC0_DP0/
ADC1_DP3
1
LADC1_DP0/
ADC0_DP3
2
PTD5
PTD6/
LLWU_P15
PTD11
PTD13
PTE2/
LLWU_P1
USB0_DM
VREGIN
ADC0_DM1
ADC1_DM1
ADC0_DM0/
ADC1_DM3
2
ADC1_DM0/
ADC0_DM3
3
PTD4/
LLWU_P14
PTD3
PTD2/
LLWU_P13
PTD1
PTE1/
LLWU_P0
PTE6
VSS
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
NC
3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
4
PTC19
PTC18
PTC17
PTD0/
LLWU_P12
PTE0
PTE3
PTE5
NC
PTA11
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
4
XTAL32
5
PTC14
PTC15
PTC11/
LLWU_P11
PTC16
VDD
VDDA
VREFH
PTE24
PTE25
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
5
EXTAL32
6
PTC13
PTC12
PTC10
PTC9
VDD
VSSA
VREFL
PTE26
PTA0
VBAT
6
VSS
7
PTC8
PTC7
PTC6/
LLWU_P10
PTC5/
LLWU_P9
VDD
VSS
VSS
PTE4/
LLWU_P2
PTA2
PTA5
7
RTC_
WAKEUP_B
8
PTC4/
LLWU_P8
PTC3/
LLWU_P7
PTC2
PTC1/
LLWU_P6
PTB23
PTB22
PTB3
PTA1
PTA4/
LLWU_P3
PTA12
8
PTA13/
LLWU_P4
9
PTD9
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTA3
PTA10
PTA14
9
PTA15
10
PTD8
PTB16
PTB11
PTB10
PTB9
PTB20
PTB1
PTA17
PTA16
VSS
10
VDD
11
ANC
BPTB12
CPTB13
DPTB8
EPTB7
FPTB6
G
PTB0/
LLWU_P5
HPTA29
JRESET_b
KPTA19
11
LPTA18
Figure 39. 121 XFBGA Pinout Diagram
Pinout
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 79
NXP Semiconductors
60
59
58
57
56
55
54
53
52
51
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ADC1_DP0/ADC0_DP3
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
ADC1_DM1
ADC1_DP1
ADC0_DM1
ADC0_DP1
VREGIN
VOUT33
USB0_DM
USB0_DP
VSS
VDD
PTE6
PTE5
PTE4/LLWU_P2
PTE3
PTE2/LLWU_P1
PTE1/LLWU_P0
PTE0 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
VSS
PTB11
PTB10
PTB9
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
25
24
23
22
21
VSSA
VREFL
VREFH
VDDA
ADC1_DM0/ADC0_DM3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
99
79
78
77
76
PTD6/LLWU_P15
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
50
49
48
47
46
45
44
43
42
41
PTA18
VSS
VDD
PTA17
PTA16
PTA15
PTA14
PTA13/LLWU_P4
PTA12
VSS
VDD
PTA5
PTA4/LLWU_P3
PTA3
PTA2
PTA1
PTA0
PTE26
PTE25
PTE24
VBAT
EXTAL32
XTAL32
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
98 PTD5
97 PTD4/LLWU_P14
96 PTD3
95 PTD2/LLWU_P13
94 PTD1
93 PTD0/LLWU_P12
92 PTC18
91 PTC17
90 PTC16
89 VDD
88 VSS
80 PTC8
PTC9
PTC10
81
82
83 PTC11/LLWU_P11
84 PTC12
85 PTC13
86 PTC14
87 PTC15
100 PTD7
Figure 40. 100 LQFP Pinout Diagram
Pinout
80 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
1
APTC4/
LLWU_P8
BPTC3/
LLWU_P7
C PTC2
D PTB23
E PTB18
F PTB16
G PTB10
H PTB7
J PTB3
K PTA29
L RESET_b
M PTA19
1
N PTA18
2
PTC7
PTC6/
LLWU_P10
PTC5/
LLWU_P9
PTC0
PTB19
PTB17
PTB11
PTB6
PTB2
PTA28
PTA24
VSS
2
VDD
3
PTC9
PTC8
PTC10
PTC1/
LLWU_P6
PTB20
VDD
PTB9
PTB5
PTB1
PTA27
PTA25
PTA17
3
PTA15
4
PTC12
PTC11/
LLWU_P11
PTC13
PTB22
PTB21
VSS
PTB8
PTB4
PTB0/
LLWU_P5
PTA26
PTA16
PTA13/
LLWU_P4
4
PTA10
5
PTC15
PTC14
PTC16
PTC19
VDD
VSS
VDD
VSS
PTA14
PTA12
PTA9
PTA7
5
PTA6
6
PTC17
PTC18
PTD2/
LLWU_P13
PTD0/
LLWU_P12
VSS
VDD
VSS
PTA11
PTA8
PTA5
PTA4/
LLWU_P3
6
PTA3
7
PTD1
PTD3
PTD4/
LLWU_P14
PTD10
PTE6
VDD
VSS
VDD
PTA2
PTA1
PTA0
PTE28
7
PTE26
8
PTD5
PTD6/
LLWU_P15
PTD11
PTE1/
LLWU_P0
PTE7
ADC0_DP1
ADC0_DM1
VDD
PTE27
PTE25
PTE24
VBAT
8
EXTAL32
9
PTD7
PTD8
PTD13
PTE2/
LLWU_P1
PTE8
PTE11
ADC0_DP0/
ADC1_DP3
ADC0_DM0/
ADC1_DM3
RTC_
WAKEUP_B
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
9
XTAL32
10
PTD9
PTD12
PTE0
PTE4/
LLWU_P2
PTE9
PTE12
VOUT33
VREGIN
ADC1_DP0/
ADC0_DP3
ADC1_DM0/
ADC0_DM3
VREFH
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
10
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
11
PTD14
PTD15
PTE3
PTE5
PTE10
VSS
USB0_DP
USB0_DM
ADC1_DP1
ADC1_DM1
VDDA
VREFL
11
VSSA
A
B
C
D
E
F
G
H
J
K
L
M
N
Figure 41. 142 CSP Pinout Diagram
6Ordering parts
Ordering parts
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 81
NXP Semiconductors
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MK64
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field Description Values
Q Qualification status M = Fully qualified, general market flow
P = Prequalification
K## Kinetis family K64 = Ethernet with high RAM density
A Key attribute D = Cortex-M4 w/ DSP
F = Cortex-M4 w/ DSP and FPU
M Flash memory type N = Program flash only
X = Program flash and FlexMemory
FFF Program flash memory size 32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
Table continues on the next page...
Part identification
82 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
Field Description Values
R Silicon revision Z = Initial
(Blank) = Main
A = Revision after main
T Temperature range (°C) V = –40 to 105
C = –40 to 85
PP Package identifier FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC Maximum CPU frequency (MHz) 5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz
N Packaging type R = Tape and reel
(Blank) = Trays
7.4 Example
This is an example part number:
MK64FN1M0VMD12
8Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
Table continues on the next page...
Terminology and guidelines
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 83
NXP Semiconductors
Term Definition
Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:
Lies within the range of values specified by the operating behavior
Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
8.2 Examples
Operating rating:
Operating requirement:
Operating behavior that includes a typical value:
EXAMPLE
EXAMPLEEXAMPLE
EXAMPLE
Terminology and guidelines
84 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD Supply voltage 3.3 V
8.4 Relationship between ratings and operating requirements
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
Terminology and guidelines
Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016 85
NXP Semiconductors
9 Revision History
The following table provides a revision history for this document.
Table 58. Revision History
Rev. No. Date Substantial Changes
2 01/2014 Initial public release.
3 04/2014 Format changes
Updated Table 23 "Flash command timing specifications."
4 09/2014 Updated Table 6 "Power consumption operating behavior."
Updated Table 17 "IRC48M specifications
Updated Table 35 "VREF full-range operating behavior"
5 12/2014 Updated Table 6 "Power consumption operating behavior."
Added a note to the section "Power consumption operating behaviors."
6 08/2015 Added a footnote to the maximum SCL clock frequency value in the table "I2C timing"
Changed the title of the table "I2C 1 MHZ timing" to "I2C 1 Mbps timing"
Added a footnote and updated the table "IRC48M specifications" for open loop total
deviation of IRC48M frequency at high voltage and low voltage.
Added a footnote on the ambient temperature entry to the section "Thermal operating
requirements."
Added a note to the section "Power consumption operating behaviors" and updated
values in the table "Power consumption operating behaviors."
Added a note to the maximum frequency value in the table "Slave mode DSPI timing
(limited voltage range)."
Redeveloped the section "Terminology and guidelines."
7 10/2016 Updated the values of IDD_STOP and IDD_VLLS0 in the table "Power consumption
operating behaviors"
Revision History
86 Kinetis K64F Sub-Family Data Sheet, Rev. 7, 10/2016
NXP Semiconductors
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/salestermsandconditions.
NXP, NXP logo, and Kinetis are trademarks of NXP B.V. All other product or
service names are the property of their respective owners. ARM and Cortex are
registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or
elsewhere. The USB-IF Logo is a registered trademark of USB Implementers
Forum, Inc. All rights reserved.
©2014–2016 NXP B.V.
Document Number K64P144M120SF5
Revision 7, 10/2016

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