JPY | USD

nRF52840 Objective Specification Datashee

Nordic Semiconductor ASA

Download PDF Datasheet

Datasheet

All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
201-07-06
nRF5240 2EMHFWLYHProduct SpecificationY1
51 Mbps  (BLE)
+8 dBm TX power (down to -20 dBm in 4 dB steps)
On-air compatible with nRF52, nRF51, nRF24L and nRF24AP Series
Supported data rates:
'endedoutput (on-chip balun)
ϰ͘9+ ,"#$-%.
ϰ͘8+ ,"/$
 /''0-".
2128822,1"((4
56:+;"((4
Watchpoint and trace debug modules (DWT, ETM and ITM)
 '"-'=<.
53 
On-chipDC/DC and LDO regulators with automated low current modes
A"ed peripheral power management
5," "
ϯ:+*?BC!/+!,/#2

C'(< and with support for concurrent multi-protocol
!%%, +<29("44 
 
# "
4x 4 "4"-6=."s48<+
Audio peripherals: I2S, d 4(-6<.
53*4"
Up to 4x SPI masters/3x '60ss48<+
Up to 2x 02 ws;s
2x 7+/#-2#';/#'.48<+
 D""-D<82.
33"s-/#2.
6,
AD5C73 ,!7E7
Advanced cŽŵƉƵƚĞƌƉĞƌŝƉŚĞƌĂůƐĂŶĚ/ͬKĚĞǀŝĐĞƐ
DŽƵƐĞ
<ĞLJďŽĂƌĚ
Dulti-touch trackpad
Health/fitness sensor and monitor devices
Wireless payment enabled devices
Interactive entertainment devices
Remote controls
Gaming controllers
Bluetooth 5: 2 Mbps, 1 Mbps, 500 kbps, 125 kbps
IEEE 802.15.4-2006: 250 kbps
Proprietary 2.4 GHz: 2 Mbps, 1 Mbps
ARM® Cortex®-M4 32-bit processor with FPU, 64 MHz
Regulated s" for external components from 8? to *3?
'" >? to 5.5 ?
%4:+*?B55͕ŶŽZDƌĞƚĞŶƚŝŽŶ
Advanced on-chip interfaces
USB 2.0 full speed (12 Mbps) controller
QSPI 32 MHz interface
High speed 32 MHz SPI
Type 2 near field communication (NFC-A) tag with wake-on field
Touch-to-pair support
Key features Applications
Programmable peripheral interconnect (PPI)
48 general purpose I/O pins
EasyDMA automated data transfer without CPU processing on peripherals
15 low-power  with wake-up from System OFF mode
Advanced wearables
Internet of things (IoT)
Smart home sensors and controllers
Industrial IoT sensors and controllers
103125 kbps BLE  (long range)
HW accelerated security
ARM® TrustZone® Cryptocell 310 cryptographic accelerator
128 bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption)
5, IEEE 802.15.4-2006, 2.4 GHz transceiver
1 MB flash/256 kB RAM
Contents
Page 2
Contents
1 Revision history...................................................................................9
2 About this document............................................................................................ 10
2.1 Document naming and status...............................................................................................10
2.2 Peripheral naming and abbreviations................................................................................... 10
2.3 Register tables...................................................................................................................... 10
2.4 Registers............................................................................................................................... 11
3 Block diagram........................................................................................................12
4 Pin assignments....................................................................................................13
4.1 QIAA pin assignments.......................................................................................................... 13
5 Absolute maximum ratings.................................................................................. 16
6 Recommended operating conditions.................................................................. 17
7 CPU......................................................................................................................... 18
7.1 Floating point interrupt.......................................................................................................... 18
7.2 Electrical specification...........................................................................................................18
7.3 CPU and support module configuration................................................................................19
8 Memory................................................................................................................... 20
8.1 RAM - Random access memory...........................................................................................20
8.2 Flash - Non-volatile memory.................................................................................................20
8.3 Memory map......................................................................................................................... 21
8.4 Instantiation........................................................................................................................... 23
9 AHB multilayer.......................................................................................................25
10 EasyDMA.............................................................................................................. 26
10.1 EasyDMA array list............................................................................................................. 27
11 NVMC Non-volatile memory controller.........................................................28
11.1 Writing to flash....................................................................................................................28
11.2 Erasing a page in flash.......................................................................................................28
11.3 Writing to user information configuration registers (UICR)................................................. 28
11.4 Erasing user information configuration registers (UICR).................................................... 28
11.5 Erase all.............................................................................................................................. 29
11.6 Cache.................................................................................................................................. 29
11.7 Registers............................................................................................................................. 29
11.8 Electrical specification.........................................................................................................32
12 FICR Factory information configuration registers.......................................33
12.1 Registers............................................................................................................................. 33
13 UICR User information configuration registers........................................... 44
13.1 Registers............................................................................................................................. 44
14 Peripheral interface.............................................................................................59
14.1 Peripheral ID....................................................................................................................... 59
14.2 Peripherals with shared ID..................................................................................................59
14.3 Peripheral registers.............................................................................................................60
14.4 Bit set and clear..................................................................................................................60
14.5 Tasks...................................................................................................................................60
14.6 Events..................................................................................................................................60
14.7 Shortcuts............................................................................................................................. 61
14.8 Interrupts............................................................................................................................. 61
15 Debug and trace.................................................................................................. 62
15.1 DAP - Debug access port...................................................................................................62
15.2 CTRL-AP - Control access port..........................................................................................63
15.3 Debug interface mode.........................................................................................................64
Contents
Page 3
15.4 Real-time debug..................................................................................................................65
15.5 Trace................................................................................................................................... 65
16 POWER Power supply....................................................................................66
16.1 Main supply.........................................................................................................................66
16.2 USB supply......................................................................................................................... 71
16.3 System OFF mode..............................................................................................................72
16.4 System ON mode............................................................................................................... 73
16.5 RAM power control............................................................................................................. 73
16.6 Reset................................................................................................................................... 73
16.7 Retained registers...............................................................................................................74
16.8 Reset behavior....................................................................................................................74
16.9 Registers............................................................................................................................. 75
16.10 Electrical specification.....................................................................................................138
17 CLOCK Clock control...................................................................................141
17.1 HFCLK clock controller..................................................................................................... 141
17.2 LFCLK clock controller......................................................................................................143
17.3 Registers........................................................................................................................... 145
17.4 Electrical specification.......................................................................................................150
18 Power and clock management.........................................................................152
18.1 Current consumption scenarios........................................................................................ 152
19 GPIO General purpose input/output........................................................... 154
19.1 Pin configuration............................................................................................................... 154
19.2 GPIO located near the RADIO......................................................................................... 156
19.3 Registers........................................................................................................................... 156
19.4 Electrical specification.......................................................................................................197
20 GPIOTE GPIO tasks and events..................................................................200
20.1 Pin events and tasks........................................................................................................ 200
20.2 Port event..........................................................................................................................201
20.3 Tasks and events pin configuration..................................................................................201
20.4 Registers........................................................................................................................... 201
20.5 Electrical specification.......................................................................................................211
21 PPI Programmable peripheral interconnect...............................................212
21.1 Pre-programmed channels................................................................................................213
21.2 Registers........................................................................................................................... 213
22 RADIO 2.4 GHz Radio.................................................................................. 249
22.1 Packet configuration..........................................................................................................249
22.2 Address configuration........................................................................................................250
22.3 Data whitening.................................................................................................................. 251
22.4 CRC...................................................................................................................................251
22.5 Radio states...................................................................................................................... 252
22.6 Transmit sequence............................................................................................................253
22.7 Receive sequence.............................................................................................................254
22.8 Received Signal Strength Indicator (RSSI).......................................................................256
22.9 Interframe spacing.............................................................................................................256
22.10 Device address match.................................................................................................... 257
22.11 Bit counter.......................................................................................................................257
22.12 IEEE 802.15.4 Operation................................................................................................258
22.13 EasyDMA.........................................................................................................................265
22.14 Registers......................................................................................................................... 266
22.15 Electrical specification.....................................................................................................287
23 TIMER Timer/counter....................................................................................292
23.1 Capture..............................................................................................................................293
23.2 Compare............................................................................................................................293
23.3 Task delays.......................................................................................................................293
23.4 Task priority.......................................................................................................................293
23.5 Registers........................................................................................................................... 293
23.6 Electrical specification.......................................................................................................299
Contents
Page 4
24 RTC Real-time counter.................................................................................300
24.1 Clock source..................................................................................................................... 300
24.2 Resolution versus overflow and the PRESCALER...........................................................300
24.3 COUNTER register............................................................................................................301
24.4 Overflow features..............................................................................................................301
24.5 TICK event........................................................................................................................ 301
24.6 Event control feature.........................................................................................................302
24.7 Compare feature............................................................................................................... 302
24.8 TASK and EVENT jitter/delay...........................................................................................304
24.9 Reading the COUNTER register.......................................................................................306
24.10 Registers......................................................................................................................... 306
24.11 Electrical specification.....................................................................................................312
25 RNG Random number generator................................................................ 313
25.1 Bias correction.................................................................................................................. 313
25.2 Speed................................................................................................................................ 313
25.3 Registers........................................................................................................................... 313
25.4 Electrical specification.......................................................................................................315
26 TEMP Temperature sensor.......................................................................... 316
26.1 Registers........................................................................................................................... 316
26.2 Electrical specification.......................................................................................................321
27 ECB AES electronic codebook mode encryption......................................322
27.1 Shared resources..............................................................................................................322
27.2 EasyDMA...........................................................................................................................322
27.3 ECB data structure............................................................................................................322
27.4 Registers........................................................................................................................... 323
27.5 Electrical specification.......................................................................................................324
28 CCM AES CCM mode encryption................................................................325
28.1 Shared resources..............................................................................................................325
28.2 Key-steam generation....................................................................................................... 325
28.3 Encryption..........................................................................................................................326
28.4 Decryption......................................................................................................................... 326
28.5 AES CCM and RADIO concurrent operation....................................................................327
28.6 Encrypting packets on-the-fly in radio transmit mode.......................................................327
28.7 Decrypting packets on-the-fly in radio receive mode........................................................328
28.8 CCM data structure...........................................................................................................329
28.9 EasyDMA and ERROR event...........................................................................................330
28.10 Registers......................................................................................................................... 330
28.11 Electrical specification.....................................................................................................334
29 AAR Accelerated address resolver.............................................................335
29.1 Shared resources..............................................................................................................335
29.2 EasyDMA...........................................................................................................................335
29.3 Resolving a resolvable address........................................................................................335
29.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................336
29.5 IRK data structure.............................................................................................................336
29.6 Registers........................................................................................................................... 337
29.7 Electrical specification.......................................................................................................339
30 SPIM Serial peripheral interface master with EasyDMA............................340
30.1 SPI master transaction sequence.....................................................................................340
30.2 D/CX functionality..............................................................................................................341
30.3 Pin configuration............................................................................................................... 342
30.4 Shared resources..............................................................................................................342
30.5 EasyDMA...........................................................................................................................342
30.6 Low power.........................................................................................................................344
30.7 Registers........................................................................................................................... 344
30.8 Electrical specification.......................................................................................................352
31 SPIS Serial peripheral interface slave with EasyDMA...............................354
Contents
Page 5
31.1 Shared resources..............................................................................................................354
31.2 EasyDMA...........................................................................................................................354
31.3 SPI slave operation...........................................................................................................355
31.4 Pin configuration............................................................................................................... 356
31.5 Registers........................................................................................................................... 357
31.6 Electrical specification.......................................................................................................365
32 TWIM — I2C compatible two-wire interface master with EasyDMA...............367
32.1 Shared resources..............................................................................................................368
32.2 EasyDMA...........................................................................................................................368
32.3 Master write sequence......................................................................................................368
32.4 Master read sequence...................................................................................................... 369
32.5 Master repeated start sequence.......................................................................................370
32.6 Low power.........................................................................................................................371
32.7 Master mode pin configuration......................................................................................... 371
32.8 Registers........................................................................................................................... 371
32.9 Electrical specification.......................................................................................................378
32.10 Pullup resistor................................................................................................................. 379
33 TWIS I2C compatible two-wire interface slave with EasyDMA..................380
33.1 Shared resources..............................................................................................................382
33.2 EasyDMA...........................................................................................................................382
33.3 TWI slave responding to a read command.......................................................................382
33.4 TWI slave responding to a write command...................................................................... 383
33.5 Master repeated start sequence.......................................................................................384
33.6 Terminating an ongoing TWI transaction..........................................................................385
33.7 Low power.........................................................................................................................385
33.8 Slave mode pin configuration........................................................................................... 385
33.9 Registers........................................................................................................................... 386
33.10 Electrical specification.....................................................................................................392
34 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 394
34.1 Shared resources..............................................................................................................394
34.2 EasyDMA...........................................................................................................................394
34.3 Transmission..................................................................................................................... 395
34.4 Reception.......................................................................................................................... 395
34.5 Error conditions.................................................................................................................397
34.6 Using the UARTE without flow control............................................................................. 397
34.7 Parity and stop bit configuration....................................................................................... 397
34.8 Low power.........................................................................................................................398
34.9 Pin configuration............................................................................................................... 398
34.10 Registers......................................................................................................................... 398
34.11 Electrical specification.....................................................................................................407
35 QDEC Quadrature decoder..........................................................................408
35.1 Sampling and decoding.................................................................................................... 408
35.2 LED output........................................................................................................................ 409
35.3 Debounce filters................................................................................................................ 409
35.4 Accumulators.....................................................................................................................410
35.5 Output/input pins...............................................................................................................410
35.6 Pin configuration............................................................................................................... 410
35.7 Registers........................................................................................................................... 411
35.8 Electrical specification.......................................................................................................417
36 SAADC — Successive approximation analog-to-digital converter...............418
36.1 Shared resources..............................................................................................................418
36.2 Overview............................................................................................................................418
36.3 Digital output..................................................................................................................... 419
36.4 Analog inputs and channels..............................................................................................420
36.5 Operation modes...............................................................................................................420
36.6 EasyDMA...........................................................................................................................422
36.7 Resistor ladder..................................................................................................................423
36.8 Reference..........................................................................................................................424
Contents
Page 6
36.9 Acquisition time.................................................................................................................424
36.10 Limits event monitoring...................................................................................................425
36.11 Registers......................................................................................................................... 426
36.12 Electrical specification.....................................................................................................450
36.13 Performance factors........................................................................................................452
37 COMP Comparator........................................................................................453
37.1 Differential mode...............................................................................................................454
37.2 Single-ended mode........................................................................................................... 455
37.3 Registers........................................................................................................................... 457
37.4 Electrical specification.......................................................................................................462
38 LPCOMP Low power comparator................................................................463
38.1 Shared resources..............................................................................................................464
38.2 Pin configuration............................................................................................................... 464
38.3 Registers........................................................................................................................... 465
38.4 Electrical specification.......................................................................................................469
39 WDT Watchdog timer................................................................................... 470
39.1 Reload criteria...................................................................................................................470
39.2 Temporarily pausing the watchdog...................................................................................470
39.3 Watchdog reset.................................................................................................................470
39.4 Registers........................................................................................................................... 471
39.5 Electrical specification.......................................................................................................475
40 SWI Software interrupts...............................................................................476
40.1 Registers........................................................................................................................... 476
41 NFCT Near field communication tag...........................................................477
41.1 Overview............................................................................................................................477
41.2 Operating states................................................................................................................479
41.3 Pin configuration............................................................................................................... 480
41.4 EasyDMA...........................................................................................................................480
41.5 Frame assembler.............................................................................................................. 481
41.6 Frame disassembler..........................................................................................................482
41.7 Frame timing controller..................................................................................................... 483
41.8 Collision resolution............................................................................................................484
41.9 Antenna interface..............................................................................................................485
41.10 NFCT antenna recommendations...................................................................................485
41.11 Battery protection............................................................................................................486
41.12 References...................................................................................................................... 486
41.13 Registers......................................................................................................................... 486
41.14 Electrical specification.....................................................................................................498
42 PDM Pulse density modulation interface................................................... 499
42.1 Master clock generator..................................................................................................... 499
42.2 Module operation.............................................................................................................. 499
42.3 Decimation filter................................................................................................................ 500
42.4 EasyDMA...........................................................................................................................500
42.5 Hardware example............................................................................................................501
42.6 Pin configuration............................................................................................................... 501
42.7 Registers........................................................................................................................... 502
42.8 Electrical specification.......................................................................................................507
43 I2S Inter-IC sound interface......................................................508
43.1 Mode..................................................................................................................................508
43.2 Transmitting and receiving................................................................................................508
43.3 Left right clock (LRCK)..................................................................................................... 509
43.4 Serial clock (SCK).............................................................................................................509
43.5 Master clock (MCK).......................................................................................................... 510
43.6 Width, alignment and format.............................................................................................510
43.7 EasyDMA...........................................................................................................................512
Contents
Page 7
43.8 Module operation.............................................................................................................. 514
43.9 Pin configuration............................................................................................................... 515
43.10 Registers......................................................................................................................... 516
43.11 Electrical specification.....................................................................................................523
44 MWU Memory watch unit.............................................................................524
44.1 Registers........................................................................................................................... 524
45 EGU Event generator unit............................................................................551
45.1 Registers........................................................................................................................... 551
45.2 Electrical specification.......................................................................................................557
46 PWM Pulse width modulation..................................................................... 558
46.1 Wave counter....................................................................................................................558
46.2 Decoder with EasyDMA....................................................................................................561
46.3 Limitations......................................................................................................................... 566
46.4 Pin configuration............................................................................................................... 566
46.5 Registers........................................................................................................................... 567
46.6 Electrical specification.......................................................................................................575
47 SPI Serial peripheral interface master........................................................576
47.1 Functional description....................................................................................................... 576
47.2 Registers........................................................................................................................... 579
47.3 Electrical specification.......................................................................................................582
48 TWI I2C compatible two-wire interface....................................................... 583
48.1 Functional description....................................................................................................... 583
48.2 Master mode pin configuration......................................................................................... 583
48.3 Shared resources..............................................................................................................584
48.4 Master write sequence......................................................................................................584
48.5 Master read sequence...................................................................................................... 585
48.6 Master repeated start sequence.......................................................................................586
48.7 Low power.........................................................................................................................587
48.8 Registers........................................................................................................................... 587
48.9 Electrical specification.......................................................................................................591
49 UART Universal asynchronous receiver/transmitter.................................593
49.1 Functional description....................................................................................................... 593
49.2 Pin configuration............................................................................................................... 593
49.3 Shared resources..............................................................................................................594
49.4 Transmission..................................................................................................................... 594
49.5 Reception.......................................................................................................................... 594
49.6 Suspending the UART...................................................................................................... 595
49.7 Error conditions.................................................................................................................595
49.8 Using the UART without flow control................................................................................596
49.9 Parity configuration............................................................................................................596
49.10 Registers......................................................................................................................... 596
49.11 Electrical specification.....................................................................................................601
50 ACL Access control lists.............................................................................602
50.1 Registers........................................................................................................................... 603
51 USBD Universal serial bus device..............................................................611
51.1 USB device states.............................................................................................................611
51.2 USB terminology............................................................................................................... 612
51.3 USB pins........................................................................................................................... 613
51.4 USBD start-up sequence.................................................................................................. 613
51.5 USB pull-up.......................................................................................................................614
51.6 USB reset..........................................................................................................................614
51.7 USB suspend and resume................................................................................................615
51.8 EasyDMA...........................................................................................................................616
51.9 Control transfers................................................................................................................617
51.10 Bulk and interrupt transactions....................................................................................... 620
51.11 Isochronous transactions................................................................................................ 622
51.12 USB register access limitations...................................................................................... 624
Contents
Page 8
51.13 Registers......................................................................................................................... 625
51.14 Electrical specification.....................................................................................................662
52 QSPI Quad serial peripheral interface........................................................663
52.1 Configuring peripheral.......................................................................................................663
52.2 Write operation..................................................................................................................664
52.3 Read operation..................................................................................................................664
52.4 Erase operation.................................................................................................................664
52.5 Execute in place............................................................................................................... 664
52.6 Sending custom instructions.............................................................................................665
52.7 Deep power-down mode...................................................................................................666
52.8 Instruction set....................................................................................................................666
52.9 Interface description..........................................................................................................667
52.10 Registers......................................................................................................................... 671
52.11 Electrical specification.....................................................................................................680
53 CRYPTOCELL ARM TrustZone CryptoCell 310..........................................681
53.1 Standards.......................................................................................................................... 682
53.2 Control interface................................................................................................................682
54 Mechanical specifications................................................................................ 684
54.1 AQFN73 7 x 7 mm package.............................................................................................684
55 Ordering information.........................................................................................685
55.1 Package marking.............................................................................................................. 685
55.2 Box labels..........................................................................................................................685
55.3 Order code........................................................................................................................ 686
55.4 Code ranges and values...................................................................................................686
55.5 Product options................................................................................................................. 687
56 Reference circuitry............................................................................................688
56.1 Circuit configuration no. 1.................................................................................................688
56.2 Circuit configuration no. 2.................................................................................................689
56.3 Circuit configuration no. 3.................................................................................................690
56.4 Circuit configuration no. 4.................................................................................................692
56.5 Circuit configuration no. 5.................................................................................................693
56.6 Circuit configuration no. 6.................................................................................................694
56.7 PCB guidelines..................................................................................................................695
56.8 PCB layout example......................................................................................................... 695
57 Liability disclaimer............................................................................................ 698
57.1 RoHS and REACH statement...........................................................................................698
57.2 Life support applications................................................................................................... 698
1 Revision history
Page 9
1 Revision history
Date Version Description
July 2017 0.5.1 The following content is changed in this version:
Pin assignments on page 13: Added description for trace pins
CPU on page 18: Improved SysTick timer description
Memory on page 20: Memory map figure updated
AHB multilayer on page 25: Added SPIM3 and updated RAMPRI registers
EasyDMA on page 26: Miscellaneous documentation improvements
UICR — User information configuration registers on page 44: Improved
APPROTECT description and added DEBUGCTRL register
SPIM — Serial peripheral interface master with EasyDMA on page 340:
Fixed error in mode table and changed the base address of SPIM3
Debug and trace on page 62: Added r_pull parameter for CTRL-AP, in
addition to miscellaneous documentation improvements
POWER — Power supply on page 66:
Added clarifications for supplying external circuitry
Improved register descriptions
Removed deprecated RAMON and RAMONB registers
Removed pin reset from CTRL-AP feature
Improved description of POFCON
CLOCK — Clock control on page 141:
Added HFXO debounce functionality
Changed LFRC accuracy to +- 500 ppm
Improved description in TRACECONFIG register
RADIO — 2.4 GHz Radio on page 249:
Removed 9 dBm output power option
Updated TX sequence figure
Improved TIFS description
Added PHYEND event
Added PDUSTAT register
Removed 250 kbit/s Nordic proprietary mode
Changed to using term bps instead of sps for data rate in electrical
specifications
SAADC — Successive approximation analog-to-digital converter on page
418: Updated VDD/5 input specification
COMP — Comparator on page 453: REFSEL AREF value changed
PWM — Pulse width modulation on page 558: Changed width of
DECODER.LOAD field
PDM — Pulse density modulation interface on page 499: Fixed error in
electrical specification units
I2S — Inter-IC sound interface on page 508: PSEL registers PORT field
updated
Reference circuitry on page 688: Reference schematics updated and
erroneous sentence for VDD/VDDH connection removed
Block diagram on page 12: Miscellaneous improvements
December 2016 0.5 First release
2 About this document
Page 10
2 About this document
This product specification is organized into chapters based on the modules and peripherals that are available
in this IC.
The peripheral descriptions are divided into separate sections that include the following information:
A detailed functional description of the peripheral
Register configuration for the peripheral
Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 17.
2.1 Document naming and status
Nordic uses three distinct names for this document, which are reflecting the maturity and the status of the
document and its content.
Table 1: Defined document names
Document name Description
Objective Product Specification (OPS) Applies to document versions up to 0.7.
This product specification contains target specifications for product development.
Preliminary Product Specification (PPS) Applies to document versions 0.7 and up to 1.0.
This product specification contains preliminary data. Supplementary data may be
published from Nordic Semiconductor ASA later.
Product Specification (PS) Applies to document versions 1.0 and higher.
This product specification contains final product specifications. Nordic
Semiconductor ASA reserves the right to make changes at any time without notice
in order to improve design and supply the best possible product.
2.2 Peripheral naming and abbreviations
Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for
identification and reference. This name is used in chapter headings and references, and it will appear in the
ARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identify
the peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using the
peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally
only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in
the CMSIS to identify the peripheral instance.
2.3 Register tables
Individual registers are described using register tables. These tables are built up of two sections. The first
three colored rows describe the position and size of the different fields in the register. The following rows
describe the fields in more detail.
2.3.1 Fields and values
The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has
enumerated values, then every value will be identified with a unique value id in the Value Id column.
A blank space means that the field is reserved and read as undefined, and it also must be written as 0 to
secure forward compatibility. If a register is divided into more than one field, a unique field name is specified
for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can be
substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/off, and so on.
2 About this document
Page 11
Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal
values have no prefix.
The Value column can be populated in the following ways:
Individual enumerated values, for example 1, 3, 9.
Range of values, e.g. [0..4], indicating all values from and including 0 and 4.
Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field's translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the
first field. Subsequent fields will indicate inheritance with '..'.
A feature marked Deprecated should not be used for new designs.
2.4 Registers
Table 2: Register Overview
Register Offset Description
DUMMY 0x514 Example of a register controlling a dummy feature
2.4.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D C C C B A A
Reset 0x00050002 0 0000000000001010000000000000010
Id RW Field Value Id Value Description
A RW FIELD_A Example of a field with several enumerated values
Disabled 0 The example feature is disabled
NormalMode 1 The example feature is enabled in normal mode
ExtendedMode 2 The example feature is enabled along with extra functionality
B RW FIELD_B Example of a deprecated field Deprecated
Disabled 0 The override feature is disabled
Enabled 1 The override feature is enabled
C RW FIELD_C Example of a field with a valid range of values
ValidRange [2..7] Example of allowed values for this field
D RW FIELD_D Example of a field with no restriction on the values
3 Block diagram
Page 12
3 Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that share
physical pins with other signals.
nRF52840
APB0
AHB TO APB
BRIDGE
RADIO
CPU
ARM
CORTEX-M4
AHB-AP
RNG
TEMP
WDT
NVMC
ANT
POWER
nRESET RTC [0..2]
PPI
TIMER [0..4]
NVIC
UICRFICR
SW-DP
CODE
EasyDMA master
QDEC
SAADC
GPIOTE
P0
(P0.0 – P0.31)
AIN0 AIN7
LED
A
B
UARTE [0..1]
SPIS [0..2] MOSI
MISO
CSN
COMP
EasyDMA
RXD
TXD
CTS
RTS
ETM
SysTick
TPIU
TP
EasyDMA
LPCOMP
EasyDMA
master
master
NFCT
NFC1
NFC2
EasyDMA master
master
SWDIO
SWCLK
CTRL-AP
PWM [0..3]
OUT0 – OUT3
I2S
MCK
LRCK
SCL
SDOUT
SDIN
PDM
CLK
DIN
SCK
EasyDMA master
EasyDMA master
EasyDMA master
I-Cache
slave
slave
slave
slave
slave
master
CLOCK
XL2
XL1
XC2
XC1
USBD
D-
D+
EasyDMA master
VBUS
SPIM [0..3]
SCK
MISO
EasyDMA
MOSI
master
TWIM [0..1] SCL
SDA
EasyDMA
master
QSPI IO3
IO2
IO1
IO0
EasyDMA
master CSN
SCK
ECB
EasyDMAmaster
CCM
EasyDMA
master
AAR
EasyDMA
master
CryptoCell
DMA
master
TWIS [0..1] SCL
SDA
EasyDMA
master
RAM0
slave
RAM1
slave
RAM2
slave
RAM3
slave
RAM4
slave
RAM5
slave
RAM6
slave
RAM7
slave
GPIO
slave
RAM8
slave
AHB multilayer
Figure 1: Block diagram
4 Pin assignments
Page 13
4 Pin assignments
This section describes the pin assignment and the pin functions.
This device provides flexibility when it comes to routing and configuration of the GPIO pins. However, some
pins have recommendations for how the pin should be configured or what it should be used for. See Table 3:
QIAA pin assignments on page 13 for more information about this.
4.1 QIAA pin assignments
This section describes the pin assignment and the pin functions.
Figure 2: QIAA pin assignments, top view
Table 3: QIAA pin assignments
Pin Name Function Description Recommended usage
A8 P0.31
AIN7
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
A10 P0.29
AIN5
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
A12 P0.02
AIN0
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
A14 P1.15 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
A16 P1.13 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
A18 DEC2 Power 1.3 V regulator supply decoupling (Radio supply)
A20 P1.10 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
A22 VDD Power Power supply
A23 XC2 Analog input Connection for 32 MHz crystal.
B1 VDD Power Power supply
B3 DCC Power DC/DC converter output
4 Pin assignments
Page 14
Pin Name Function Description Recommended usage
B5 DEC4 Power 1.3 V regulator supply decoupling
B7 VSS Power Ground
B9 P0.30
AIN6
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
B11 P0.28
AIN4
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
B13 P0.03
AIN1
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
B15 P1.14 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
B17 P1.12 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
B19 P0.11
TRACEDATA2
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[2].
Standard drive, low frequency I/O
only.
B24 XC1 Analog input Connection for 32 MHz crystal
C1 DEC1 Power 1.1 V regulator supply decoupling
D2 P0.00
XL1
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal
D23 DEC3 Power Power supply, decoupling
E24 DEC6 Power 1.3 V regulator supply decoupling (Radio supply)
F2 P0.01
XL2
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal
F23 VSS_PA Power Ground (Radio supply)
G1 P0.26 Digital I/O General purpose I/O
H2 P0.27 Digital I/O General purpose I/O
H23 ANT RF Single-ended radio antenna connection See Reference circuitry on page
688 for guidelines on how to
ensure good RF performance.
J1 P0.04
AIN2
Digital I/O
Analog input
General purpose I/O
Analog input
J24 P0.10
NFC2
Digital I/O
NFC input
General purpose I/O
NFC antenna connection
Standard drive, low frequency I/O
only.
K2 P0.05
AIN3
Digital I/O
Analog input
General purpose I/O
Analog input
L1 P0.06 Digital I/O General purpose I/O
L24 P0.09
NFC1
Digital I/O
NFC input
General purpose I/O
NFC antenna connection
Standard drive, low frequency I/O
only.
M2 P0.07
TRACECLK
Digital I/O
Trace clock
General purpose I/O pin
Trace buffer clock
N1 P0.08 Digital I/O General purpose I/O
N24 DEC5 Power 1.3 V regulator supply decoupling (flash supply)
P2 P1.08 Digital I/O General purpose I/O
P23 P1.07 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
R1 P1.09
TRACEDATA3
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[3].
R24 P1.06 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
T2 P0.11 Digital I/O General purpose I/O
T23 P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
U1 P0.12
TRACEDATA1
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[1].
4 Pin assignments
Page 15
Pin Name Function Description Recommended usage
U24 P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
V23 P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
W1 VDD Power Power supply
W24 P1.02 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
Y2 VDDH Power High voltage power supply
Y23 P1.01 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
AA24 SWDCLK Debug Serial wire debug clock input for debug and
programming
AB2 DCCH Power DC/DC converter output
AC5 DECUSB Power Decoupling for USB 3.3 V
AC9 P0.14 Digital I/O General purpose I/O
AC11 P0.16 Digital I/O General purpose I/O
AC13 P0.18
nRESET
Digital I/O General purpose I/O
Configurable as system RESET
QSPI/CSN
AC15 P0.19 Digital I/O General purpose I/O QSPI/SCK
AC17 P0.21 Digital I/O General purpose I/O QSPI
AC19 P0.23 Digital I/O General purpose I/O QSPI
AC21 P0.25 Digital I/O General purpose I/O
AC24 SWDIO Debug Debug serial data
AD2 VBUS Power 5 V input for USB 3.3 V regulator
AD4 D- Digital I/O USB D- USB
AD6 D+ Digital I/O USB D+ USB
AD8 P0.13 Digital I/O General purpose I/O
AD10 P0.15 Digital I/O General purpose I/O
AD12 P0.17 Digital I/O General purpose I/O
AD14 VDD Power Power supply
AD16 P0.20 Digital I/O General purpose I/O
AD18 P0.22 Digital I/O General purpose I/O QSPI
AD20 P0.24 Digital I/O General purpose I/O
AD22 P1.00
TRACEDATA0
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[0].
Serial wire output (SWO).
QSPI
AD23 VDD Power Flash supply pad
Bottom of chip
Die pad VSS Power Ground pad. Exposed die pad must be connected to
ground (VSS) for proper device operation.
Important: For more information on Standard drive, see GPIO — General purpose input/output on
page 154. Low frequency I/O is signals with a frequency up to 10 kHz.
5 Absolute maximum ratings
Page 16
5 Absolute maximum ratings
Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time
without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may
affect the reliability of the device.
Table 4: Absolute maximum ratings
Note Min. Max. Unit
Supply voltages
VDD -0.3 +3.9 V
VDDH -0.3 +5.8 V
VBUS -0.3 +5.8 V
VSS 0 V
I/O pin voltage
VI/O, VDD ≤3.6 V -0.3 VDD + 0.3 V V
VI/O, VDD >3.6 V -0.3 3.9 V V
NFC antenna pin current
INFC1/2 80 mA
Radio
RF input level 10 dBm
Environmental (AQFN package)
Storage temperature -40 +125 °C
MSL Moisture Sensitivity Level 2
ESD HBM Human Body Model 4 kV
ESD CDMQF Charged Device Model
(AQFN73, 7×7 mm package)
750 V
Flash memory
Endurance 10 000 Write/erase cycles
Retention 10 years at 40°C
6 Recommended operating conditions
Page 17
6 Recommended operating conditions
The operating conditions are the physical parameters that the chip can operate within.
Table 5: Recommended operating conditions
Symbol Parameter Notes Min. Nom. Max. Units
VDD VDD supply voltage, independent of DCDC enable 1.7 3.0 3.6 V
VDDPOR VDD supply voltage needed during power-on
reset
1.75 V
VDDH VDDH supply voltage, independent of DCDC
enable
2.5 3.7 5.5 V
VBUS VBUS USB supply voltage 4.35 5 5.5 V
tR_VDD Supply rise time (0 V to 1.7 V) 60 ms
tR_VDDH Supply rise time (0 V to 3.7 V) 100 ms
TA Operating temperature -40 25 85 °C
Important: The on-chip power-on reset circuitry may not function properly for rise times longer than
the specified maximum.
7 CPU
Page 18
7 CPU
The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2
technology) that implements a superset of 16 and 32-bit instructions to maximize code density and
performance.
This processor implements several features that enable energy-efficient arithmetic and high-performance
signal processing, including:
Digital signal processing (DSP) instructions
Single-cycle multiply and accumulate (MAC) instructions
Hardware divide
8- and 16-bit single instruction multiple data (SIMD) instructions
Single-precision floating-point unit (FPU)
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling
events at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 series. An instruction cache can be
enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache
on page 29. The section Electrical specification on page 18 shows CPU performance parameters
including wait states in different modes, CPU current and efficiency, and processing power and efficiency
based on the CoreMark® benchmark.
The ARM System Timer (SysTick) is present on nRF52840. The SysTick's clock will only tick when the CPU
is running or when the system is in debug interface mode.
7.1 Floating point interrupt
The floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which in
turn will trigger the FPU interrupt.
See Instantiation on page 23 for more information about the exceptions triggering the FPU interrupt.
To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit within
the floating-point status and control register (FPSCR) needs to be cleared. For more information about the
FPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
7.2 Electrical specification
7.2.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is
executing the CoreMark benchmark. It includes power regulator and clock base currents. All other blocks
are IDLE.
Symbol Description Min. Typ. Max. Units
WFLASH CPU wait states, running CoreMark from flash, cache disabled 2
WFLASHCACHE CPU wait states, running CoreMark from flash, cache enabled 3
WRAM CPU wait states, running CoreMark from RAM 0
IDDFLASHCACHE CPU current, running CoreMark from flash, cache enabled, LDO 6.5 mA
IDDFLASHCACHEDCDC CPU current, running CoreMark from flash, cache enabled,
DCDC 3V
3.6 mA
IDDFLASH CPU current, running CoreMark from flash, cache disabled, LDO mA
7 CPU
Page 19
Symbol Description Min. Typ. Max. Units
IDDFLASHDCDC CPU current, running CoreMark from flash, cache disabled,
DCDC 3V
mA
IDDRAM CPU current, running CoreMark from RAM, LDO mA
IDDRAMDCDC CPU current, running CoreMark from RAM, DCDC 3V mA
IDDFLASH/MHz CPU efficiency, running CoreMark from flash, cache enabled,
LDO
102 µA/
MHz
IDDFLASHDCDC/MHz CPU efficiency, running CoreMark from flash, cache enabled,
DCDC 3V
56 µA/
MHz
CMFLASH CoreMark, running CoreMark from flash, cache enabled 212 CoreMark
CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache
enabled
3.3 CoreMark/
MHz
CMFLASH/mA CoreMark per mA, running CoreMark from flash, cache enabled,
DCDC 3V
59 CoreMark/
mA
7.3 CPU and support module configuration
The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the
device.
Option / Module Description Implemented
Core options
NVIC Nested vector interrupt controller 37 vectors
PRIORITIES Priority bits 3
WIC Wakeup interrupt controller NO
Endianness Memory system endianness Little endian
Bit-banding Bit banded memory NO
DWT Data watchpoint and trace YES
SysTick System tick timer YES
Modules
MPU Memory protection unit YES
FPU Floating-point unit YES
DAP Debug access port YES
ETM Embedded trace macrocell YES
ITM Instrumentation trace macrocell YES
TPIU Trace port interface unit YES
ETB Embedded trace buffer NO
FPB Flash patch and breakpoint unit YES
HTM AMBA AHB trace macrocell NO
8 Memory
Page 20
8 Memory
The nRF52840 contains 1 MB of flash and 256 kB of RAM that can be used for code and data storage.
The CPU and the peripherals having EasyDMA can access memory via the AHB multilayer interconnect.
The CPU is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Figure 3:
Memory layout on page 20.
RAM3
AHB slave
RAM2
AHB slave
RAM1
AHB slave
RAM0
AHB slave
RAM7
AHB slave
RAM6
AHB slave
RAM5
AHB slave
RAM4
AHB slave
AHB multilayer interconnect
AHB
slave
Page 0
Page 1
Page 2
Page 3..254
Page 255
0x0000 0000
0x0000 2000
0x0000 3000
0x000F F000
Flash
ICODE/DCODE
AHB
slave
NVMC
ICODE
DCODE
Peripheral
EasyDMA
DMA bus
Peripheral
EasyDMA
DMA bus
CPU
ARM Cortex-M4
System bus
ICODE
DCODE
AHB2APB
AHB
APB
Block 0
Block 1
Block 2..6
Block 7
0x0000 0200
0x0000 0400
0x0000 1000
0x0000 0E00
I-Cache
0x2000 0000
0x2000 1000
0x2000 2000
0x2000 3000
0x2000 4000
0x2000 5000
0x2000 6000
0x2000 7000
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
0x2000 8000
0x2000 9000
0x2000 A000
0x2000 B000
0x2000 C000
0x2000 D000
0x2000 E000
0x2000 F000
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Data RAM
System
0x0080 0000
0x0080 1000
0x0080 2000
0x0080 3000
0x0080 4000
0x0080 5000
0x0080 6000
0x0080 7000
0x0080 8000
0x0080 9000
0x0080 A000
0x0080 B000
0x0080 C000
0x0080 D000
0x0080 E000
0x0080 F000
Code RAM
ICODE / DCODE
Section 0
Section 1
Section 2
Section 3
Section 4
Section 5
0x2001 0000 0x0081 0000
0x2001 8000 0x0081 8000
0x2002 0000 0x0082 0000
0x2002 8000 0x0082 8000
0x2003 0000 0x0083 0000
0x2003 8000 0x0083 8000
RAM8
AHB slave
Figure 3: Memory layout
See AHB multilayer on page 25 and EasyDMA on page 26 for more information about the AHB
multilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to the
application to partition the RAM within these regions so that one does not corrupt the other.
8.1 RAM - Random access memory
The RAM interface is divided into 9 RAM AHB slaves.
RAM AHB slave 0-7 is connected to 2x4 kB RAM sections each and RAM AHB slave 8 is connected to 6x32
kB sections, as shown in Figure 3: Memory layout on page 20.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,
which is configured via RAM register (see the POWER — Power supply on page 66).
8.2 Flash - Non-volatile memory
The flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of
times it can be written and erased and also on how it can be written.
8 Memory
Page 21
Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatile
memory controller on page 28.
The flash is divided into 256x4 kB pages that can be accessed by the CPU via both the ICODE and DCODE
buses as shown in Figure 3: Memory layout on page 20. Each page is divided into 8 blocks.
8.3 Memory map
The complete memory map is shown in Figure 4: Memory map on page 22. As described in Memory on
page 20, Code RAM and the Data RAM are the same physical RAM.
8 Memory
Page 22
Device
Device
Device
RAM
RAM
Peripheral
SRAM
Code
Private peripheral bus
AHB peripherals
APB peripherals
UICR
FICR
Data RAM
Code RAM
Flash
0xFFFFFFFF
0x00000000
0x20000000
0x40000000
0x60000000
0x80000000
0xA0000000
0xC0000000
0xE0000000
0x00000000
0x10000000
0x40000000
0x50000000
0xE0000000
0x00800000
0x10001000
0x20000000
XIP 0x12000000
0x19FFFFFF
System address map Address map
Figure 4: Memory map
8 Memory
Page 23
8.4 Instantiation
Table 6: Instantiation table
ID Base Address Peripheral Instance Description
0 0x40000000 CLOCK CLOCK Clock control
0 0x40000000 POWER POWER Power control
1 0x40001000 RADIO RADIO 2.4 GHz radio
2 0x40002000 UARTE UARTE0 Universal asynchronous receiver/transmitter with EasyDMA, unit 0
2 0x40002000 UART UART0 Universal asynchronous receiver/transmitter Deprecated
3 0x40003000 TWIM TWIM0 Two-wire interface master 0
3 0x40003000 SPIS SPIS0 SPI slave 0
3 0x40003000 SPIM SPIM0 SPI master 0
3 0x40003000 SPI SPI0 SPI master 0 Deprecated
3 0x40003000 TWIS TWIS0 Two-wire interface slave 0
3 0x40003000 TWI TWI0 Two-wire interface master 0 Deprecated
4 0x40004000 TWIS TWIS1 Two-wire interface slave 1
4 0x40004000 SPIS SPIS1 SPI slave 1
4 0x40004000 SPIM SPIM1 SPI master 1
4 0x40004000 TWI TWI1 Two-wire interface master 1 Deprecated
4 0x40004000 TWIM TWIM1 Two-wire interface master 1
4 0x40004000 SPI SPI1 SPI master 1 Deprecated
5 0x40005000 NFCT NFCT Near field communication tag
6 0x40006000 GPIOTE GPIOTE GPIO tasks and events
7 0x40007000 SAADC SAADC Analog to digital converter
8 0x40008000 TIMER TIMER0 Timer 0
9 0x40009000 TIMER TIMER1 Timer 1
10 0x4000A000 TIMER TIMER2 Timer 2
11 0x4000B000 RTC RTC0 Real-time counter 0
12 0x4000C000 TEMP TEMP Temperature sensor
13 0x4000D000 RNG RNG Random number generator
14 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption
15 0x4000F000 AAR AAR Accelerated address resolver
15 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption
16 0x40010000 WDT WDT Watchdog timer
17 0x40011000 RTC RTC1 Real-time counter 1
18 0x40012000 QDEC QDEC Quadrature decoder
19 0x40013000 LPCOMP LPCOMP Low power comparator
19 0x40013000 COMP COMP General purpose comparator
20 0x40014000 EGU EGU0 Event generator unit 0
20 0x40014000 SWI SWI0 Software interrupt 0
21 0x40015000 EGU EGU1 Event generator unit 1
21 0x40015000 SWI SWI1 Software interrupt 1
22 0x40016000 EGU EGU2 Event generator unit 2
22 0x40016000 SWI SWI2 Software interrupt 2
23 0x40017000 EGU EGU3 Event generator unit 3
23 0x40017000 SWI SWI3 Software interrupt 3
24 0x40018000 SWI SWI4 Software interrupt 4
24 0x40018000 EGU EGU4 Event generator unit 4
25 0x40019000 SWI SWI5 Software interrupt 5
25 0x40019000 EGU EGU5 Event generator unit 5
26 0x4001A000 TIMER TIMER3 Timer 3
27 0x4001B000 TIMER TIMER4 Timer 4
28 0x4001C000 PWM PWM0 Pulse width modulation unit 0
29 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface
30 0x4001E000 ACL ACL Access control lists
30 0x4001E000 NVMC NVMC Non-volatile memory controller
8 Memory
Page 24
ID Base Address Peripheral Instance Description
31 0x4001F000 PPI PPI Programmable peripheral interconnect
32 0x40020000 MWU MWU Memory watch unit
33 0x40021000 PWM PWM1 Pulse width modulation unit 1
34 0x40022000 PWM PWM2 Pulse width modulation unit 2
35 0x40023000 SPIM SPIM2 SPI master 2
35 0x40023000 SPIS SPIS2 SPI slave 2
35 0x40023000 SPI SPI2 SPI master 2 Deprecated
36 0x40024000 RTC RTC2 Real-time counter 2
37 0x40025000 I2S I2S Inter-IC sound interface
38 0x40026000 FPU FPU FPU interrupt
39 0x40027000 USBD USBD Universal serial bus device
40 0x40028000 UARTE UARTE1 Universal asynchronous receiver/transmitter with EasyDMA, unit 1
41 0x40029000 QSPI QSPI External memory interface
45 0x4002D000 PWM PWM3 Pulse width modulation unit 3
47 0x4002F000 SPIM SPIM3 SPI master 3
0 0x50000000 GPIO GPIO General purpose input and output Deprecated
0 0x50000000 GPIO P0 General purpose input and output, port 0
0 0x50000300 GPIO P1 General purpose input and output, port 1
42 0x5002A000 CRYPTOCELL CRYPTOCELL CryptoCell subsystem control interface
N/A 0x10000000 FICR FICR Factory information configuration
N/A 0x10001000 UICR UICR User information configuration
9 AHB multilayer
Page 25
9 AHB multilayer
AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is
resolved using priorities.
Each bus master is connected to the slave devices using an interconnection matrix. The bus masters are
assigned priorities. Priorities are used to resolve access when two (or more) bus masters request access to
the same slave device. The following applies:
If two (or more) bus masters request access to the same slave device, the master with the highest priority
is granted the access first.
Bus masters with lower priority are stalled until the higher priority master has completed its transaction.
If the higher priority master pauses at any point during its transaction, the lower priority master in queue is
temporarily granted access to the slave device until the higher priority master resumes its activity.
Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.
Below is a list of bus masters in the system and their priorities.
Table 7: AHB bus masters (listed in priority order, highest to lowest)
Bus master name Description
CPU
CTRL-AP
USB
CRYPTOCELL
SPIM1/SPIS1/TWIM1/TWIS1 Same priority and mutually exclusive
RADIO
CCM/ECB/AAR Same priority and mutually exclusive
SAADC
UARTE0
SPIM0/SPIS0/TWIM0/TWIS0 Same priority and mutually exclusive
SPIM2/SPIS2 Same priority and mutually exclusive
NFCT
I2S
PDM
PWM0
PWM1
PWM2
QSPI
PWM3
UARTE1
SPIM3
Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available slaves
are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix is
illustrated in Memory on page 20.
10 EasyDMA
Page 26
10 EasyDMA
EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM.
EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for
direct access to Data RAM. EasyDMA is not able to access flash.
A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example,
for reading and writing of data between the peripheral and RAM. This concept is illustrated in Figure 5:
EasyDMA example on page 26.
Peripheral
READER
Peripheral
core
AHB multilayer
AHB
WRITER
AHB
RAM
RAM
RAM
EasyDMA
EasyDMA
Figure 5: EasyDMA example
An EasyDMA channel is usually implemented like illustrated by the code below, but some variations may
occur:
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000;
uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for
reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed
that the peripheral will:
Read 5 bytes from the readerBuffer located in RAM at address 0x20000000.
Process the data.
Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005.
The memory layout of these buffers is illustrated in Figure 6: EasyDMA memory layout on page 27.
10 EasyDMA
Page 27
readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3]
readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2]
writerBuffer[3] writerBuffer[4] writerBuffer[5]
0x20000000
0x20000004
0x20000008
Figure 6: EasyDMA memory layout
The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer
(writerBuffer). Otherwise, the channel would overflow the writerBuffer.
Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many
bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see
how many bytes WRITER wrote to RAM.
10.1 EasyDMA array list
EasyDMA is able to operate in a mode called array list.
The array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
The EasyDMA array list can be implemented by using the data structure ArrayList_type as illustrated in the
code example below:
#define BUFFER_SIZE 4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type ReaderList[3];
READER.MAXCNT = BUFFER_SIZE;
READER.PTR = &ReaderList;
The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA
uses the READER.MAXCNT register to determine when the buffer is full.
buffer[0] buffer[1]0x20000000 : ReaderList[0]
0x20000004 : ReaderList[1]
0x20000008 : ReaderList[2]
buffer[2] buffer[3]
READER.PTR = &ReaderList
buffer[0] buffer[1] buffer[2] buffer[3]
buffer[0] buffer[1] buffer[2] buffer[3]
Figure 7: EasyDMA array list
11 NVMC — Non-volatile memory controller
Page 28
11 NVMC — Non-volatile memory controller
The non-volatile memory controller (NVMC) is used for writing and erasing the internal flash memory and the
UICR.
Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before
an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page
30. The user must make sure that writing and erasing are not enabled at the same time. Failing to do so
may result in unpredictable behavior.
11.1 Writing to flash
When writing is enabled, the flash is written by writing a full 32-bit word to a word-aligned address in the
flash.
The NVMC is only able to write '0' to bits in the flash that are erased, that is, set to '1'. It cannot write back a
bit to '1'.
As illustrated in Memory on page 20, the flash is divided into multiple pages that are further divided into
multiple blocks. The same block in the flash can only be written nWRITE number of times before an erase
must be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory on
page 20 for block size.
Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits to flash,
write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that the
restriction about the number of writes (see above) still applies in this case.
The time it takes to write a word to the flash is specified by tWRITE. The CPU is halted if the CPU executes
code from the flash while the NVMC is writing to the flash.
Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.
11.2 Erasing a page in flash
When erase is enabled, the flash can be erased page by page using the ERASEPAGE register.
After erasing a flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by
tERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase
operation.
11.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as flash. After UICR has been
written, the new UICR configuration will only take effect after a reset.
UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR or
ERASEALL.
The time it takes to write a word to the UICR is specified by tWRITE. The CPU is halted if the CPU executes
code from the flash while the NVMC is writing to the UICR.
11.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR register.
After erasing UICR all bits in UICR are set to '1'. The time it takes to erase UICR is specified by tERASEPAGE.
The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.
11 NVMC — Non-volatile memory controller
Page 29
11.5 Erase all
When erase is enabled, the whole flash and UICR can be erased in one operation by using the ERASEALL
register. ERASEALL will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted if the CPU
executes code from the flash while the NVMC performs the erase operation.
11.6 Cache
An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
See the Memory map in Memory map on page 21 for the location of flash.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states
for a cache miss, where the instruction is not available in the cache and needs to be fetched from flash,
depends on the processor frequency and is shown in CPU on page 18
Enabling the cache can increase CPU performance and reduce power consumption by reducing the number
of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some
current when enabled. If the reduction in average current due to reduced flash accesses is larger than the
cache power requirement, the average current to execute the program code will reduce.
When disabled, the cache does not use current and does not retain its content.
It is possible to enable cache profiling to analyze the performance of the cache for your program using the
ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every
instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after
reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get
correct numbers.
11.7 Registers
Table 8: Instances
Base address Peripheral Instance Description Configuration
0x4001E000 NVMC NVMC Non-volatile memory controller
Table 9: Register Overview
Register Offset Description
READY 0x400 Ready flag
CONFIG 0x504 Configuration register
ERASEPAGE 0x508 Register for erasing a page in code area
ERASEPCR1 0x508 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated
ERASEALL 0x50C Register for erasing all non-volatile user memory
ERASEPCR0 0x510 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated
ERASEUICR 0x514 Register for erasing user information configuration registers
ICACHECNF 0x540 I-code cache configuration register.
IHIT 0x548 I-code cache hit counter.
IMISS 0x54C I-code cache miss counter.
11.7.1 READY
Address offset: 0x400
Ready flag
11 NVMC — Non-volatile memory controller
Page 30
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A R READY NVMC is ready or busy
Busy 0 NVMC is busy (on-going write or erase operation)
Ready 1 NVMC is ready
11.7.2 CONFIG
Address offset: 0x504
Configuration register
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW WEN Program memory access mode. It is strongly recommended
to only activate erase and write modes when they are actively
used. Enabling write or erase will invalidate the cache and keep
it invalidated.
Ren 0 Read only access
Wen 1 Write enabled
Een 2 Erase enabled
11.7.3 ERASEPAGE
Address offset: 0x508
Register for erasing a page in code area
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEPAGE Register for starting erase of a page in code area
The value is the address to the page to be erased. (Addresses of
first word in page). Note that the erase must be enabled using
CONFIG.WEN before the page can be erased. Attempts to erase
pages that are outside the code area may result in undesirable
behaviour, e.g. the wrong page may be erased.
11.7.4 ERASEPCR1 ( Deprecated )
Address offset: 0x508
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEPCR1 Register for erasing a page in code area. Equivalent to
ERASEPAGE.
11.7.5 ERASEALL
Address offset: 0x50C
Register for erasing all non-volatile user memory
11 NVMC — Non-volatile memory controller
Page 31
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEALL Erase all non-volatile memory including UICR registers. Note
that the erase must be enabled using CONFIG.WEN before the
non-volatile memory can be erased.
NoOperation 0 No operation
Erase 1 Start chip erase
11.7.6 ERASEPCR0 ( Deprecated )
Address offset: 0x510
Register for erasing a page in code area. Equivalent to ERASEPAGE.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEPCR0 Register for starting erase of a page in code area. Equivalent to
ERASEPAGE.
11.7.7 ERASEUICR
Address offset: 0x514
Register for erasing user information configuration registers
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW ERASEUICR Register starting erase of all user information configuration
registers. Note that the erase must be enabled using
CONFIG.WEN before the UICR can be erased.
NoOperation 0 No operation
Erase 1 Start erase of UICR
11.7.8 ICACHECNF
Address offset: 0x540
I-code cache configuration register.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id B A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW CACHEEN Cache enable
Disabled 0 Disable cache. Invalidates all cache entries.
Enabled 1 Enable cache
B RW CACHEPROFEN Cache profiling enable
Disabled 0 Disable cache profiling
Enabled 1 Enable cache profiling
11.7.9 IHIT
Address offset: 0x548
I-code cache hit counter.
11 NVMC — Non-volatile memory controller
Page 32
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW HITS Number of cache hits
11.7.10 IMISS
Address offset: 0x54C
I-code cache miss counter.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW MISSES Number of cache misses
11.8 Electrical specification
11.8.1 Flash programming
Symbol Description Min. Typ. Max. Units
nWRITE,BLOCK Amount of writes allowed in a block between erase 403
nWRITE Number of times an address can be written between erase12
tWRITE Time to write one 32-bit word 412µs
tERASEPAGE Time to erase one page 853ms
tERASEALL Time to erase all flash 1694ms
Iwrite Flash write current 5 mA
Ierasepage Flash erase page current 5 mA
Ieraseall Flash erase all current 5 mA
11.8.2 Cache size
Symbol Description Min. Typ. Max. Units
SizeICODE I-Code cache size 2048 Bytes
1The page must be erased when either of nWRITE,BLOCK or nWRITE is not satisfied
2HFXO is used here, this may vary upto +/-5% when HFINT is used
3HFXO is used here, this may vary upto +/-5% when HFINT is used
4HFXO is used here, this may vary upto +/-5% when HFINT is used
12 FICR — Factory information configuration
registers
Page 33
12 FICR — Factory information configuration registers
Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by
the user. These registers contain chip-specific information and configuration.
12.1 Registers
Table 10: Instances
Base address Peripheral Instance Description Configuration
0x10000000 FICR FICR Factory information configuration
Table 11: Register Overview
Register Offset Description
CODEPAGESIZE 0x010 Code memory page size
CODESIZE 0x014 Code memory size
DEVICEID[0] 0x060 Device identifier
DEVICEID[1] 0x064 Device identifier
ER[0] 0x080 Encryption root, word 0
ER[1] 0x084 Encryption root, word 1
ER[2] 0x088 Encryption root, word 2
ER[3] 0x08C Encryption root, word 3
IR[0] 0x090 Identity Root, word 0
IR[1] 0x094 Identity Root, word 1
IR[2] 0x098 Identity Root, word 2
IR[3] 0x09C Identity Root, word 3
DEVICEADDRTYPE 0x0A0 Device address type
DEVICEADDR[0] 0x0A4 Device address 0
DEVICEADDR[1] 0x0A8 Device address 1
INFO.PART 0x100 Part code
INFO.VARIANT 0x104 Part variant (hardware version and production configuration)
INFO.PACKAGE 0x108 Package option
INFO.RAM 0x10C RAM variant
INFO.FLASH 0x110 Flash variant
0x114 Reserved
0x118 Reserved
0x11C Reserved
TEMP.A0 0x404 Slope definition A0
TEMP.A1 0x408 Slope definition A1
TEMP.A2 0x40C Slope definition A2
TEMP.A3 0x410 Slope definition A3
TEMP.A4 0x414 Slope definition A4
TEMP.A5 0x418 Slope definition A5
TEMP.B0 0x41C Y-intercept B0
TEMP.B1 0x420 Y-intercept B1
TEMP.B2 0x424 Y-intercept B2
TEMP.B3 0x428 Y-intercept B3
TEMP.B4 0x42C Y-intercept B4
TEMP.B5 0x430 Y-intercept B5
TEMP.T0 0x434 Segment end T0
TEMP.T1 0x438 Segment end T1
TEMP.T2 0x43C Segment end T2
TEMP.T3 0x440 Segment end T3
TEMP.T4 0x444 Segment end T4
12 FICR — Factory information configuration
registers
Page 34
Register Offset Description
NFC.TAGHEADER0 0x450 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
NFC.TAGHEADER1 0x454 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
NFC.TAGHEADER2 0x458 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
NFC.TAGHEADER3 0x45C Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
12.1.1 CODEPAGESIZE
Address offset: 0x010
Code memory page size
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R CODEPAGESIZE Code memory page size
12.1.2 CODESIZE
Address offset: 0x014
Code memory size
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R CODESIZE Code memory size in number of pages
Total code space is: CODEPAGESIZE * CODESIZE
12.1.3 DEVICEID[0]
Address offset: 0x060
Device identifier
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEID 64 bit unique device identifier
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
12.1.4 DEVICEID[1]
Address offset: 0x064
Device identifier
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEID 64 bit unique device identifier
12 FICR — Factory information configuration
registers
Page 35
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
DEVICEID[0] contains the least significant bits of the device
identifier. DEVICEID[1] contains the most significant bits of the
device identifier.
12.1.5 ER[0]
Address offset: 0x080
Encryption root, word 0
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption root, word 0
12.1.6 ER[1]
Address offset: 0x084
Encryption root, word 1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption root, word 1
12.1.7 ER[2]
Address offset: 0x088
Encryption root, word 2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption root, word 2
12.1.8 ER[3]
Address offset: 0x08C
Encryption root, word 3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R ER Encryption root, word 3
12.1.9 IR[0]
Address offset: 0x090
Identity Root, word 0
12 FICR — Factory information configuration
registers
Page 36
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word 0
12.1.10 IR[1]
Address offset: 0x094
Identity Root, word 1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word 1
12.1.11 IR[2]
Address offset: 0x098
Identity Root, word 2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word 2
12.1.12 IR[3]
Address offset: 0x09C
Identity Root, word 3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R IR Identity Root, word 3
12.1.13 DEVICEADDRTYPE
Address offset: 0x0A0
Device address type
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEADDRTYPE Device address type
Public 0 Public address
Random 1 Random address
12.1.14 DEVICEADDR[0]
Address offset: 0x0A4
Device address 0
12 FICR — Factory information configuration
registers
Page 37
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEADDR 48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
12.1.15 DEVICEADDR[1]
Address offset: 0x0A8
Device address 1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R DEVICEADDR 48 bit device address
DEVICEADDR[0] contains the least significant bits of the device
address. DEVICEADDR[1] contains the most significant bits of
the device address. Only bits [15:0] of DEVICEADDR[1] are used.
12.1.16 INFO.PART
Address offset: 0x100
Part code
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0x00052840 0 0000000000001010010100001000000
Id RW Field Value Id Value Description
A R PART Part code
N52840 0x52840 nRF52840
Unspecified 0xFFFFFFFF Unspecified
12.1.17 INFO.VARIANT
Address offset: 0x104
Part variant (hardware version and production configuration)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R VARIANT Part variant (hardware version and production configuration).
Encoded as ASCII.
AAAA 0x41414141 AAAA
AAAB 0x41414142 AAAB
AABA 0x41414241 AABA
AABB 0x41414242 AABB
AAB0 0x41414230 AAB0
ABBA 0x41424241 ABBA
Unspecified 0xFFFFFFFF Unspecified
12.1.18 INFO.PACKAGE
Address offset: 0x108
Package option
12 FICR — Factory information configuration
registers
Page 38
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R PACKAGE Package option
QI 0x2004 QIxx - 73-pin aQFN
Unspecified 0xFFFFFFFF Unspecified
12.1.19 INFO.RAM
Address offset: 0x10C
RAM variant
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R RAM RAM variant
K16 0x10 16 kByte RAM
K32 0x20 32 kByte RAM
K64 0x40 64 kByte RAM
K128 0x80 128 kByte RAM
K256 0x100 256 kByte RAM
Unspecified 0xFFFFFFFF Unspecified
12.1.20 INFO.FLASH
Address offset: 0x110
Flash variant
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R FLASH Flash variant
K128 0x80 128 kByte FLASH
K256 0x100 256 kByte FLASH
K512 0x200 512 kByte FLASH
K1024 0x400 1 MByte FLASH
K2048 0x800 2 MByte FLASH
Unspecified 0xFFFFFFFF Unspecified
12.1.21 TEMP.A0
Address offset: 0x404
Slope definition A0
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0xFFFFF320 1 1111111111111111111001100100000
Id RW Field Value Id Value Description
A R A A (slope definition) register.
12.1.22 TEMP.A1
Address offset: 0x408
Slope definition A1
12 FICR — Factory information configuration
registers
Page 39
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0xFFFFF343 1 1111111111111111111001101000011
Id RW Field Value Id Value Description
A R A A (slope definition) register.
12.1.23 TEMP.A2
Address offset: 0x40C
Slope definition A2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0xFFFFF35D 1 1111111111111111111001101011101
Id RW Field Value Id Value Description
A R A A (slope definition) register.
12.1.24 TEMP.A3
Address offset: 0x410
Slope definition A3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0xFFFFF400 1 1111111111111111111010000000000
Id RW Field Value Id Value Description
A R A A (slope definition) register.
12.1.25 TEMP.A4
Address offset: 0x414
Slope definition A4
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0xFFFFF452 1 1111111111111111111010001010010
Id RW Field Value Id Value Description
A R A A (slope definition) register.
12.1.26 TEMP.A5
Address offset: 0x418
Slope definition A5
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAA
Reset 0xFFFFF37B 1 1111111111111111111001101111011
Id RW Field Value Id Value Description
A R A A (slope definition) register.
12.1.27 TEMP.B0
Address offset: 0x41C
Y-intercept B0
12 FICR — Factory information configuration
registers
Page 40
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0xFFFF3FCC 1 1111111111111110011111111001100
Id RW Field Value Id Value Description
A R B B (y-intercept)
12.1.28 TEMP.B1
Address offset: 0x420
Y-intercept B1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0xFFFF3F98 1 1111111111111110011111110011000
Id RW Field Value Id Value Description
A R B B (y-intercept)
12.1.29 TEMP.B2
Address offset: 0x424
Y-intercept B2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0xFFFF3F98 1 1111111111111110011111110011000
Id RW Field Value Id Value Description
A R B B (y-intercept)
12.1.30 TEMP.B3
Address offset: 0x428
Y-intercept B3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0xFFFF0012 1 1111111111111110000000000010010
Id RW Field Value Id Value Description
A R B B (y-intercept)
12.1.31 TEMP.B4
Address offset: 0x42C
Y-intercept B4
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0xFFFF004D 1 1111111111111110000000001001101
Id RW Field Value Id Value Description
A R B B (y-intercept)
12.1.32 TEMP.B5
Address offset: 0x430
Y-intercept B5
12 FICR — Factory information configuration
registers
Page 41
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAAAAAAAA
Reset 0xFFFF3E10 1 1111111111111110011111000010000
Id RW Field Value Id Value Description
A R B B (y-intercept)
12.1.33 TEMP.T0
Address offset: 0x434
Segment end T0
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0xFFFFFFE2 1 1111111111111111111111111100010
Id RW Field Value Id Value Description
A R T T (segment end) register
12.1.34 TEMP.T1
Address offset: 0x438
Segment end T1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0xFFFFFF00 1 1111111111111111111111100000000
Id RW Field Value Id Value Description
A R T T (segment end) register
12.1.35 TEMP.T2
Address offset: 0x43C
Segment end T2
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0xFFFFFF14 1 1111111111111111111111100010100
Id RW Field Value Id Value Description
A R T T (segment end) register
12.1.36 TEMP.T3
Address offset: 0x440
Segment end T3
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0xFFFFFF19 1 1111111111111111111111100011001
Id RW Field Value Id Value Description
A R T T (segment end) register
12.1.37 TEMP.T4
Address offset: 0x444
Segment end T4
12 FICR — Factory information configuration
registers
Page 42
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0xFFFFFF50 1 1111111111111111111111101010000
Id RW Field Value Id Value Description
A R T T (segment end) register
12.1.38 NFC.TAGHEADER0
Address offset: 0x450
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFF5F 1 1111111111111111111111101011111
Id RW Field Value Id Value Description
A R MFGID Default Manufacturer ID: Nordic Semiconductor ASA has ICM
0x5F
B R UD1 Unique identifier byte 1
C R UD2 Unique identifier byte 2
D R UD3 Unique identifier byte 3
12.1.39 NFC.TAGHEADER1
Address offset: 0x454
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R UD4 Unique identifier byte 4
B R UD5 Unique identifier byte 5
C R UD6 Unique identifier byte 6
D R UD7 Unique identifier byte 7
12.1.40 NFC.TAGHEADER2
Address offset: 0x458
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R UD8 Unique identifier byte 8
B R UD9 Unique identifier byte 9
C R UD10 Unique identifier byte 10
D R UD11 Unique identifier byte 11
12.1.41 NFC.TAGHEADER3
Address offset: 0x45C
Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST,
NFCID1_2ND_LAST and NFCID1_LAST.
12 FICR — Factory information configuration
registers
Page 43
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D D D D D C C C C C C C C B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A R UD12 Unique identifier byte 12
B R UD13 Unique identifier byte 13
C R UD14 Unique identifier byte 14
D R UD15 Unique identifier byte 15
13 UICR — User information configuration
registers
Page 44
13 UICR — User information configuration registers
The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring
user-specific settings.
For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page 28 and
Memory on page 20 chapters.
13.1 Registers
Table 12: Instances
Base address Peripheral Instance Description Configuration
0x10001000 UICR UICR User information configuration
Table 13: Register Overview
Register Offset Description
0x000 Reserved
0x004 Reserved
0x008 Reserved
0x010 Reserved
NRFFW[0] 0x014 Reserved for Nordic firmware design
NRFFW[1] 0x018 Reserved for Nordic firmware design
NRFFW[2] 0x01C Reserved for Nordic firmware design
NRFFW[3] 0x020 Reserved for Nordic firmware design
NRFFW[4] 0x024 Reserved for Nordic firmware design
NRFFW[5] 0x028 Reserved for Nordic firmware design
NRFFW[6] 0x02C Reserved for Nordic firmware design
NRFFW[7] 0x030 Reserved for Nordic firmware design
NRFFW[8] 0x034 Reserved for Nordic firmware design
NRFFW[9] 0x038 Reserved for Nordic firmware design
NRFFW[10] 0x03C Reserved for Nordic firmware design
NRFFW[11] 0x040 Reserved for Nordic firmware design
NRFFW[12] 0x044 Reserved for Nordic firmware design
NRFFW[13] 0x048 Reserved for Nordic firmware design
NRFFW[14] 0x04C Reserved for Nordic firmware design
NRFHW[0] 0x050 Reserved for Nordic hardware design
NRFHW[1] 0x054 Reserved for Nordic hardware design
NRFHW[2] 0x058 Reserved for Nordic hardware design
NRFHW[3] 0x05C Reserved for Nordic hardware design
NRFHW[4] 0x060 Reserved for Nordic hardware design
NRFHW[5] 0x064 Reserved for Nordic hardware design
NRFHW[6] 0x068 Reserved for Nordic hardware design
NRFHW[7] 0x06C Reserved for Nordic hardware design
NRFHW[8] 0x070 Reserved for Nordic hardware design
NRFHW[9] 0x074 Reserved for Nordic hardware design
NRFHW[10] 0x078 Reserved for Nordic hardware design
NRFHW[11] 0x07C Reserved for Nordic hardware design
CUSTOMER[0] 0x080 Reserved for customer
CUSTOMER[1] 0x084 Reserved for customer
CUSTOMER[2] 0x088 Reserved for customer
CUSTOMER[3] 0x08C Reserved for customer
CUSTOMER[4] 0x090 Reserved for customer
CUSTOMER[5] 0x094 Reserved for customer
CUSTOMER[6] 0x098 Reserved for customer
13 UICR — User information configuration
registers
Page 45
Register Offset Description
CUSTOMER[7] 0x09C Reserved for customer
CUSTOMER[8] 0x0A0 Reserved for customer
CUSTOMER[9] 0x0A4 Reserved for customer
CUSTOMER[10] 0x0A8 Reserved for customer
CUSTOMER[11] 0x0AC Reserved for customer
CUSTOMER[12] 0x0B0 Reserved for customer
CUSTOMER[13] 0x0B4 Reserved for customer
CUSTOMER[14] 0x0B8 Reserved for customer
CUSTOMER[15] 0x0BC Reserved for customer
CUSTOMER[16] 0x0C0 Reserved for customer
CUSTOMER[17] 0x0C4 Reserved for customer
CUSTOMER[18] 0x0C8 Reserved for customer
CUSTOMER[19] 0x0CC Reserved for customer
CUSTOMER[20] 0x0D0 Reserved for customer
CUSTOMER[21] 0x0D4 Reserved for customer
CUSTOMER[22] 0x0D8 Reserved for customer
CUSTOMER[23] 0x0DC Reserved for customer
CUSTOMER[24] 0x0E0 Reserved for customer
CUSTOMER[25] 0x0E4 Reserved for customer
CUSTOMER[26] 0x0E8 Reserved for customer
CUSTOMER[27] 0x0EC Reserved for customer
CUSTOMER[28] 0x0F0 Reserved for customer
CUSTOMER[29] 0x0F4 Reserved for customer
CUSTOMER[30] 0x0F8 Reserved for customer
CUSTOMER[31] 0x0FC Reserved for customer
PSELRESET[0] 0x200 Mapping of the nRESET function
PSELRESET[1] 0x204 Mapping of the nRESET function
APPROTECT 0x208 Access port protection
NFCPINS 0x20C Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
DEBUGCTRL 0x210 Processor debug control
EXTSUPPLY 0x300 Enable external circuitry to be supplied from VDD pin. Applicable in high voltage mode only.
REGOUT0 0x304 GPIO reference voltage / external output supply voltage in high voltage mode
13.1.1 NRFFW[0]
Address offset: 0x014
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.2 NRFFW[1]
Address offset: 0x018
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.3 NRFFW[2]
Address offset: 0x01C
13 UICR — User information configuration
registers
Page 46
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.4 NRFFW[3]
Address offset: 0x020
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.5 NRFFW[4]
Address offset: 0x024
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.6 NRFFW[5]
Address offset: 0x028
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.7 NRFFW[6]
Address offset: 0x02C
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.8 NRFFW[7]
Address offset: 0x030
Reserved for Nordic firmware design
13 UICR — User information configuration
registers
Page 47
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.9 NRFFW[8]
Address offset: 0x034
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.10 NRFFW[9]
Address offset: 0x038
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.11 NRFFW[10]
Address offset: 0x03C
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.12 NRFFW[11]
Address offset: 0x040
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.13 NRFFW[12]
Address offset: 0x044
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13 UICR — User information configuration
registers
Page 48
13.1.14 NRFFW[13]
Address offset: 0x048
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.15 NRFFW[14]
Address offset: 0x04C
Reserved for Nordic firmware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFFW Reserved for Nordic firmware design
13.1.16 NRFHW[0]
Address offset: 0x050
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.17 NRFHW[1]
Address offset: 0x054
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.18 NRFHW[2]
Address offset: 0x058
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.19 NRFHW[3]
Address offset: 0x05C
Reserved for Nordic hardware design
13 UICR — User information configuration
registers
Page 49
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.20 NRFHW[4]
Address offset: 0x060
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.21 NRFHW[5]
Address offset: 0x064
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.22 NRFHW[6]
Address offset: 0x068
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.23 NRFHW[7]
Address offset: 0x06C
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.24 NRFHW[8]
Address offset: 0x070
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13 UICR — User information configuration
registers
Page 50
13.1.25 NRFHW[9]
Address offset: 0x074
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.26 NRFHW[10]
Address offset: 0x078
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.27 NRFHW[11]
Address offset: 0x07C
Reserved for Nordic hardware design
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW NRFHW Reserved for Nordic hardware design
13.1.28 CUSTOMER[0]
Address offset: 0x080
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.29 CUSTOMER[1]
Address offset: 0x084
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.30 CUSTOMER[2]
Address offset: 0x088
Reserved for customer
13 UICR — User information configuration
registers
Page 51
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.31 CUSTOMER[3]
Address offset: 0x08C
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.32 CUSTOMER[4]
Address offset: 0x090
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.33 CUSTOMER[5]
Address offset: 0x094
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.34 CUSTOMER[6]
Address offset: 0x098
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.35 CUSTOMER[7]
Address offset: 0x09C
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13 UICR — User information configuration
registers
Page 52
13.1.36 CUSTOMER[8]
Address offset: 0x0A0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.37 CUSTOMER[9]
Address offset: 0x0A4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.38 CUSTOMER[10]
Address offset: 0x0A8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.39 CUSTOMER[11]
Address offset: 0x0AC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.40 CUSTOMER[12]
Address offset: 0x0B0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.41 CUSTOMER[13]
Address offset: 0x0B4
Reserved for customer
13 UICR — User information configuration
registers
Page 53
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.42 CUSTOMER[14]
Address offset: 0x0B8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.43 CUSTOMER[15]
Address offset: 0x0BC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.44 CUSTOMER[16]
Address offset: 0x0C0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.45 CUSTOMER[17]
Address offset: 0x0C4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.46 CUSTOMER[18]
Address offset: 0x0C8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13 UICR — User information configuration
registers
Page 54
13.1.47 CUSTOMER[19]
Address offset: 0x0CC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.48 CUSTOMER[20]
Address offset: 0x0D0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.49 CUSTOMER[21]
Address offset: 0x0D4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.50 CUSTOMER[22]
Address offset: 0x0D8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.51 CUSTOMER[23]
Address offset: 0x0DC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.52 CUSTOMER[24]
Address offset: 0x0E0
Reserved for customer
13 UICR — User information configuration
registers
Page 55
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.53 CUSTOMER[25]
Address offset: 0x0E4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.54 CUSTOMER[26]
Address offset: 0x0E8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.55 CUSTOMER[27]
Address offset: 0x0EC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.56 CUSTOMER[28]
Address offset: 0x0F0
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.57 CUSTOMER[29]
Address offset: 0x0F4
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13 UICR — User information configuration
registers
Page 56
13.1.58 CUSTOMER[30]
Address offset: 0x0F8
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.59 CUSTOMER[31]
Address offset: 0x0FC
Reserved for customer
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CUSTOMER Reserved for customer
13.1.60 PSELRESET[0]
Address offset: 0x200
Mapping of the nRESET function
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If they do not, there
will be no nRESET function exposed on a GPIO, and the device will always start independently of the levels
present on any of the GPIOs.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id C B A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PIN 18 Pin number of PORT onto which nRESET is exposed
B RW PORT 0 Port number onto which nRESET is exposed
C RW CONNECT Connection
Disconnected 1 Disconnect
Connected 0 Connect
13.1.61 PSELRESET[1]
Address offset: 0x204
Mapping of the nRESET function
All PSELRESET registers have to contain the same value for a pin mapping to be valid. If they do not, there
will be no nRESET function exposed on a GPIO, and the device will always start independently of the levels
present on any of the GPIOs.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id C B A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PIN 18 Pin number of PORT onto which nRESET is exposed
B RW PORT 0 Port number onto which nRESET is exposed
C RW CONNECT Connection
Disconnected 1 Disconnect
Connected 0 Connect
13 UICR — User information configuration
registers
Page 57
13.1.62 APPROTECT
Address offset: 0x208
Access port protection
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AAAAAAAA
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PALL Enable or disable access port protection.
See Debug and trace on page 62 for more information.
Disabled 0xFF Disable
Enabled 0x00 Enable
13.1.63 NFCPINS
Address offset: 0x20C
Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW PROTECT Setting of pins dedicated to NFC functionality
Disabled 0 Operation as GPIO pins. Same protection as normal GPIO pins
NFC 1 Operation as NFC antenna pins. Configures the protection for
NFC operation
13.1.64 DEBUGCTRL
Address offset: 0x210
Processor debug control
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id B B B B B B B B A A A A A A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW CPUNIDEN Configure CPU non-intrusive debug features
Enabled 0xFF Enable CPU ITM and ETM functionality (default behavior)
Disabled 0x00 Disable CPU ITM and ETM functionality
B RW CPUFPBEN Configure CPU flash patch and breakpoint (FPB) unit behavior
Enabled 0xFF Enable CPU FPB unit (default behavior)
Disabled 0x00 Disable CPU FPB unit. Writes into the FPB registers will be
ignored.
13.1.65 EXTSUPPLY
Address offset: 0x300
Enable external circuitry to be supplied from VDD pin. Applicable in high voltage mode only.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW EXTSUPPLY Enable external circuitry to be supplied from VDD pin (output of
REG0 stage)
Disabled 0 No current can be drawn from the VDD pin
Enabled 1 It is allowed to supply external circuitry from the VDD pin
13 UICR — User information configuration
registers
Page 58
13.1.66 REGOUT0
Address offset: 0x304
GPIO reference voltage / external output supply voltage in high voltage mode
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A
Reset 0xFFFFFFFF 1 1111111111111111111111111111111
Id RW Field Value Id Value Description
A RW VOUT Output voltage from of REG0 regulator stage. The maximum
output voltage from this stage is given as VDDH - VEXDIF.
1V8 0 1.8 V
2V1 1 2.1 V
2V4 2 2.4 V
2V7 3 2.7 V
3V0 4 3.0 V
3V3 5 3.3 V
DEFAULT 7 Default voltage: 1.8 V
14 Peripheral interface
Page 59
14 Peripheral interface
Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral
events are indicated to the CPU by event registers and interrupts if they are configured for a given event.
Peripheral
core
TASK
OR
Task signal from PPI
write
task
event
EVENT m
IRQ signal to NVIC
INTEN m
Peripheral
SHORTSk
Event signal to PPI
Figure 8: Tasks, events, shortcuts, and interrupts
14.1 Peripheral ID
Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit
registers.
See Instantiation on page 23 for more information about which peripherals are available and where they are
located in the address map.
There is a direct relationship between the peripheral ID and base address. For example, a peripheral with
base address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1,
and a peripheral with base address 0x4001F000 is assigned ID=31.
Peripherals may share the same ID, which may impose one or more of the following limitations:
Some peripherals share some registers or other common resources.
Operation is mutually exclusive. Only one of the peripherals can be used at a time.
Switching from one peripheral to another must follow a specific pattern (disable the first, then enable the
second peripheral).
14.2 Peripherals with shared ID
In general (with the exception of ID 0), peripherals sharing an ID and base address may not be used
simultaneously. The user can only enable one peripheral at the time on this specific ID.
14 Peripheral interface
Page 60
When switching between two peripherals that share an ID, the user should do the following to prevent
unwanted behavior:
Disable the previously used peripheral.
Remove any programmable peripheral interconnect (PPI) connections set up for the peripheral that is
being disabled.
Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF.
Explicitly configure the peripheral that you enable and do not rely on configuration values that may be
inherited from the peripheral that was disabled.
Enable the now configured peripheral.
See Instantiation on page 23 to see which peripherals are sharing ID.
14.3 Peripheral registers
Most peripherals feature an ENABLE register. Unless otherwise specified in the relevant chapter, the
peripheral registers (in particular the PSEL registers) must be configured before enabling the peripheral.
Note that the peripheral must be enabled before tasks and events can be used.
14.4 Bit set and clear
Registers with multiple single-bit bit fields may implement the set-and-clear pattern. This pattern enables
firmware to set and clear individual bits in a register without having to perform a read-modify-write operation
on the main register.
This pattern is implemented using three consecutive addresses in the register map, where the main register
is followed by dedicated SET and CLR registers (in that exact order).
The SET register is used to set individual bits in the main register while the CLR register is used to clear
individual bits in the main register. Writing 1 to a bit in the SET or CLR register will set or clear the same bit
in the main register respectively. Writing 0 to a bit in the SET or CLR register has no effect. Reading the SET
or CLR registers returns the value of the main register.
Restriction: The main register may not be visible and hence not directly accessible in all cases.
14.5 Tasks
Tasks are used to trigger actions in a peripheral, for example to start a particular behavior. A peripheral can
implement multiple tasks with each task having a separate register in that peripheral's task register group.
A task is triggered when firmware writes 1 to the task register or when the peripheral itself or another
peripheral toggles the corresponding task signal. See Figure 8: Tasks, events, shortcuts, and interrupts on
page 59.
14.6 Events
Events are used to notify peripherals and the CPU about events that have happened, for example a state
change in a peripheral. A peripheral may generate multiple events with each event having a separate
register in that peripheral’s event register group.
An event is generated when the peripheral itself toggles the corresponding event signal, and the event
register is updated to reflect that the event has been generated. See Figure 8: Tasks, events, shortcuts, and
interrupts on page 59. An event register is only cleared when firmware writes 0 to it.
Events can be generated by the peripheral even when the event register is set to 1.
14 Peripheral interface
Page 61
14.7 Shortcuts
A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is
enabled, its associated task is automatically triggered when its associated event is generated.
Using a shortcut is the equivalent to making the same connection outside the peripheral and through the
PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay
through the PPI.
Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut
can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a maximum
of 32 shortcuts for each peripheral.
14.8 Interrupts
All peripherals support interrupts. Interrupts are generated by events.
A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example, the
peripheral with ID=4 is connected to interrupt number 4 in the nested vectored interrupt controller (NVIC).
Using the INTEN, INTENSET and INTENCLR registers, every event generated by a peripheral can be
configured to generate that peripheral's interrupt. Multiple events can be enabled to generate interrupts
simultaneously. To resolve the correct interrupt source, the event registers in the event group of peripheral
registers will indicate the source.
Some peripherals implement only INTENSET and INTENCLR, and the INTEN register is not available
on those peripherals. Refer to the individual chapters for details. In all cases, however, reading back the
INTENSET or INTENCLR register returns the same information as in INTEN.
Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET
and INTENCLR registers.
The relationship between tasks, events, shortcuts, and interrupts is shown in Figure 8: Tasks, events,
shortcuts, and interrupts on page 59.
14.8.1 Interrupt clearing
When clearing an interrupt by writing 0 to an event register, or disabling an interrupt using the INTENCLR
register, it can take up to four CPU clock cycles to take effect. This means that an interrupt may reoccur
immediatelly even if a new event has not come, if the program exits an interrupt handler after the interrupt is
cleared or disabled, but before four clock cycles have passed.
Important: To avoid an interrupt reoccurring before a new event has come, the program should
perform a read from one of the peripheral registers, for example, the event register that has been
cleared, or the INTENCLR register that has been used to disable the interrupt.
This will cause a one to three-cycle delay and ensure the interrupt is cleared before exiting the interrupt
handler. Care should be taken to ensure the compiler does not remove the read operation as an
optimization. If the program can guarantee a four-cycle delay after event clear or interrupt disable another
way, then a read of a register is not required.
15 Debug and trace
Page 62
15 Debug and trace
The debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging.
DAP
CPU
ARM Cortex-M4
SWDCLK
SWDIO
SW-DP
POWER
CxxxPWRUPREQ
CxxxPWRUPRACK
Power
External
debugger
Peripherals
RAM & flash
APB/AHB
AHB
AHB-AP
DAP bus
interconnect
APPROTECT.PALL
CTRL-AP
UICR
NVMC
ETM
ITM
TPIU
Trace
TraceTRACEDATA[3]
TRACEDATA[2]
TRACEDATA[1]
TRACEDATA[0] / SWO
TRACECLK
Figure 9: Overview
The main features of the debug and trace system are:
Two-pin serial wire debug (SWD) interface
Flash patch and breakpoint unit (FPB) supports:
Two literal comparators
Six instruction comparators
Data watchpoint and trace unit (DWT)
Four comparators
Instrumentation trace macrocell (ITM)
Embedded trace macrocell (ETM)
Trace port interface unit (TPIU)
4-bit parallel trace of ITM and ETM trace data
Serial wire output (SWO) trace of ITM data
15.1 DAP - Debug access port
An external debugger can access the device via the DAP.
The DAP implements a standard ARM® CoreSight SW-DP (serial wire debug port).
The SW-DP implements the SWD (serial wire debug) protocol that is a two-pin serial interface, see SWDCLK
and SWDIO in Debug and trace on page 62.
In addition to the default access port in the CPU (AHB-AP), the DAP includes a custom control access port
(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port on page 63.
Important:
The SWDIO line has an internal pull-up resistor.
The SWDCLK line has an internal pull-down resistor.
15 Debug and trace
Page 63
15.2 CTRL-AP - Control access port
The control access port (CTRL-AP) is a custom access port that enables control of the device even if the
other access ports in the DAP are being disabled by the access port protection.
Access port protection blocks the debugger from read and write access to all CPU registers and memory-
mapped addresses. See the UICR register APPROTECT on page 57 for more information about enabling
access port protection.
This access port enables the following features:
Soft reset, see Reset on page 73 for more information
Disable access port protection
Access port protection can only be disabled by issuing an ERASEALL command via CTRL-AP. This
command will erase flash, UICR, and RAM.
15.2.1 Registers
Table 14: Register Overview
Register Offset Description
RESET 0x000 Soft reset triggered through CTRL-AP
ERASEALL 0x004 Erase all
ERASEALLSTATUS 0x008 Status register for the ERASEALL operation
APPROTECTSTATUS 0x00C Status register for access port protection
IDR 0x0FC CTRL-AP identification register, IDR
RESET
Address offset: 0x000
Soft reset triggered through CTRL-AP
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A RW RESET Soft reset triggered through CTRL-AP. See Reset behaviour in
POWER chapter for more details.
NoReset 0 Reset is not active
Reset 1 Reset is active. Device is held in reset.
ERASEALL
Address offset: 0x004
Erase all
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A W ERASEALL Erase all flash and RAM
NoOperation 0 No operation
Erase 1 Erase all flash and RAM
ERASEALLSTATUS
Address offset: 0x008
Status register for the ERASEALL operation
15 Debug and trace
Page 64
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A R ERASEALLSTATUS Status register for the ERASEALL operation
Ready 0 ERASEALL is ready
Busy 1 ERASEALL is busy (on-going)
APPROTECTSTATUS
Address offset: 0x00C
Status register for access port protection
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0x00000000 0 0000000000000000000000000000000
Id RW Field Value Id Value Description
A R APPROTECTSTATUS Status register for access port protection
Enabled 0 Access port protection enabled
Disabled 1 Access port protection not enabled
IDR
Address offset: 0x0FC
CTRL-AP identification register, IDR
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id E E E E D D D D C C C C C C C B B B B A A A A A A A A
Reset 0x02880000 0 0000010100010000000000000000000
Id RW Field Value Id Value Description
A R APID AP identification
B R CLASS Access port (AP) class
NotDefined 0x0 No defined class
MEMAP 0x8 Memory access port
C R JEP106ID JEDEC JEP106 identity code
D R JEP106CONT JEDEC JEP106 continuation code
E R REVISION Revision
15.2.2 Electrical specification
Control access port
Symbol Description Min. Typ. Max. Units
Rpull Internal SWDIO and SWDCLK pull up/down resistance 13
15.3 Debug interface mode
Before the external debugger can access the CPU's access port (AHB-AP) or the control access port (CTRL-
AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.
As long as the debugger is requesting power via CxxxPWRUPREQ, the device will be in debug interface
mode. If the debugger is not requesting power via CxxxPWRUPREQ, the device will be in normal mode.
Some peripherals will behave differently in debug interface mode compared to normal mode. These
differences are described in more detail in the chapters of the peripherals that are affected.
When a debug session is over, the external debugger must make sure to put the device back into normal
mode since the overall power consumption will be higher in debug interface mode compared to normal
mode.
For details on how to use the debug capabilities please read the debug documentation of your IDE.
15 Debug and trace
Page 65
If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and
the DIF flag in RESETREAS on page 77 will be set.
15.4 Real-time debug
The nRF52840 supports real-time debugging.
Real-time debugging will allow interrupts to execute to completion in real time when breakpoints are set
in thread mode or lower priority interrupts. This enables the developer to set a breakpoint and single-step
through their code without a failure of the real-time event-driven threads running at higher priority. For
example, this enables the device to continue to service the high-priority interrupts of an external controller or
sensor without failure or loss of state synchronization while the developer steps through code in a low-priority
thread.
15.5 Trace
The device supports ETM and ITM trace.
Trace data from the ETM and the ITM is sent to an external debugger via a 4-bit wide parallel trace port
(TPIU), see TRACEDATA[0] through TRACEDATA[3] and TRACECLK in Figure 9: Overview on page 62.
In addition to parallel trace, the TPIU supports serial trace via the serial wire output (SWO) trace protocol.
Parallel and serial trace cannot be used at the same time.
ETM trace is only supported in parallel trace mode, while ITM trace is supported in both parallel and serial
trace modes. For details on how to use the trace capabilities, please read the debug documentation of your
IDE.
TPIU's trace pins are multiplexed with GPIOs, and SWO and TRACEDATA[0] use the same GPIO, see Pin
assignments on page 13 for more information. The speed of the trace pins depends on the drive setting of
the GPIOs that the trace pins are multiplexed with. Trace speed is configured in the TRACECONFIG on
page 149 register.
Only S0S1 and H0H1 drives are suitable for debugging. S0S1 is the default drive at reset. If parallel or serial
trace port signals are not fast enough in the debugging conditions, all GPIOs in use for tracing should be set
to high drive (H0H1). The user must make sure that these GPIOs' drive is not overwritten by software during
the debugging session.
15.5.1 Electrical specification
Trace port
Symbol Description Min. Typ. Max. Units
Tcyc Clock period, as defined by ARM (See ARM Infocenter,
Embedded Trace Macrocell Architecture Specification, Trace
Port Physical Interface, Timing specifications)
62.5 500 ns
16 POWER — Power supply
Page 66
16 POWER — Power supply
The power supply consists of a number of LDO and DC/DC regulators that are utilized to maximize the
system's power efficiency.
This device has the following power supply features:
On-chip LDO and DC/DC regulators
Global System ON/OFF modes
Individual RAM section power control for all system modes
Analog or digital pin wakeup from System OFF
Supervisor HW to manage power-on reset, brownout, and power fail
Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency
External circuitry supply
Separate USB supply
16.1 Main supply
The main supply voltage is connected to VDD/VDDH pins. The system will enter one of two supply voltage
modes, normal or high voltage mode, depending on how the supply voltage is connected to these pins.
Normal voltage mode is entered when the supply voltage is connected to both the VDD and VDDH pins (so
that VDD equals VDDH).
High voltage mode is entered when the supply voltage is only connected to the VDDH pin and the VDD pin is
not connected to any voltage supply.
The MAINREGSTATUS on page 81 register can be used for reading out the current supply voltage
mode.
For the supply voltage range of the two supply voltage modes, see Regulator operating conditions on page
138.
16.1.1 Main voltage regulators
The system contains two main supply regulator stages, REG0 and REG1.
Each of the regulator stages have the following regulator type options:
Low-dropout regulator (LDO)
Buck regulator (DC/DC)
In normal voltage mode, only the REG1 regulator stage is used and the REG0 stage is automatically
disabled. In high voltage mode, both regulator stages (REG0 and REG1) are used. The output voltage of
REG0 can be configured in register REGOUT0 on page 58 listed in UICR — User information configuration
registers on page 44. This output voltage is connected to VDD and is the input voltage to REG1.
By default, the LDO regulators are enabled and the DC/DC regulators are disabled. Registers DCDCEN0
on page 81 and DCDCEN on page 80 are used to independently enable the DC/DC regulators for the
two stages (REG0 and REG1 respectively).
When a DC/DC converter is enabled, the LDO for the corresponding regulator stage will be disabled.
External LC filters must be connected for each of the DC/DC regulators being used. The advantage of using
a DC/DC regulator is that the overall power consumption is normally reduced as the efficiency of such a
regulator is higher than that of a LDO. The efficiency benefit of using a DC/DC regulator becomes particularly
prominent at high dropout voltage (between the input voltage and the output voltage). The efficiency of
internal regulators vary with the supply voltage and the current drawn from the regulators.
Important: Do not enable DCDC regulator without an external LC filter being connected as this will
inhibit device operation, including debug access, until an LC filter is connected.
16 POWER — Power supply
Page 67
16.1.2 GPIO levels
The GPIO high reference voltage always equals the level on the VDD pin.
In normal voltage mode, the GPIO high level equals the voltage supplied to the VDD pin, and in high voltage
mode it equals the level specified in the register REGOUT0 on page 58 listed in UICR — User information
configuration registers on page 44.
16.1.3 External circuitry supply
In high voltage mode, the output from REG0 can be used to supply external circuitry from the VDD pin.
Before any current can be drawn from the VDD pin, this feature must be enabled in the EXTSUPPLY on
page 57 UICR register.
The VDD output voltage is configured in the REGOUT0 on page 58 UICR register.
The supported output voltage range depends on the supply voltage provided on the VDDH pin. Minimum
difference between voltage supplied on the VDDH pin and the voltage output on the VDD pin is defined by
VEXDIF parameter in Regulator operating conditions on page 138.
Supplying external circuitry is allowed in both System OFF and System ON mode.
Important: When in System OFF mode, 1 mA is the maximum current draw allowed by external
circuitry (as defined by the IEX,OFF parameter in Regulator operating conditions on page 138).
16.1.4 Regulator configuration examples
The voltage regulators can be configured in several ways, depending on the selected supply voltage mode
(normal/high) and the regulator type option (LDO or DC/DC).
Four configuration examples are illustrated in images below.
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC
1.3V System power
Supply
Figure 10: Normal voltage mode, LDO only
16 POWER — Power supply
Page 68
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC
1.3V System power
Supply
Figure 11: Normal voltage mode, DC/DC REG1 enabled
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC
1.3V System power
Supply
REGOUT0
Figure 12: High voltage mode, LDO only
16 POWER — Power supply
Page 69
Main supply
REG0
LDO
DC/DC
REG1
LDO
DC/DC
REGOUT0DCDCEN0 DCDCEN
DCCH VDD DCC GND
VDDH
DEC
1.3V System power
Supply
REGOUT0
Figure 13: High voltage mode, DC/DC for REG0 and REG1 enabled
16.1.5 Power supply supervisor
The power supply supervisor enables monitoring of the connected power supply.
The power supply supervisor provides:
Power-on reset, signalling to the circuit when a supply is connected.
An optional power-fail comparator (POF), to signal the application when the supply voltages drop below a
configured threshold.
A fixed brownout reset detector, to hold the system in reset when the voltage is too low for safe operation.
The power supply supervisor is illustrated in Figure 14: Power supply supervisor on page 70. To enable
and configure the power-fail comparator, see the register POFCON on page 79.
16 POWER — Power supply
Page 70
POFCON.POF
MUX VPOF
...........
MUX
2.8 V
1.8 V
1.7 V
4.2 V
...........
2.8 V
2.8 V
VDD
VDDH
VPOFH
POFWARN
VBOR
Brownout reset
Power-on reset
C
R
VDD
POFCON.THRESHOLD
POFCON.POF
(VDDH>VDD)
POFCON.THRESHOLDVDDH
Figure 14: Power supply supervisor
16 POWER — Power supply
Page 71
16.1.6 Power-fail comparator
Using the power-fail comparator (POF) is optional. When enabled, it can provide the CPU with an early
warning of an impending power supply failure.
To enable and configure the power-fail comparator, see the register POFCON on page 79.
The threshold (VPOF) must be configured to a suitable level. When the supply voltage falls below the
defined threshold, the power-fail comparator will generate an event (POFWARN) which can be used by an
application to prepare for power failure. This event will also be generated if the supply voltage is already
below the threshold at the time the power-fail comparator is enabled, or if the threshold is re-configured to a
level above the supply voltage.
If the power-fail warning is enabled and the supply voltage is below the threshold, the power-fail comparator
will prevent the NVMC from performing write operations to the NVM.
The comparator features a hysteresis of VHYST, as illustrated in Figure 15: Power-fail comparator (BOR =
brownout reset) on page 71.
VDD
t
MCU
POFWARN
VPOF
VPOF+VHYST
POFWARN
1.7V
BOR
Figure 15: Power-fail comparator (BOR = brownout reset)
To save power, the power-fail comparator is not active in System OFF or in System ON when HFCLK is not
running.
16.2 USB supply
When using the USB peripheral, a 5 V USB supply needs to be provided on the VBUS pin.
The USB peripheral has a dedicated internal voltage regulator for converting the VBUS supply to 3.3 V used
by the USB signalling interface (D+ and D- lines, and pull-up on D+). The rest of the USB peripheral (USBD)
is supplied through the main supply like any other on-chip feature. As a consequence, both VBUS and either
VDDH or VDD supplies are required for USB peripheral operation.
When VBUS rises into its valid range, the software is notified through a USBDETECTED event. A
USBREMOVED event is sent when VBUS goes below its valid range. Use these events to implement the
USBD start-up sequence described in the USBD chapter.
When VBUS rises into its valid range while the device is in System OFF, the device resets and transitions to
System ON mode. The RESETREAS register will have the VBUS bit set to indicate the source of the wake-
up.
See VBUS detection specifications on page 140 for the levels at which the events are sent (VBUS,DETECT
and VBUS,REMOVE) or at which the system is woken up from System OFF ( VBUS,DETECT).
16 POWER — Power supply
Page 72
When the USBD peripheral is enabled through the ENABLE register and VBUS is detected, the regulator
is turned on. A USBPWRRDY event is sent when the regulator's worst case settling time has elapsed,
indicating to the software that it can enable the USB pull-up to signal a USB connection to the host.
The software can read the state of the VBUS detection and regulator output readiness at any time through the
USBREGSTATUS register.
USB supply
LDO
VBUS
DECUSB
3.3 V USB power
5 V USB
supply
Figure 16: USB voltage regulator
To ensure stability, the input and output of the USB regulator need to be decoupled with a suitable
decoupling capacitor. See Reference circuitry on page 688 for the recommended values.
16.3 System OFF mode
System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core
functionality is powered down and all ongoing tasks are terminated.
The device can be put into System OFF mode using the POWER register interface. When in System OFF
mode, the device can be woken up through one of the following signals:
1. The DETECT signal, optionally generated by the GPIO peripheral.
2. The ANADETECT signal, optionally generated by the LPCOMP module.
3. The SENSE signal, optionally generated by the NFC module to wake-on-field.
4. Detecting a valid USB voltage on the VBUS pin (VBUS,DETECT).
5. A reset.
The system is reset when it wakes up from the System OFF mode.
One or more RAM sections can be retained in System OFF mode, depending on the settings in the
RAM[n].POWER registers. RAM[n].POWER are retained registers. Note that these registers are usually
overwritten by the start-up code provided with the nRF application examples.
Before entering the System OFF mode, the user must make sure that all on-going EasyDMA transactions
have been completed. See peripheral specific chapters for more information about how to acquire the status
of EasyDMA transactions.
16 POWER — Power supply
Page 73
16.3.1 Emulated System OFF mode
If the device is in debug interface mode, System OFF will be emulated to secure that all required resources
needed for debugging are available during System OFF.
See Debug and trace on page 62 for more information. Required resources needed for debugging include
the following key components: Debug and trace on page 62, CLOCK — Clock control on page 141,
POWER — Power supply on page 66, NVMC — Non-volatile memory controller on page 28, CPU, flash,
and RAM. Since the CPU is kept on in an emulated System OFF mode, it is recommended to add an infinite
loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be
executed.
16.4 System ON mode
System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or
peripherals, can be in IDLE or RUN mode, depending on the configuration set by the software and the state
of the application executing.
Register RESETREAS on page 77 provides information about the source causing the wakeup or reset.
The system can switch the appropriate internal power sources on and off , depending on how much power
is needed at any given time. The power requirement of a peripheral is directly related to its activity level, and
the activity level of a peripheral is usually raised and lowered when specific tasks are triggered or events are
generated.
16.4.1 Sub power modes
In System ON mode, when both the CPU and all the peripherals are in IDLE mode, the system can reside in
one of the two sub power modes.
The sub power modes are:
Constant latency
Low power
In constant latency mode, the CPU wakeup latency and the PPI task response are constant and kept at
a minimum. This is secured by forcing a set of basic resources to be turned on while in sleep. Having a
constant and predictable latency is at cost of having increased power consumption. The constant latency
mode is selected by triggering the CONSTLAT task.
In low power mode, the automatic power management system described in System ON mode on page
73 ensures that the most efficient supply option is chosen to save most power. Having the lowest power
possible is at cost of having a varying CPU wakeup latency and PPI task response. The low power mode is
selected by triggering the LOWPWR task.
When the system enters System ON mode, it is by default in low power sub power mode.
16.5 RAM power control
RAM power control is used for RAM retention in System OFF mode and for powering down unused sections
in System ON mode.
Each RAM section can power up and down independently in both System ON and System OFF mode. See
chapter Memory on page 20 for more information on RAM sections.
RAM sections can be retained in System OFF mode, depending on the settings in the RAM[n].POWER
registers. RAM[n].POWER are retained registers.
16.6 Reset
Several sources may trigger a reset.