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The Simplified Diagram shows three states of operation:
the start, run and regulate mode. Previous surge stopper
parts are powered off the input supply, therefore the surge
voltage is limited to the breakdown voltage of the input pins
of the part. As demonstrated in run and regulate modes,
the majority of this part is powered off the output, so the
MOSFET isolates the surge from the power pins of the
part. This allows surge voltages up to the breakdown of
the external MOSFET.
In the start mode a 15µA trickle current flows through RIN,
half is used to charge the gate with the other half used as
bias current. As the GATE pin charges, the external MOSFET
brings up the OUT pin. This leads to the run mode where
the output is high enough to become a supply voltage for
the charge pump. The charge pump is then used to fully
charge the gate 12V above the source.
With the output voltage equal to the input voltage, it is
necessary to protect the load from an input supply over-
voltage. In the regulate mode, the overvoltage regulation
amplifier is referenced to the output through a 1.23V
reference. If the voltage drop across the upper feedback
resistor, RFB1, exceeds 1.23V the regulation amplifier pulls
the gate down to regulate the RFB1 voltage back to 1.23V.
Therefore, the output voltage is clamped by setting the
proper ratio between RFB1 and RFB2.
For example, if the output voltage is regulated at 100V then
the voltage drop across the RFB2 is 98.77V. If the Zener Z3
is 5.7V then the voltage drop across RSS is 94.3V. There-
fore, when the output is at a high voltage, the majority of
the voltage is dropped across the two resistors RFB2 and
RSS. This demonstrates how the LTC4366 floats up with
the supply. The adjustable 3-terminal regulators, such
as the LT
1085 and LM117, are also based on this idea.
The Functional Diagram shows the actual circuits. An
external RIN resistor on the VDD pin powers up the 12V
shunt regulator which then powers up logic supply, VCC.
After verifying that the shutdown input is not active, the
GATE pin is charged with a 7.5µA current from VDD. This
is the start mode.
Once the OUT to VSS voltage exceeds the 2.55V UVLO1
threshold, the overvoltage amplifier is enabled. Next, the
UVLO2 threshold of 4.75V is crossed and the charge pump
turns on. The charge pump charges the GATE pin with
20µA to its final value 12V above OUT (clamped by Z4).
This allows the capacitor between OUT and VSS to charge
until clamped by Z3 to 5.7V. In this run mode the MOSFET
is configured as a low resistance pass transistor with little
voltage drop and power dissipation in the MOSFET.
The powered up LTC4366 is now ready to protect the load
against an overvoltage transient. The overvoltage regula-
tion amplifier monitors the load voltage between OUT and
ground by sensing the voltage on the FB pin with respect
to the OUT pin (drop across RFB1). In an overvoltage
condition the OUT rises until the amplifier drives the M1
gate to regulate and limit the output voltage. This is the
During regulation the excess voltage is dropped across the
MOSFET. To prevent overheating the MOSFET, the LTC4366
limits the overvoltage regulation time using the TIMER pin.
The TIMER pin is charged with 9µA until the pin exceeds
2.8V. At that point an overvoltage fault is set, the MOSFET
is turned off, and the part enters a cool-down period of
9 seconds. The logic and timer block are active during
cool down while the GATE pin is pulled to OUT.
The latched-off version, LTC4366-1, will remain in fault
until the SD pin is toggled low and then high. Once the fault
is cleared, the GATE is permitted to turn the MOSFET on
again. The auto-retry version, LTC4366-2, waits 9 seconds
then clears the fault and restarts.