JPY | USD

LTM4613 Datasheet

Linear Technology/Analog Devices

Download PDF Datasheet

Datasheet

LTM4613
1
4613fd
For more information www.linear.com/LTM4613
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
FCB
MARG0
MARG1
MPGM
VOUT
VFB
VIN
0.1µF
10µF
× 3
22pF COUT
VOUT
12V
8A
CIN
VIN
24V
TO 36V PLLIN
CLOCK SYNC
LTM4613
SGND
VD
PGND
MARGIN
CONTROL
51k
5.23k
392k
5% MARGIN
4613 TA01
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
EN55022B Compliant
36VIN, 15VOUT, 8A,
DC/DC
µ
Module Regulator
The LT M
®
4613 is a complete, ultralow noise, 8A switch
mode DC/DC power supply. Included in the package are the
switching controller, power FETs, inductor and all support
components. Operating over an input voltage range of 5V
to 36V, the LTM4613 supports an output voltage range of
3.3V to 15V, set by a single external resistor. Only bulk
input and output capacitors are needed to finish the design.
High switching frequency and an adaptive on-time current
mode architecture enables a very fast transient response
to line and load changes without sacrificing stability.
The onboard input filter and noise cancellation circuits
achieve low noise coupling, thus effectively reducing
the electromagnetic interference (EMI)—see Figure 7.
Furthermore, the DC/DC µModule
®
regulator can be syn-
chronized with an external clock to reduce undesirable
frequency harmonics and allow PolyPhase
®
operation for
high load currents.
The LTM4613
is offered in 15mm × 15mm × 4.32mm
LGA and 15mm × 15mm × 4.92mm BGA packages. The
LTM4613 is available with SnPb (BGA) or RoHS compli-
ant terminal finish.
12V/8A Ultralow Noise µModule with 24V to 36V Input
n Complete Low EMI Switch Mode Power Supply
n EN55022 Class B Compliant
n Wide Input Voltage Range: 5V to 36V
n 8A Output Current
n 3.3V to 15V Output Voltage Range
n Low Input and Output Referred Noise
n Output Voltage Tracking and Margining
n PLL Frequency Synchronization
n 2% Maximum Total DC Error
n Power Good Tracks with Margining
n Current Foldback Protection
n Parallel/Current Sharing
n Ultrafast Transient Response
n Current Mode Control
n Programmable Soft-Start
n Output Overvoltage Protection
n –55°C to 125°C Operating Temperature Range
(LTM4613MPV, LTM4613MPY)
n 15mm × 15mm × 4.32mm LGA and
15mm × 15mm × 4.92mm BGA Packages
n SnPb (BGA) or RoHS Compliant (LGA and BGA) Finish
n Telecom and Networking Equipment
n Industrial and Avionic Equipment
n RF Systems
Radiated Emission Scan with 24VIN to 12VOUT at 8A
L, LT, LTC, LT M , µModule, PolyPhase, Linear Technology, and the Linear logo are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
70
60
50
40
30
SIGNAL AMPLITUDE (dB uV/m)
20
10
0
30 226.2 422.4 613.6
FREQUENCY (MHz)
4613 TA01b
814.3
1010.0
–10
EN55022B LIMIT
LTM4613
2
4613fd
For more information www.linear.com/LTM4613
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
INTVCC, DRVCC ............................................. 0.3V to 6V
VOUT ........................................................... 0.3V to 16V
PLLIN, FCB, TRACK/SS, MPGM, MARG0,
MARG1, PGOOD ....................0.3V to INTVCC + 0.3V
RUN .............................................................0.3V to 5V
VFB, COMP ................................................ 0.3V to 2.7V
(Note 1)
MARG1
DRVCC
VFB
PGOOD
SGND
NC
NC
NC
FCB
VIN
BANK 1 VD
PGND
BANK 2
VOUT
BANK 3
fSET
MARG0
RUN
COMP
MPGM
PLLIN
INTVCC
VD
TRACK/SS
LGA PACKAGE
133-LEAD (15mm × 15mm × 4.32mm)
TOP VIEW
SGND
1221 43 5 6 98 10 117
A
B
C
D
E
F
G
H
J
K
L
M
TJMAX = 125°C, θJCtop = 17°C/w, θJCbottom = 2.3°C/W, θJA = 10°C/W, θJB = 2.5°C/W,
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
WEIGHT = 2.5g
MARG1
DRVCC
VFB
PGOOD
SGND
NC
NC
NC
FCB
VIN
BANK 1 VD
PGND
BANK 2
VOUT
BANK 3
fSET
MARG0
RUN
COMP
MPGM
PLLIN
INTVCC
VD
TRACK/SS
BGA PACKAGE
133-LEAD (15mm × 15mm × 4.92mm)
TOP VIEW
SGND
1221 43 5 6 98 10 117
A
B
C
D
E
F
G
H
J
K
L
M
TJMAX = 125°C, θJCtop = 17°C/w, θJCbottom = 2.3°C/W, θJA = 10°C/W, θJB = 2.5°C/W,
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
WEIGHT = 2.7g
PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
DEVICE FINISH CODE
LTM4613EV#PBF Au (RoHS) LTM4613V e4 LGA 3 –40°C to 125°C
LTM4613IV#PBF Au (RoHS) LTM4613V e4 LGA 3 –40°C to 125°C
LTM4613MPV#PBF Au (RoHS) LTM4613V e4 LGA 3 –55°C to 125°C
LTM4613EY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 –40°C to 125°C
LTM4613IY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 –40°C to 125°C
LTM4613IY SnPb (63/37) LTM4613Y e0 BGA 3 –40°C to 125°C
LTM4613MPY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 –55°C to 125°C
LTM4613MPY SnPb (63/37) LTM4613Y e0 BGA 3 –55°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
Terminal Finish Part Marking: www.linear.com/leadfree
Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures: www.linear.com/umodule/pcbassembly
LGA and BGA Package and Tray Drawings: www.linear.com/packaging
VIN, VD .......................................................0.3V to 36V
Internal Operating Temperature Range (Note 2)
E- and I-Grades .................................. 40°C to 125°C
MP-Grade .......................................... 55°C to 125°C
Storage Temperature Range .................. 55°C to 125°C
Peak Solder Reflow Package Body Temperature ..... 245°C
ORDER INFORMATION
http://www.linear.com/product/LTM4613#orderinfo
LTM4613
3
4613fd
For more information www.linear.com/LTM4613
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 24V, unless otherwise noted. Per Typical
Application (front page) configuration.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN(DC) Input DC Voltage l5 36 V
VOUT(DC) Output Voltage, Total Variation
with Line and Load
CIN = 10µF × 3, COUT = 47µF × 4; FCB = 0,
VIN = 24V to 36V, VOUT = 12V
l11.83 12.07 12.31 V
Input Specifications
VIN(UVLO) Undervoltage Lockout Threshold IOUT = 0A 3.2 4.8 V
IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A; CIN = 10µF × 3, COUT = 47µF × 4; CSS = 22nF
VOUT = 12V
VIN = 24V
VIN = 36V
150
120
mA
mA
IQ(VIN) Input Supply Bias Current VIN = 36V, VOUT = 12V, Switching Continuous, IOUT = 0A
VIN = 24V, VOUT = 12V, Switching Continuous, IOUT = 0A
Shutdown, RUN = 0, VIN = 36V
78
60
50
mA
mA
µA
IS(VIN) Input Supply Current VIN = 36V, VOUT = 12V, IOUT = 8A
VIN = 24V, VOUT = 12V, IOUT = 8A
2.90
4.26
A
A
VINTVCC Internal VCC Voltage VIN = 36V, RUN > 2V, IOUT = 0A 4.7 5 5.5 V
Output Specifications
IOUT(DC) Output Continuous Current Range VIN = 24V, VOUT = 12V (Note 4) 0 8 A
VOUT(LINE)
VOUT
Line Regulation Accuracy VOUT = 12V, FCB = 0V, VIN = 24V to 36V,
IOUT = 0A
l
0.05
0.3
%
∆VOUT(LOAD)
VOUT
Load Regulation Accuracy VOUT = 12V, FCB = 0V, IOUT = 0A to 8A (Note 4)
VIN = 36V
VIN = 24V
l
l
0.5
0.5
0.75
0.75
%
%
VIN(AC) Input Ripple Voltage IOUT = 0A,
CIN = 1 × 10µF X5R Ceramic and 1 × 100µF Electrolytic,
3 × 10µF X5R Ceramic on VD Pins
VIN = 24V, VOUT = 12V (Note 5)
10
mVP-P
VOUT(AC) Output Ripple Voltage IOUT = 0A,
COUT = 1 × 10µF, 4 × 47µF X5R Ceramic
VIN = 24V, VOUT = 12V
19
mVP-P
fSOutput Ripple Voltage Frequency VIN = 24V, VOUT = 12V, IOUT = 0A 600 kHz
∆VOUT(START) Turn-On Overshoot COUT = 47µF × 4, VOUT = 12V, IOUT = 0A, CSS = 22nF
VIN = 36V
VIN = 24V
20
20
mV
mV
tSTART Turn-On Time COUT = 47µF × 4, VOUT = 12V, IOUT = 0A, CSS = Open
VIN = 36V
VIN = 24V
0.3
0.3
ms
ms
∆VOUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load
COUT = 1 × 10µF, 3 × 47µF X5R Ceramic, 1 × 47µF POSCAP
VIN = 24V, VOUT = 12V
250
mV
tSETTLE Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load
COUT = 1 × 10µF, 3 × 47µF X5R Ceramic, 1 × 47µF POSCAP
VIN = 24V, VOUT = 12V
100 µs
IOUT(PK) Output Current Limit COUT = 47µF × 4
VIN = 36V, VOUT = 12V
VIN = 24V, VOUT = 12V
12
12
A
A
LTM4613
4
4613fd
For more information www.linear.com/LTM4613
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4613 is tested under pulsed load conditions such that
TJ ≈ TA. The LTM4613E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4613I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. The LTM4613MP
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Control Section
VFB Voltage at VFB Pin IOUT = 0A, VOUT = 12V l0.591 0.6 0.609 V
VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V
ITRACK/SS Soft-Start Charging Current VTRACK/SS = 0V –1 –1.5 –2 µA
VFCB Forced Continuous Threshold 0.57 0.6 0.63 V
IFCB Forced Continuous Pin Current VFCB = 0V –1 –2 µA
tON(MIN) Minimum On-Time (Note 3) 50 100 ns
tOFF(MIN) Minimum Off-Time (Note 3) 250 400 ns
RPLLIN PLLIN Input Resistor 50
IDRVCC Current into DRVCC Pin VOUT = 12V, IOUT = 0A, DRVCC = 5V 22 30 mA
RFBHI Resistor Between VOUT and VFB
Pins
99.5 100 100.5
VMPGM Margin Reference Voltage 1.18 V
VMARG0,
VMARG1
MARG0, MARG1 Voltage
Thresholds
1.4 V
PGOOD
∆VFBH PGOOD Upper Threshold VFB Rising 7 10 13 %
∆VFBL PGOOD Lower Threshold VFB Falling –7 –10 –13 %
∆VFB(HYS) PGOOD Hysteresis VFB Returning 1.5 %
VPGL PGOOD Low Voltage IPGOOD = 5mA 0.2 0.4 V
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 24V, unless otherwise noted. Per Typical
Application (front page) configuration.
is guaranteed and tested over the full –55°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 3: 100% tested at die level only.
Note 4: See the Output Current Derating curves for different VIN, VOUT
and TA.
Note 5: Guaranteed by design.
LTM4613
5
4613fd
For more information www.linear.com/LTM4613
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current with
3.3VOUT (FCB = 0)
Efficiency vs Load Current with
5VOUT (FCB = 0)
Efficiency vs Load Current with
12VOUT (FCB = 0)
Efficiency vs Load Current with
15VOUT (FCB = 0)
Transient Response from 12VIN
to 3.3VOUT
Transient Response from 12VIN
to 5VOUT
Transient Response from 24VIN
to 12VOUT
Start-Up with 24VIN to 12VOUT
at IOUT = 0A
Start-Up with 24VIN to 12VOUT at
IOUT = 8A
(Refer to Figure 18)
LOAD CURRENT (A)
0
EFFICIENCY (%)
80
90
8
4613 G01
70
60 246
1357
100
75
85
65
95
5VIN, 3.3VOUT
12VIN, 3.3VOUT
24VIN, 3.3VOUT
36VIN, 3.3VOUT
LOAD CURRENT (A)
0
EFFICIENCY (%)
80
90
8
4613 G02
70
60 246
1357
100
75
85
65
95
12VIN, 5VOUT
24VIN, 5VOUT
36VIN, 5VOUT
LOAD CURRENT (A)
0
EFFICIENCY (%)
80
90
8
4613 G03
70
60 246
1357
100
75
85
65
95
20VIN, 12VOUT
24VIN, 12VOUT
28VIN, 12VOUT
36VIN, 12VOUT
LOAD CURRENT (A)
0
EFFICIENCY (%)
80
90
8
4613 G04
70
60 246
1357
100
75
85
65
95
24VIN, 15VOUT
28VIN, 15VOUT
32VIN, 15VOUT
36VIN, 15VOUT
IOUT
5A/DIV
VOUT
100mV/DIV
AC
100µs/DIV
LOAD STEP: 0A TO 4A
COUT = 1 × 47µF POSCAP
1 × 10µF CERAMIC CAPACITOR AND
3 × 47µF CERAMIC CAPACITORS
4613 G05
IOUT
5A/DIV
VOUT
100mV/DIV
AC
100µs/DIV
LOAD STEP: 0A TO 4A
COUT = 1 × 47µF POSCAP
1 × 10µF CERAMIC CAPACITOR AND
3
×
47µF CERAMIC CAPACITORS
4613 G06
IOUT
5A/DIV
VOUT
200mV/DIV
AC
100µs/DIV
LOAD STEP: 0A TO 4A
COUT = 1 × 47µF POSCAP
1 × 10µF CERAMIC CAPACITOR AND
3
×
47µF CERAMIC CAPACITORS
4613 G07
IIN
200mA/DIV
VOUT
5V/DIV
10ms/DIV
SOFT-START CAPACITOR: 0.1µF
CIN = 2 × 10µF CERAMIC CAPACITORS AND
1
×
100µF OS-CON CAPACITOR
4613 G08
IIN
VOUT
10ms/DIV
SOFT-START CAPACITOR: 0.1µF
CIN = 2 × 10µF CERAMIC CAPACITORS AND
1
100µF OS-CON CAPACITOR
LTM4613
6
4613fd
For more information www.linear.com/LTM4613
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with 24VIN to 12VOUT at
IOUT = 8A, TA = –55°C
Short-Circuit with 24VIN to 12VOUT
at IOUT = 0A
Short-Circuit with 24VIN to 12VOUT
at IOUT = 8A
VIN to VOUT Step-Down Ratio
Input Ripple
Output Ripple
VIN
100mV/DIV
AC
1µs/DIV
VIN = 24V
VOUT = 12V AT 8A RESISTIVE LOAD
CIN = 2 × 10µF CERAMIC CAPACITORS AND
1
×
100µF OS-CON CAPACITOR
4613 G14
VOUT
10mV/DIV
AC
1µs/DIV
VIN = 24V
VOUT = 12V AT 8A RESISTIVE LOAD
COUT = 1 × 47µF POSCAP
1 × 10µF CERAMIC CAPACITOR AND
3 × 47µF CERAMIC CAPACITORS
4613 G15
IOUT
2A/DIV
VOUT
5V/DIV
20ms/DIV
4613 G10
SOFT-START CAPACITOR: 0.1µF
CIN = 2 × 10µF CERAMIC CAPACITORS AND
1 × 100µF OS-CON CAPACITOR
IIN
500mA/DIV
VOUT
5V/DIV
20µs/DIV
4613 G11
COUT = 1 × 47µF POSCAP,
1 × 10µF CERAMIC CAPACITORS
AND 3 × 47µF CERAMIC CAPACITORS
IIN
VOUT
20µs/DIV
COUT = 1 × 47µF POSCAP,
1 × 10µF CERAMIC CAPACITORS
OUTPUT VOLTAGE (V)
3.3
0
INPUT VOLTAGE (V)
6
12
18
24
36
57 9 11
4613 G13
13 15
30
LTM4613
7
4613fd
For more information www.linear.com/LTM4613
PIN FUNCTIONS
VIN (Bank 1): Power Input Pins. Apply input voltage be-
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between VIN pins
and PGND pins.
PGND (Bank 2): Power Ground Pins for Both Input and
Output Returns.
VOUT (Bank 3): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins (see the LTM4613 Pin Configuration below).
VD (Pins C1 to C7, B6 to B7, A6): Top FET Drain Pins.
Add more high frequency ceramic decoupling capacitors
between VD and PGND to handle the input RMS current
and reduce the input ripple further.
DRVCC (Pins C10, E11, E12): These pins normally connect
to INTVCC for powering the internal MOSFET drivers. They
can be biased up to 6V from an external supply with about
50mA capability. This improves efficiency at the higher
input voltages by reducing power dissipation in the module.
See the Applications Information section.
INTVCC (Pin A7): This pin is for additional decoupling of
the 5V internal regulator.
PLLIN (Pin A8): External Clock Synchronization Input to the
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor. Apply a clock above 2V and below
INTVCC subject to minimum on-time and minimum off-time
requirements. See the Applications Information section.
FCB (Pin M12): Forced Continuous Input. Connect this pin
to SGND to force continuous synchronization operation
at light load or to INTVCC to enable discontinuous mode
operation at light load.
TRACK/SS (Pin A9): Output Voltage Tracking and Soft-Start
Pin. When the module is configured as a master output,
then a soft-start capacitor is placed on this pin to ground
to control the master ramp rate. A soft-start capacitor can
be used for soft-start turn-on as a standalone regulator.
Slave operation is performed by putting a resistor divider
from the master output to the ground, and connecting the
center point of the divider to this pin. See the Applications
Information section.
MPGM (Pins A12, B11): Programmable Margining In-
put. A resistor from these pins to ground sets a current
that is equal to 1.18V/R. This current multiplied by 10k
will equal a value in millivolts that is a percentage of the
0.6V reference voltage. Leave floating if margining is not
used. See the Applications Information section. To parallel
LTM4613s, each requires an individual MPGM resistor.
Do not tie MPGM pins together.
fSET (Pin B12): Frequency Set Internally to 600kHz at 12V
Output. An external resistor can be placed from this pin
to ground to increase frequency or from this pin to VIN
to reduce frequency. See the Applications Information
section for frequency adjustment.
LTM4613 Pin Configuration
(See Package Description for Pin Assignments)
MARG1
DRVCC
VFB
PGOOD
SGND
NC
NC
NC
FCB
VIN
BANK 1 VD
PGND
BANK 2
VOUT
BANK 3
fSET
MARG0
RUN
COMP
MPGM
PLLIN
INTVCC
VD
TRACK/SS
LGA PACKAGE
133-LEAD (15mm × 15mm × 4.32mm)
TOP VIEW
SGND
1221 43 5 6 98 10 117
A
B
C
D
E
F
G
H
J
K
L
M
LTM4613
8
4613fd
For more information www.linear.com/LTM4613
VFB (Pin F12): The Negative Input of the Error Ampli-
fier. Internally, this pin is connected to VOUT with a 100k
0.5% precision resistor. Different output voltages can be
programmed with an additional resistor between the VFB
and SGND pins. See the Applications Information section.
MARG0 (Pin C12): LSB Logic Input for the Margining
Function. Together with the MARG1 pin, the MARG0 pin
will determine if a margin high, margin low, or no margin
state is applied. The pin has an internal pull-down resistor
of 50k. See the Applications Information section.
MARG1 (Pins C11, D12): MSB Logic Input for the Margin-
ing Function. Together with the MARG0 pin, the MARG1
pin will determine if a margin high, margin low, or no
margin state is applied. The pins have an internal pull-down
resistor of 50k. See the Applications Information section.
SGND (Pins D9, H12): Signal Ground Pins. These pins
connect to PGND at output capacitor point.
COMP (Pins A11, D11): Current Control Threshold and
Error Amplifier Compensation Point. The current com-
parator threshold increases with this control voltage. The
voltage ranges from 0V to 2.4V with 0.7V corresponding
to zero sense voltage (zero current).
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±10% of the regulation point,
after a 25µs power bad mask timer expires.
RUN (Pins A10, B9): Run Control Pins. A voltage above
1.9V will turn on the module, and below 1V will turn off
the module. A programmable UVLO function can be ac-
complished with a resistor from VIN to this pin that has a
5.1V Zener to ground. Maximum pin voltage is 5V.
MTP (Pins J12, K12, L12): No Connect Pins. Leave float-
ing. Used for mounting to PCB.
PIN FUNCTIONS
LTM4613
9
4613fd
For more information www.linear.com/LTM4613
BLOCK DIAGRAM
DECOUPLING REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CIN External Input Capacitor Requirement
(VIN = 24V to 36V, VOUT = 12V)
IOUT = 8A 30 100 µF
COUT External Output Capacitor Requirement
(VIN = 24V to 36V, VOUT = 12V)
IOUT = 8A 100 220 µF
Specifications are at TA = 25°C. Use Figure 1 configuration.
+
INTERNAL
COMP
SGND
COMP
PGOOD
RUN
> 1.9V = ON
< 1V = OFF
MAX = 5V
MARG1
MARG0
MPGM
FCB
PLLIN
CSS
INTVCC
DRVCC
TRACK/SS
VFB
fSET
50k
133k
RFB
5.23k
50k
100k
VOUT
5.1V
ZENER
POWER CONTROL M1
VIN
24V TO 36V
VD
VOUT
12V
AT 8A
M2
50k
10µF
F CIN
+
COUT
PGND
4613 F01
10k
4.7µF
2.2µH
INPUT
FILTER
NOISE
CANCEL-
LATION
10µF
50V
× 3
RA
RB
= SGND
= PGND
UVLO
FUNCTION
VIN
Figure 1. Simplified Block Diagram
LTM4613
10
4613fd
For more information www.linear.com/LTM4613
OPERATION
Power Module Description
The LTM4613 is a standalone nonisolated switch mode
DC/DC power supply. It can deliver 8A of DC output cur-
rent with minimal external input and output capacitors.
This module provides a precisely regulated output voltage
programmable via one external resistor from 3.3VDC to
15VDC over a wide 5V to 36V input voltage. The typical
application schematic is shown in Figure 18.
The LTM4613 has an integrated constant on-time current
mode regulator, ultralow RDS(ON) FETs with fast switching
speed and integrated Schottky diodes. The typical switching
frequency is 600kHz at full load at 12V output. With current
mode control and internal feedback loop compensation,
the LTM4613 module has sufficient stability margins and
good transient performance under a wide range of operat-
ing conditions and with a wide range of output capacitors,
even all ceramic output capacitors.
Current mode control provides cycle-by-cycle fast current
limiting. Moreover, foldback current limiting is provided in
an overcurrent condition when VFB drops. Internal over-
voltage and undervoltage comparators pull the open-drain
PGOOD output low if the output feedback voltage exits a
±10% window around the regulation point. Furthermore,
in an overvoltage condition, internal top FET M1 is turned
off and bottom FET M2 is turned on and held on until the
overvoltage condition clears.
Input filter and noise cancellation circuitry reduce the
noise coupling to inputs and outputs, and ensure the
electromagnetic interference (EMI) meets the limits of
EN55022 Class B (see Figure 7).
Pulling the RUN pin below 1V forces the controller into
its shutdown state, turning off both M1 and M2. At light
load currents, discontinuous mode (DCM) operation can
be enabled to achieve higher efficiency compared to con-
tinuous mode (CCM) by setting FCB pin higher than 0.6V.
When the DRVCC pin is connected to INTVCC, an integrated
5V linear regulator powers the internal gate drivers. If a
5V external bias supply is applied on DRVCC pin, then an
efficiency improvement will occur due to the reduced power
loss in the internal linear regulator. This is especially true
at the higher input voltage range.
The MPGM, MARG0, and MARG1 pins are used to sup-
port voltage margining, where the percentage of margin
is programmed by the MPGM pin, while the MARG0 and
MARG1 select positive or negative margining. The PLLIN
pin provides frequency synchronization of the device to
an external clock. The TRACK/SS pin is used for power
supply tracking and soft-start programming.
The typical LTM4613 application circuit is shown in Fig-
ure18. External component selection is primarily deter-
mined by the input voltage, the maximum load current and
the output voltage. Refer to Table 2 for specific external
capacitor requirements for a particular application.
VIN to VOUT Step-Down Ratios
There are restrictions in the maximum VIN and VOUT step
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
Characteristic curve labeled “VIN to VOUT Step-Down
Ratio.” Note that additional thermal derating may be ap-
plied. See the Thermal Considerations and Output Current
Derating section in this data sheet.
APPLICATIONS INFORMATION
Output Voltage Programming and Margining
The PWM controller has an internal 0.6V reference volt-
age. As shown in the Block Diagram, a 100k 0.5% internal
feedback resistor connects the VOUT and VFB pins together.
Adding a resistor, RFB, from the VFB pin to the SGND pin
programs the output voltage.
VOUT =0.6V •
100k
+
R
FB
RFB
or equivalently,
RFB =
100k
VOUT
0.6V
1
LTM4613
11
4613fd
For more information www.linear.com/LTM4613
APPLICATIONS INFORMATION
Figure 2. Operating Frequency vs Output Voltage
Operating Frequency
The operating frequency of the LTM4613 is optimized to
achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
As shown in Figure 2, the frequency is linearly increased
with larger output voltages to keep the low output cur-
rent ripple. Figure 3 shows the inductor current ripple ∆I
with different output voltages. In most applications, no
additional frequency adjusting is required.
If lower output ripple is required, the operating frequency
f can be increased by adding a resistor RfSET between fSET
pin and SGND, as shown in Figure 19.
f=
V
OUT
1.51010 R
fSET
||133k
( )
[Hz]
Figure 3. Pk-Pk Inductor Current Ripple vs Output Voltage
Table 1. RFB Standard 1% Resistor Values vs VOUT
VOUT (V) 3.3 5 6 8 10 12 14 15
RFB (kΩ) 22.1 13.7 11.0 8.06 6.34 5.23 4.42 4.12
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference ±
offset for margining. A 1.18V reference divided by the
RPGM resistor on the MPGM pin programs the current.
Calculate VOUT(MARGIN):
VOUT(MARGIN) =
%V
OUT
100
• VOUT
Where %VOUT is the percentage of VOUT to be margined,
and VOUT(MARGIN) is the margin quantity in volts:
RPGM =
V
OUT
0.6V
1.18V
VOUT(MARGIN)
10k
Where RPGM is the resistor value to place on the MPGM
pin to ground.
The margining voltage, VOUT(MARGIN), will be added or
subtracted from the nominal output voltage as determined
by the state of the MARG0 and MARG1 pins. See the truth
table below:
MARG1 MARG0 MODE
LOW LOW NO MARGIN
LOW HIGH MARGIN UP
HIGH LOW MARGIN DOWN
HIGH HIGH NO MARGIN
Parallel Operation
The LTM4613 device is an inherently current mode con-
trolled device. This allows the paralleled modules to have
very good current sharing and balanced thermals on the
design. Figure 21 shows a schematic of the parallel design.
The voltage feedback equation changes with the variable
N as modules are paralleled:
RFB =
100k
N
VOUT
0.6V
1
where N is the number of paralleled modules.
OUTPUT VOLTAGE (V)
2 4
0
FREQUENCY (kHz)
400
1000
610 12
4613 F02
200
800
600
814 16
OUTPUT VOLTAGE (V)
2
0
PK-PK INDUCTOR CURRENT RIPPLE (A)
1
3
4
5
10
9
4613 F03
2
6
412 14
8 16
6
7
8
VIN = 16V
VIN = 24V
VIN = 28V
VIN = 36V
LTM4613
12
4613fd
For more information www.linear.com/LTM4613
APPLICATIONS INFORMATION
For output voltages more than 12V, the frequency can
be higher than 600kHz, thus reducing the efficiency sig-
nificantly. Additionally, the minimum off-time of 400ns
normally limits the operation when the input voltage is
close to the output voltage. Therefore, it is recommended
to lower the frequency in these conditions by connecting
a resistor (RfSET) from the fSET pin to VIN as shown in
Figure 20, where:
f=
V
OUT
51011 3RfSET 133k
RfSET 2133k
[Hz]
The load current can affect the frequency due to its con-
stant on-time control. If constant frequency is a necessity,
the PLLIN pin can be used to synchronize the frequency
of the LTM4613 to an external clock subject to minimum
on-time and off-time limits, as shown in Figures 21 to 23.
Input Capacitors
LTM4613 is designed to achieve low input conducted
EMI noise due to the fast switching of turn-on and turn-
off. Additionally, a high-frequency inductor is integrated
into the input line for noise attenuation. VD and VIN pins
are available for external input capacitors to form a high
frequency π filter. As shown in Figure 18, the ceramic
capacitors, C1-C3, on the VD pins are used to handle most
of the RMS current into the converter, so careful attention
is needed for capacitors C1-C3 selection.
For a buck converter, the switching duty cycle can be
estimated as:
D=
V
OUT
VIN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
ICIN(RMS) =
I
OUT(MAX)
η
D 1D
( )
In this equation,
η
is the estimated efficiency of the
power module. Note the capacitor ripple current ratings
are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
In a typical 8A output application, three very low ESR,
X5R or X7R, 10µF ceramic capacitors are recommended
for C1-C3. This decoupling capacitance should be placed
directly adjacent to the module VD pins in the PCB layout
to minimize the trace inductance and high frequency AC
noise. Each 10µF ceramic is typically good for 2A of RMS
ripple current. Refer to your ceramics capacitor catalog
for the RMS current ratings.
To attenuate the high frequency noise, extra input capacitors
should be connected to the VIN pads and placed before the
high frequency inductor to form the π filter. One of these
low ESR ceramic input capacitors is recommended to be
close to the connection into the system board. A large bulk
100µF capacitor is only needed if the input source imped-
ance is compromised by long inductive leads or traces.
Output Capacitors
The LTM4613 is designed for low output voltage ripple.
The bulk output capacitors defined as COUT are chosen with
low enough effective series resistance (ESR) to meet the
output voltage ripple and transient requirements. COUT can
be low ESR tantalum capacitor, low ESR polymer capaci-
tor or ceramic capacitor. The typical capacitance is 4 ×
47µF if all ceramic output capacitors are used. Additional
output filtering may be required by the system designer
if further reduction of output ripple or dynamic transient
spikes is required. Table 2 shows a matrix of different
output voltages and output capacitors to minimize the
voltage droop and overshoot during a 4A load transient.
The table optimizes total equivalent ESR and total bulk
capacitance to maximize transient performance.
Multiphase operation with multiple LTM4613 devices in
parallel will also lower the effective output ripple current
due to the phase interleaving operation. Refer to Figure 4
for the normalized output ripple current versus the duty
cycle. Figure 4 provides a ratio of peak-to-peak output
ripple current to the inductor ripple current as functions of
duty cycle and the number of paralleled phases. Pick the
corresponding duty cycle and the number of phases to get
the correct output ripple current value. For example, each
LTM4613
13
4613fd
For more information www.linear.com/LTM4613
APPLICATIONS INFORMATION
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 19)
TYPICAL MEASURED VALUES
VENDORS PART NUMBER VENDORS PART NUMBER
Murata GRM32ER61C476KEI5L (47µF, 16V) Murata GRM32ER71H106K (10µF, 50V)
Murata GRM32ER61C226KE20L (22µF, 16V) TDK C3225X5RIC226M (22µF, 16V)
Figure 4. Normalized Output Ripple Current vs Duty Cycle, ∆IL = VOT/LI
DUTY CYCLE (VO/VIN)
0.1 0.15 0.2 0.25 0.350.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
4612 F04
6-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
PEAK-TO-PEAK OUTPUT RIPPLE CURRENT
∆IL
RATIO =
VOUT
(V)
CIN
(CERAMIC)
CIN
(BULK)
COUT1
(CERAMIC) COUT2 (BULK)
VIN
(V)
DROOP
(mV)
PK-TO-PK
(mV)
RECOVERY
TIME (µs)
LOAD
STEP (A)
LOAD STEP
SLEW RATE
(A/µS)
RFB
(kΩ)
3.3 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 5 84 175 50 4 10 22.1
3.3 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 5 91 181 40 4 10 22.1
3.3 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 12 100 188 50 4 10 22.1
3.3 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 12 100 191 40 4 10 22.1
3.3 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 24 113 200 50 4 10 22.1
3.3 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 24 103 197 40 4 10 22.1
5 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 12 109 222 60 4 10 13.7
5 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 12 122 238 50 4 10 13.7
5 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 24 119 228 60 4 10 13.7
5 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 24 122 238 50 4 10 13.7
5 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 36 125 231 60 4 10 13.7
5 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 36 128 247 50 4 10 13.7
12 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 24 178 363 150 4 10 5.23
12 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 24 238 488 90 4 10 5.23
12 2 × 10µF 50V 100µF 50V 2 × 22µF 16V 150µF 16V 36 181 369 150 4 10 5.23
12 2 × 10µF 50V 100µF 50V 4 × 47µF 16V None 36 244 500 90 4 10 5.23
LTM4613
14
4613fd
For more information www.linear.com/LTM4613
APPLICATIONS INFORMATION
phases inductor ripple current IL is ~5.0A for a 36V to 12V
design. The duty cycle is about 0.33. The 2-phase curve
shows a ratio of ~0.33 for a duty cycle of 0.33. This 0.33
ratio of output ripple current to the inductor ripple current
∆IL at 5.0A equals 1.65A of output ripple current (∆IO).
The output voltage ripple has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
The equation is:
VOUT(PP) IO
8 • f •NC
OUT
+ESRIO
N
where f is the frequency and N is the number of paralleled
phases. This calculation process can be easily accom-
plished by using LTpowerCAD™.
Fault Conditions: Current Limit and
Overcurrent Foldback
LTM4613 has a current mode controller, which inherently
limits the cycle-by-cycle inductor current not only in steady
state operation, but also in response to transients.
To further limit current in the event of an overload condi-
tion, the LTM4613 provides foldback current limiting. If the
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to about one sixth
of its full current limit value.
Soft-Start and Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on this pin will program the ramp rate of the
output voltage. A 1.5µA current source will charge up the
external soft-start capacitor to 80% of the 0.6V internal
voltage reference plus or minus any margin delta. This will
control the ramp of the internal reference and the output
voltage. The total soft-start time can be calculated as:
tSOFTSTART 0.8 0.6V ±VOUT(MARGIN)
( )
CSS
1.5µA
If the RUN pin falls below 1.5V, then the TRACK/SS pin
is reset to allow for proper soft-start control when the
regulator is enabled again. Current foldback and forced
continuous mode are disabled during the soft-start pro-
cess. The soft-start function can also be used to control
the output ramp rise time, so that another regulator can
be easily tracked to it.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. Figure 5 shows an ex-
ample of coincident tracking where the master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulators feedback divider.
Ratiometric modes of tracking can be achieved by select-
ing different resistor values to change the output tracking
ratio. The master output must be greater than the slave
output for coincident tracking to work. Figure 6 shows the
coincident output tracking characteristics.
Figure 5. Coincident Tracking Schematic
Figure 6. Coincident Output Tracking Characteristics
PGOOD
RUN
COMP
INTVCC
DRVCC
TRACK/SS
fSET
VOUT
VFB
FCB
MARG0
MARG1
MPGM
TRACK
CONTROL
PLLIN
LTM4613
RFB
5.23k
51k
MASTER
OUTPUT R2
100k
COUT
SLAVE
OUTPUT
4613 F05
CIN
VIN
VD
PGNDSGND
V
IN
R1
5.23k
10µF
×3
OUTPUT
VOLTAGE
TIME 4613 F06
MASTER OUTPUT
SLAVE OUTPUT
LTM4613
15
4613fd
For more information www.linear.com/LTM4613
APPLICATIONS INFORMATION
Ratiometric tracking can be achieved by a few simple cal-
culations and the slew rate value applied to the master’s
TRACK/SS pin. The TRACK/SS pin has a control range
from 0 to 0.6V. The master’s TRACK/SS pin slew rate is
directly equal to the master’s output slew rate in Volts/
Time. The equation:
MR
SR
100k =R2
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R2 is
equal to 100k. R1 is derived from equation:
R1=
0.6V
VFB
100k +VFB
RFB
VTRACK
R2
where VFB is the feedback voltage reference of the regula-
tor, and VTRACK is 0.6V. Since R2 is equal to the 100k top
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R1 is equal to RFB with VFB =
VTRACK. Therefore R2 = 100k, and R1 = 5.23k in Figure 5.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. R2 can be solved for when SR is
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach its final value before the master output.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
R2 = 125k. Solve for R1 to equal 5.18k.
Each of the TRACK/SS pins will have the 1.5µA current
source on when a resistive divider is used to implement
tracking on that specific channel. This will impose an offset
on the TRACK/SS pin input. Smaller values resistors with
the same ratios as the resistor values calculated from
the above equation can be used. For example, where the
100k is used then a 10k value can be used to reduce the
TRACK/SS pin offset to a negligible value.
RUN Enable
The RUN pin is used to enable the power module. The
pin has an internal 5.1V Zener to ground. The pin can be
driven with 5V logic levels.
The RUN pin can also be used as an undervoltage lockout
(UVLO) function by connecting a resistor divider from
the input supply to the RUN pin. The equation for UVLO
threshold:
VUVLO =
R
A+
R
B
RB
1.5V
where RA is the top resistor, and RB is the bottom resistor.
Refer to Figure 1, Simplified Block Diagram.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point and tracks
with margining.
COMP Pin
This pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. LTpowerCAD is available for other control loop
optimization.
FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when in-
ductor current reverses. FCB pin below the 0.6V threshold
forces continuous synchronous operation, allowing current
to reverse at light loads and maintaining high frequency
operation.
PLLIN Pin
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of an external clock. The
external clock frequency range must be within ±30%
around the set operating frequency. A pulse detection
circuit is used to detect a clock on the PLLIN pin to turn
on the phase-locked loop. The pulse width of the clock
has to be at least 400ns. The clock high level must be
above 2V and clock low level below 0.3V. The PLLIN pin
LTM4613
16
4613fd
For more information www.linear.com/LTM4613
APPLICATIONS INFORMATION
must be driven from a low impedance source such as a
logic gate located close to the pin. During the start-up of
the regulator, the phase-locked loop function is disabled.
INTVCC and DRVCC Connection
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRVCC
for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4613
can be directly powered by VIN. The gate driver current
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
PLDO_LOSS = 20mA • (VIN – 5V)
The LTM4613 also provides the external gate driver voltage
pin DRVCC. If there is a 5V rail in the system, it is recom-
mended to connect the DRVCC pin to the external 5V rail.
This is especially true for higher input voltages. Do not
apply more than 6V to the DRVCC pin.
Radiated EMI Noise
High radiated EMI noise is a disadvantage for switching
regulators by nature. Fast switching turn-on and turn-off
make the large di/dt change in the converters, which act
as the radiation sources in most systems. LTM4613 inte-
grates the feature to minimize the radiated EMI noise for
applications with low noise requirements. An optimized
gate driver for the MOSFET and a noise cancellation
network are installed inside the LTM4613 to achieve the
low radiated EMI noise. Figure 7 shows a typical example
for the LTM4613 to meet the EN55022 Class B radiated
emission limit.
Thermal Considerations and Output Current Derating
In different applications, LTM4613 operates in a variety
of thermal environments. The maximum output current is
limited by the environment thermal condition. Sufficient
cooling should be provided to help ensure reliable opera-
tion. When the cooling is limited, proper output current
derating is necessary, considering ambient temperature,
airflow, input/output condition, and the need for increased
reliability.
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-12. They are intended for use
with finite element analysis (FEA) software modeling tools
that leverage the outcome of thermal modeling, simula-
tion and correlation to hardware evaluation performed on
a µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD51-12, Guidelines for Reporting and Using
Electronic Package Thermal Information.”
Many designers may opt to use laboratory equipment
and a test vehicle, such as the demo board, to predict
the µModule regulator’s thermal performance in their
Figure 7. Radiated Emission Scan with 24VIN to
12VOUT at 8A Measured in 10 Meter Chamber
70
60
50
40
30
SIGNAL AMPLITUDE (dB uV/m)
20
10
0
30 226.2 422.4 613.6
FREQUENCY (MHz) 4613 F07
814.3
1010.0
–10
EN55022B LIMIT
LTM4613
17
4613fd
For more information www.linear.com/LTM4613
application at various electrical and environmental
operating conditions to compliment any FEA activities.
Without FEA software, the thermal resistances reported
in the Pin Configuration section are, in and of themselves,
not relevant to providing guidance of thermal performance.
Instead, the derating curves provided in the data sheet
can be used in a manner that yields insight and guidance
pertaining to one’s application-usage, and can be adapted
to correlate thermal performance to ones own application.
The Pin Configuration section gives four thermal coeffi-
cients, explicitly defined in JESD51-12. These coefficients
are quoted or paraphrased below:
θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with 4 layers.
θJCbottom, the thermal resistance from the junction
to the bottom of the product case, is determined
with all of the component power dissipation flowing
through the bottom of the package. In the typical
µModule regulator, the bulk of the heat flows out of
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages, but the test conditions do not generally
match the users application.
θJCtop, the thermal resistance from the junction to the
top of the product case, is determined with nearly all of
the component power dissipation flowing through the
top of the package. As the electrical connections of the
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages, but the test conditions do not
generally match the user’s application.
θJB, the thermal resistance from the junction to the
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule regulator and into the board.
It is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package.
A graphical representation of the aforementioned thermal
resistances is given in Figure 8. Blue resistances are
contained within the µModule package, whereas green
resistances are external to the µModule package.
Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients
APPLICATIONS INFORMATION
µModule REGULATOR
4613 F08
JUNCTION
AMBIENT
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-BOARD RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
JUNCTION-TO-CASE (BOTTOM)
RESISTANCE
LTM4613
18
4613fd
For more information www.linear.com/LTM4613
As a practical matter, it should be clear to the reader that
no individual or subgroup of the four thermal resistance
parameters defined by JESD51-12, or provided in the
Pin Configuration section, replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
of the package—as the standard defines for θJCtop and
θJCbottom, respectively. In practice, power loss is thermally
dissipated in both directions away from the package.
Granted, in the absence of a heat sink and airflow, the
majority of the heat flow is into the board.
Within the LTM4613, be aware that there are multiple
power devices and components dissipating power, with
a consequence that the thermal resistances relative to
different junctions of components or die are not exactly
linear with respect to total package power loss. To reconcile
this complication without sacrificing modeling simplic-
itybut also, not ignoring practical realitiesan approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet:
1. Initially, FEA software is used to accurately build the
mechanical geometry of the LTM4613 and the specified
PCB with all of the correct material coefficients, along
with accurate power loss source definitions.
2. This model simulates a software-defined JEDEC envi-
ronment consistent with JESD51-12 to predict power
loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-
defined thermal resistance values.
APPLICATIONS INFORMATION
3. The model and FEA software is used to evaluate the
LTM4613 with heat sink and airflow.
4. Having solved for, and analyzed these thermal resistance
values and simulated various operating conditions in
the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled-environment chamber while operat-
ing the device at the same power loss as that which
was simulated. The outcome of this process and due
diligence yields the set of derating curves provided in
this data sheet.
The power loss curves in Figures 9 and 10 can be used
in coordination with the load current derating curves in
Figures 11 to 16 for calculating an approximate θJA for
the LTM4613. Each figure has three curves that are taken
at three different airflow conditions. Graph designation
delineates between no heat sink, and a BGA heat sink. Each
of the load current derating curves will lower the maxi-
mum load current as a function of the increased ambient
temperature to keep the maximum junction temperature
of the power module at 120°C maximum. This will main-
tain the maximum operating temperature below 125°C.
Table3 provides the approximate θJA for Figures 11 to 16.
A complete explanation of the thermal characteristics is
provided in the thermal application note, AN110.
Safety Considerations
The LTM4613 does not provide galvanic isolation from VIN
to VOUT. There is no internal fuse. If required, a slow blow
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic failure.
LTM4613
19
4613fd
For more information www.linear.com/LTM4613
Figure 9. Power Loss at 12VOUT and 15VOUT Figure 10. Power Loss at 5VOUT Figure 11. No Heat Sink with 36VIN
to 5VOUT
Figure 12. BGA Heat Sink with 36VIN to 5VOUT Figure 13. No Heat Sink
with 24VIN to 12VOUT
Figure 14. BGA Heat Sink
with 24VIN to 12VOUT
APPLICATIONS INFORMATION
Figure 15. No Heat Sink with 36VIN to 15VOUT Figure 16. BGA Heat Sink with 36VIN to 15VOUT
LOAD CURRENT (A)
0
5
6
7
8
4613 F09
4
3
246
10
2
1
0
POWER LOSS (W)
36VIN TO 15VOUT
24VIN TO 12VOUT
LOAD CURRENT (A)
0
5
6
7
8
4613 F10
4
3
246
10
2
1
0
POWER LOSS (W)
36VIN TO 5VOUT
AMBIENT TEMPERATURE (°C)
55
LOAD CURRENT (A)
3
4
5
85
105
4613 F11
2
1
065 75 95
6
7
8
OLFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
55
LOAD CURRENT (A)
3
4
5
85
105
4613 F12
2
1
065 75 95
6
7
8
OLFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
55
LOAD CURRENT (A)
3
4
5
85
105
4613 F13
2
1
065 75 95
6
7
8
OLFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
55
LOAD CURRENT (A)
3
4
5
85
105
4613 F14
2
1
065 75 95
6
7
8
OLFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
25 35
LOAD CURRENT (A)
3
4
5
75
105
4613 F15
2
1
045 55 65 85 95
6
7
8
OLFM
200LFM
400LFM
AMBIENT TEMPERATURE (°C)
25 35
LOAD CURRENT (A)
3
4
5
85
105
4613 F16
2
1
045 55 65 75 95
6
7
8
OLFM
200LFM
400LFM
LTM4613
20
4613fd
For more information www.linear.com/LTM4613
Layout Checklist/Example
The high integration of LTM4613 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
Use large PCB copper areas for high current path, in-
cluding VIN, PGND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capaci-
tors next to the VD, PGND and VOUT pins to minimize
high frequency noise.
Place a dedicated power ground layer underneath the
unit.
Use round corners for the PCB copper layer to minimize
the radiated noise.
To minimize the EMI noise and reduce module thermal
stress, use multiple vias for interconnection between
top layer and other power layers.
Do not put vias directly on pads.
If vias are placed onto the pads, the the vias must be
capped.
Interstitial via placement can also be used if necessary.
Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
Place one or more high frequency ceramic capacitors
close to the connection into the system board.
Figure 17 gives a good example of the recommended layout.
APPLICATIONS INFORMATION
Table 4. 5V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figure 11 36 Figure 10 0 None 8.5
Figure 11 36 Figure 10 200 None 6.5
Figure 11 36 Figure 10 400 None 6.5
Figure 12 36 Figure 10 0 BGA Heat Sink 8
Figure 12 36 Figure 10 200 BGA Heat Sink 6
Figure 12 36 Figure 10 400 BGA Heat Sink 6
Table 5. Heat Sink Manufacturers
HEAT SINK MANUFACTURER PART NUMBER WEBSITE
AAVID Thermalloy 375424B00034Gwww.aavidthermalloy.com
Cool Innovations 4-050503P to 4-050508P www.coolinnovations.com
Table 3. 12V and 15V Outputs
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 13, 15 24, 36 Figure 9 0 None 10
Figures 13, 15 24, 36 Figure 9 200 None 8
Figures 13, 15 24, 36 Figure 9 400 None 7
Figures 14, 16 24, 36 Figure 9 0 BGA Heat Sink 9.5
Figures 14, 16 24, 36 Figure 9 200 BGA Heat Sink 6.5
Figures 14, 16 24, 36 Figure 9 400 BGA Heat Sink 6.5
LTM4613
21
4613fd
For more information www.linear.com/LTM4613
APPLICATIONS INFORMATION
Figure 18. Typical 22V to 36VIN, 12V at 8A Design
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
FCB
MARG0
MARG1
MPGM
VOUT
VFB
PULL-UP SUPPLY ≤ 5V
R3
51k
C4
0.1µF
C5
22pF COUT1
22µF
16V
COUT2
180µF
16V
CIN
10µF
50V CERAMIC
VIN
22V TO 36V
CLOCK SYNC
REFER TO TABLE 2
ON/OFF
LTM4613
SGND PGND
MARGIN
CONTROL
R4
51k
RFB
5.23k
R1
392k
5% MARGIN
+
4613 F18
VDVIN PLLIN
C1 TO C3
10µF
50V
×3
VOUT
12V
8A
Figure 17. Recommended PCB Layout (LGA Shown, for BGA Use Circle Pads)
VIN
VOUT
GND
CIN CVD
CVD
COUT COUT
4613 F17
SGND
LTM4613
22
4613fd
For more information www.linear.com/LTM4613
Figure 20. 26V to 36VIN, 15V at 5A Design with 600kHz Frequency
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
FCB
MARG0
MARG1
MPGM
VOUT
VFB
PULL-UP SUPPLY ≤ 5V
R3
51k
C4
0.1µF
C5
22pF COUT1
22µF
16V
COUT2
220µF
16V
CIN
10µF
50V
CERAMIC
VIN
26V TO 36V
CLOCK SYNC
REFER TO TABLE 2
ON/OFF
LTM4613
SGND PGND
MARGIN
CONTROL
R4
51k
RFB
4.12k
RfSET
1.32M
R1
392k
5% MARGIN
+
4613 F20
VDVIN PLLIN VOUT
15V
5A
C1 TO C3
10µF
50V
×3
APPLICATIONS INFORMATION
Figure 19. Typical 5V to 36VIN, 3.3V at 8A Design with 400kHz Frequency
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
FCB
MARG0
MARG1
MPGM
VOUT
VFB
PULL-UP SUPPLY ≤ 5V
R3
51k
C4
0.1µF
C5
22pF COUT1
22µF
6.3V
COUT2
180µF
6.3V
CIN
10µF
50V CERAMIC
VIN
5V TO 36V
CLOCK SYNC
REFER TO TABLE 2
EXTERNAL 5V SUPPLY
IMPROVES EFFICIENCY—
ESPECIALLY FOR HIGH
INPUT VOLTAGES
ON/OFF LTM4613
SGND PGND
MARGIN
CONTROL
R4
51k
RfSET
93.1k
RFB
22.1k
R1
392k
5% MARGIN
+
4613 F19
VDVIN PLLIN VOUT
3.3V
8A
C1 TO C3
10µF
50V
×3
LTM4613
23
4613fd
For more information www.linear.com/LTM4613
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
VOUT
VFB
FCB
MARG0
MARG1
MPGM
PULL-UP SUPPLY ≤ 5V
R2
51k
C7
0.33µF
C6
47pF C3
22µF
16V
4613 F21
C4
180µF
16V
C11
0.1µF
C5
100µF
50V
C2
10µF
50V
C8
10µF
50V
VIN
20V TO 36V
LTC6908-1
2-PHASE
OSCILLATOR
CLOCK SYNC
0° PHASE
CLOCK SYNC
180° PHASE
LTM4613
SGND PGND
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
LTM4613
SGND PGND
MARGIN
CONTROL
5% MARGIN
R4
51k
RFB
2.61k
R1
392k
R5
166k
V+
GND
SET
OUT1
OUT2
MOD
+
VOUT
VFB
FCB
MARG0
MARG1
MPGM
C9
22µF
16V
C10
180µF
16V
R6
392k
+
+
VOUT = 0.6V • 100k/N + RFB
RFB
VDVIN PLLIN
VDVIN PLLIN
VOUT
12V
16A
C1
10µF
50V
×3
C11
10µF
50V
×3
Figure 21. 2-Phase, Parallel 12V at 16A Design with 600kHz Frequency
APPLICATIONS INFORMATION
LTM4613
24
4613fd
For more information www.linear.com/LTM4613
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
VOUT
VFB
FCB
MARG0
MARG1
MPGM
PULL-UP SUPPLY ≤ 5V
R2
51k
C7
0.1µF
C6
22pF C3
22µF
16V
4613 F22
C4
180µF
16V
12V
6A
C11
0.1µF
C5
100µF
50V
C2
10µF
50V
C8
10µF
50V
VIN
22V TO 36V
LTC6908-1
2-PHASE
OSCILLATOR
CLOCK SYNC
0° PHASE
CLOCK SYNC
180° PHASE
LTM4613
SGND PGND
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
LTM4613
SGND
12V TRACK
PGND
MARGIN
CONTROL
5% MARGIN
R4
51k
RFB1
5.23k
RFB2
6.34k
R1
392k
R8
100k
R9
6.34k
R3
51k
R7
51k
PULL-UP SUPPLY ≤ 5V
R5
166k
V+
GND
SET
OUT1
OUT2
MOD
+
VOUT
VFB
FCB
MARG0
MARG1
MPGM
C1
22pF C9
22µF
16V
C10
180µF
16V
10V
6A
MARGIN
CONTROL
R6
392k
+
+
VDVIN PLLIN
VDVIN PLLIN
C11
10µF
50V
×3
C1
10µF
50V
×3
Figure 22. 2-Phase, 12V and 10V at 6A Design with 600kHz Frequency and Output Voltage Tracking
APPLICATIONS INFORMATION
LTM4613
25
4613fd
For more information www.linear.com/LTM4613
DRVCC
fSET
TRACK/SS
PGOOD
RUN
COMP
INTVCC
FCB
MARG0
MARG1
MPGM
VOUT
VFB
VDVIN
5V
R2
51k
C7
0.15µF
C6
22pF C3
22µF
6.3V
4613 F23
C4
180µF
6.3V
5V
8A
C11
0.1µF
C5
100µF
50V
C2
10µF
50V
C8
10µF
50V
VIN
7V TO 36V
LTC6908-1
2-PHASE
OSCILLATOR
PLLIN
CLOCK SYNC
0° PHASE
CLOCK SYNC
180° PHASE
SGND PGND
PGOOD
RUN
COMP
INTVCC
DRVCC
fSET
TRACK/SS
VIN
VDPLLIN
SGND
5V TRACK
PGND
MARGIN
CONTROL
R4
51k
RfSET1
133k RFB1
13.7k
R1
392k
R8
100k
R9
22.1k
RfSET2
64.9k
R3
51k
R7
51k
3.3V
R5
200k
V+
GND
SET
OUT1
OUT2
MOD
+
VOUT
VFB
FCB
MARG0
MARG1
MPGM
C1
22pF C9
22µF
6.3V
C10
180µF
6.3V
3.3V
8A
MARGIN
CONTROL
RFB2
22.1k
R6
392k
+
+
LTM4613
LTM4613
5% MARGIN
C1
10µF
50V
×3
C11
10µF
50V
×3
Figure 23. 2-Phase, 5V and 3.3V at 8A Design with 500kHz Frequency and Output Voltage Tracking
APPLICATIONS INFORMATION
LTM4613
26
4613fd
For more information www.linear.com/LTM4613
PIN NAME
A1
A2
A3
A4
A5
VIN
VIN
VIN
VIN
VIN
B1
B2
B3
B4
B5
VIN
VIN
VIN
VIN
VIN
Pin Assignment Tables
(Arranged by Pin Function)
PIN NAME
D1
D2
D3
D4
D5
D6
PGND
PGND
PGND
PGND
PGND
PGND
E1
E2
E3
E4
E5
E6
E7
E8
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
F1
F2
F3
F4
F5
F6
F7
F8
F9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PIN NAME
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
PIN NAME
A6
A7
A8
A9
A10
A11
A12
VD
INTVCC
PLLIN
TRACK/SS
RUN
COMP
MPGM
B6
B7
B8
B9
B10
B11
B12
VD
VD
RUN
MPGM
fSET
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
VD
VD
VD
VD
VD
VD
VD
DRVCC
MARG1
MARG0
D7
D8
D9
D10
D11
D12
SGND
COMP
MARG1
E9
E10
E11
E12
DRVCC
DRVCC
F10
F11
F12
VFB
G12 PGOOD
H12 SGND
J12 NC
K12 NC
L12 NC
M12 FCB
PACKAGE DESCRIPTION
LTM4613
27
4613fd
For more information www.linear.com/LTM4613
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4613#packaging for the most recent package drawings.
DETAIL B
DETAIL B
SUBSTRATE
MOLD
CAP
// bbb Z
Z
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
LAND DESIGNATION PER JESD MO-222, SPP-010
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 133
4
3
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
PACKAGE TOP VIEW
4
PAD “A1”
CORNER
X
Y
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
3
SEE NOTES
SUGGESTED PCB LAYOUT
TOP VIEW
DETAIL A
F
G
H
L
M
J
K
E
A
B
C
D
2 14 312 11 9 510 678
D
0.630 ±0.025 Ø 133x
E
b
e
e
b
F
G
LGA 133 1212 REV A
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1
SYMBOL
A
b
D
E
e
F
G
H1
H2
aaa
bbb
eee
MIN
4.22
0.60
0.27
3.95
NOM
4.32
0.63
15.0
15.0
1.27
13.97
13.97
0.32
4.00
MAX
4.42
0.66
0.37
4.05
0.15
0.10
0.05
NOTES
DIMENSIONS
TOTAL NUMBER OF LGA PADS: 133
LTMXXXXXX
µModule
H2
H1
DETAIL A
0.630 ±0.025 SQ. 133x
SYXeee
C(0.30)
PAD 1
6.9850
6.9850
5.7150
5.7150
4.4450
4.4450
3.1750
3.1750
1.9050
1.9050
0.6350
0.6350
0.0000
6.9850
6.9850
5.7150
5.7150
4.4450
4.4450
3.1750
3.1750
1.9050
1.9050
0.6350
0.6350
0.0000
LGA Package
133-Lead (15mm × 15mm × 4.32mm)
(Reference LTC DWG # 05-08-1884 Rev A)
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
7
SEE NOTES
LTM4613
28
4613fd
For more information www.linear.com/LTM4613
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4613#packaging for the most recent package drawings.
4
PIN “A1”
CORNER
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
PACKAGE TOP VIEW
X
Y
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
3
SEE NOTES
SUGGESTED PCB LAYOUT
TOP VIEW
BGA 133 1114 REV Ø
LTMXXXXXX
µModule
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
DETAIL A
PIN 1
0.0000
0.0000
DETAIL A
Øb (133 PLACES)
D
A
DETAIL B
PACKAGE SIDE VIEW
Z
MX YZddd
MZeee
0.630 ±0.025 Ø 133x
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
4.72
0.50
4.22
0.60
0.60
NOM
4.92
0.60
4.32
0.75
0.63
15.0
15.0
1.27
13.97
13.97
0.32
4.00
MAX
5.12
0.70
4.42
0.90
0.66
0.37
4.05
0.15
0.10
0.20
0.30
0.15
NOTES
DIMENSIONS
TOTAL NUMBER OF BALLS: 133
Eb
e
e
b
A2
F
G
BGA Package
133-Lead (15mm × 15mm × 4.92mm)
(Reference LTC DWG # 05-08-1992 Rev Ø)
0.6350
0.6350
1.9050
1.9050
3.1750
3.1750
4.4450
4.4450
5.7150
5.7150
6.9850
6.9850
6.9850
5.7150
5.7150
4.4450
4.4450
3.1750
3.1750
1.9050
1.9050
0.6350
0.6350
6.9850
G
F
E
A
B
D
C
H
M
L
K
J
2 14 356712 891011
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
7
SEE NOTES
0.27
3.95
DETAIL B
SUBSTRATE
A1
b1
ccc Z
MOLD
CAP
// bbb Z
Z
H2
H1
LTM4613
29
4613fd
For more information www.linear.com/LTM4613
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 06/15 Added BGA Package 2, 28
B 09/15 Added LTM4613IY (SnPb) 2
C 07/16 Added MP-Grade 2
D 09/16 Changed Max value of VINTVCC of 5.3 to 5.5 3
LTM4613
30
4613fd
For more information www.linear.com/LTM4613
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2011
LT 0916 REV D • PRINTED IN USA
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTM4613
RELATED PARTS
PACKAGE PHOTOGRAPH
PART NUMBER DESCRIPTION COMMENTS
LTM4612 Lower IOUT Than LTM4613, EN55022B Compliant,
36VIN, 5A µModule Regulator
5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, 15mm × 15mm × 2.82mm (LGA)
LTM4606 EN55022B Compliant, 28VIN, 6A µModule Regulator 4.5V ≤ VIN ≤ 28V, 0.5V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.82mm (LGA),
15mm × 15mm × 3.42mm (BGA)
LTM8031 EN55022B Compliant, 36VIN, 1A µModule Regulator 3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 9mm × 15mm × 2.82mm (LGA),
9mm × 15mm × 3.42mm (BGA)
LTM8032 EN55022B Compliant, 36VIN, 2A µModule Regulator 3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 9mm × 15mm × 2.82mm (LGA),
9mm × 15mm × 3.42mm (BGA)
LTM8033 EN55022B Compliant, 36VIN, 3A µModule Regulator 3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 24V, 11.25mm × 15mm × 4.32mm (LGA),
11.25mm × 15mm × 4.92mm (BGA)
LTM8028 Low Output Noise, 36VIN, 5A µModule Regulator 6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 1.8V, 15mm × 15mm × 4.92mm (BGA)
LTM4601AHV 28VIN, 12A µModule Regulator with PLL, Tracking and
Margining
4.5V VIN 28V, 0.6V VOUT 5V, 15mm × 15mm × 2.82mm (LGA), 15mm ×
15mm × 3.42mm (BGA)
LTM4641 38VIN, 10A µModule Regulator with Input and Load
Protection
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 6V, 15mm × 15mm × 5.01mm (BGA)
LTM8003 FMEA Compliant Pinout, 150°C Operation, 40VIN, 3.5A
µModule Regulator
3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 18V, 6.25mm × 9mm × 3.32mm (BGA)
LTM8053 40VIN, 3.5A µModule Regulator in 6.25mm × 9mm BGA
Package
3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 15V, 6.25mm × 9mm × 3.32mm (BGA)
DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design:
Selector Guides
Demo Boards and Gerber Files
Free Simulation Tools
Manufacturing:
Quick Start Guide
PCB Design, Assembly and Manufacturing Guidelines
Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.

Products

DC DC CONVERTER 12V 8A
入手可能な数量1240
単価5526
DC DC CONVERTER 3.3-15V 8A
入手可能な数量265
単価5747
DC DC CONVERTER 3.3-15V 8A
入手可能な数量305
単価7937
DC DC CONVERTER 12V 8A
入手可能な数量335
単価10215
DC DC CONVERTER 12V 8A
入手可能な数量0
単価6922
DC DC CONVERTER 3.3-15V 8A
入手可能な数量0
単価7230
BOARD DEMO LTM4613
入手可能な数量0
単価7612