PDTA115E Datasheet by NXP USA Inc.

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DATA SHEET
Product data sheet
Supersedes data of 2004 May 05 2004 Jul 30
DISCRETE SEMICONDUCTORS
PDTA115E series
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩ
2004 Jul 30 2
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
FEATURES
Built-in bias resistors
Simplified circuit design
Reduction of component count
Reduced pick and place costs.
APPLICATIONS
General purpose switching and amplification
Inverter and interface circuits
Circuit driver.
QUICK REFERENCE DATA
DESCRIPTION
PNP resistor-equipped transistor (see “Simplified outline,
symbol and pinning” for package details).
SYMBOL PARAMETER TYP. MAX. UNIT
VCEO collector-emitter
voltage
− −50 V
IOoutput current (DC) − −20 mA
R1 bias resistor 100 kΩ
R2 bias resistor 100 kΩ
PRODUCT OVERVIEW
Note
1. * = p: Made in Hong Kong.
* = t: Made in Malaysia.
* = W: Made in China.
TYPE NUMBER PACKAGE MARKING CODE NPN COMPLEMENT
PHILIPS EIAJ
PDTA115EE SOT416 SC-75 5E PDTC115EE
PDTA115EEF SOT490 SC-89 6B PDTC115EEF
PDTA115EK SOT346 SC-59 62 PDTC115EK
PDTA115EM SOT883 SC-101 F6 PDTC115EM
PDTA115ES SOT54 (TO-92) SC-43 TA115E PDTC115ES
PDTA115ET SOT23 *AB(1) PDTC115ET
PDTA115EU SOT323 SC-70 *7C(1) PDTC115EU
E 1 #2 E 2 :21: E : :'_:,‘:n:| MAMJJH PDTA115EE base PDTA115EEF emitter PDTA115EK co‘lector PDTA115ET 7 PDTA115EU I Tap mew MDEN‘ PDTA115EM base emitter 7 co‘lector , 1 Emmm mew M00207 2004 Ju‘ 30
2004 Jul 30 3
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
SIMPLIFIED OUTLINE, SYMBOL AND PINNING
TYPE NUMBER SIMPLIFIED OUTLINE AND SYMBOL PINNING
PIN DESCRIPTION
PDTA115ES 1base
2collector
3emitter
PDTA115EE 1base
PDTA115EEF 2emitter
PDTA115EK 3collector
PDTA115ET
PDTA115EU
PDTA115EM 1base
2emitter
3collector
handbook, halfpage
MAM338
1
2
3
R1
R2
2
3
1
handbook, halfpage
MDB271
Top view
12
3
1
2
3
R1
R2
handbook, halfpage
MDB267
2
1
3
Bottom view
1
2
3
R1
R2
2004 Jul 30 4
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
ORDERING INFORMATION
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
PDTA115EE plastic surface mounted package; 3 leads SOT416
PDTA115EEF plastic surface mounted package; 3 leads SOT490
PDTA115EK plastic surface mounted package; 3 leads SOT346
PDTA115EM leadless ultra small plastic package; 3 solder lands; body
1.0 × 0.6 × 0.5 mm
SOT883
PDTA115ES plastic single-ended leaded (through hole) package; 3 leads SOT54
PDTA115ET plastic surface mounted package; 3 leads SOT23
PDTA115EU plastic surface mounted package; 3 leads SOT323
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCBO collector-base voltage open emitter − −50 V
VCEO collector-emitter voltage open base − −50 V
VEBO emitter-base voltage open collector − −10 V
VIinput voltage
positive +10 V
negative − −40 V
IOoutput current (DC) − −20 mA
ICM peak collector current − −100 mA
Ptot total power dissipation Tamb 25 °C
SOT23 note 1 250 mW
SOT54 note 1 500 mW
SOT323 note 1 200 mW
SOT346 note 1 250 mW
SOT416 note 1 150 mW
SOT490 notes 1 and 2 250 mW
SOT883 notes 2 and 3 250 mW
Tstg storage temperature 65 +150 °C
Tjjunction temperature 150 °C
Tamb operating ambient temperature 65 +150 °C
2004 Jul 30 5
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
THERMAL CHARACTERISTICS
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient Tamb 25 °C
SOT23 note 1 500 K/W
SOT54 note 1 250 K/W
SOT323 note 1 625 K/W
SOT346 note 1 500 K/W
SOT416 note 1 833 K/W
SOT490 notes 1 and 2 500 K/W
SOT883 notes 2 and 3 500 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ICBO collector-base cut-off current VCB = 50 V; IE = 0 A −−−100 nA
ICEO collector-emitter cut-off current VCE = 30 V; IB = 0 A −−−1μA
VCE = 30 V; IB = 0 A;
Tj = 150 °C
−−−50 μA
IEBO emitter-base cut-off current VEB = 5 V; IC = 0 A −−−50 μA
hFE DC current gain VCE = 5 V; IC = 5 mA 80 − −
VCEsat collector-emitter saturation voltage IC = 5 mA; IB = 0.25 mA −−−150 mV
Vi(off) input-off voltage IC = 100 μA; VCE = 5 V − −1.2 0.5 V
Vi(on) input-on voltage IC = 1 mA; VCE = 0.3 V 31.6 V
R1 input resistor 70 100 130 kΩ
resistor ratio 0.8 11.2
Cccollector capacitance IE = ie = 0 A; VCB = 10 V;
f = 1 MHz
−−3pF
R2
R1
--------
05 1mm scale DIMENSIONS (mm arelhe m A A‘ UNIT max hp c D E e 91 HE G v w 095 can 025 ‘5 09 175 045 023 m“ use 0‘ 015 (no 14 07 ms 015 013 ”2 "2 s oumNE EufiOPEAN VERS'o" IEC JED JEITA PROJEcnou 'SSUE ””5 50mm 5075 E@ 4444—“ 2004 Ju‘ 30
2004 Jul 30 6
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
PACKAGE OUTLINES
UNIT A1
max bpcDEe
1
H
E
L
p
Qw
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1 0.30
0.15 0.25
0.10 1.8
1.4 0.9
0.7 0.5
e
11.75
1.45 0.2
v
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.23
0.13
SOT416 SC-75
w
M
bp
D
e1
e
A
A1
Lp
Q
detail X
HE
EAB
B
v
M
A
0 0.5 1 mm
scale
A
0.95
0.60
c
X
12
3
Plastic surface-mounted package; 3 leads SOT41
6
04-11-04
06-03-16
a 1 2mm scawe UNIT A up c D E e 2‘ ME Lp v w a a a 33 n 2 1 7 n 95 ‘ 7 o 5 mm as 023 01 15 075 ‘0 05 15 03 0‘ 01 REFERENCES OUTLINE £132:ng ISSUE DATE VERSION IEC JEDEC JEITA 9597—25 someo so 39 E} @ 0670346 2004 Ju‘ 30 7
2004 Jul 30 7
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT bpcDE e1HELpwv
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
05-07-28
06-03-16
IEC JEDEC JEITA
mm 0.33
0.23 0.2
0.1 1.7
1.5 0.95
0.75 0.5
e
1.0 1.7
1.5 0.1
0.1
DIMENSIONS (mm are the original dimensions)
0.5
0.3
SOT490 SC-89
bp
D
e1
e
A
Lp
detail X
HE
E
wM
vMA
B
AB
0 1 2 mm
scale
A
0.8
0.6
c
X
12
3
Plastic surface-mounted package; 3 leads SOT49
0
n 1 2mm W scaxe DIMENSIONSmImaremeovg al UNIT A A, up c u E 2 e1 HE LP a v w 13 m use 026 31 ‘7 so as 033 mm H) 0013 035 (no 27 13 ‘9 ”95 25 02 023 02 02 OUTLINE REFERENCES EU PR T0236 5059A 50mm VERSION IEC JEDEC JEITA Er @ 2004 Ju‘ 30
2004 Jul 30 8
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A
1
b
p
cDE e
1
H
E
L
p
Qwv
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.50
0.35 0.26
0.10 3.1
2.7 1.7
1.3 0.95
e
1.9 3.0
2.5 0.33
0.23 0.2
0.2
DIMENSIONS (mm are the original dimensions)
0.6
0.2
SOT346 TO-236 SC-59A
bp
D
e1
e
A
A1
Lp
Q
detail X
HE
E
w
M
v
M
A
B
A
B
0 1 2 mm
scale
A
1.3
1.0 0.1
0.013
c
X
12
3
Plastic surface-mounted package; 3 leads SOT34
6
04-11-11
06-03-16
Product data sheet PNP reSIstor-eqUIpped tranSIstors; PDTA115E series R2 = 1 00 k9 aSIic package; 3 Solder lands; body 1.0 x 0.6 x 0.5 mm SOT863 ‘7 L 4. « L14» 7.- I T 04» scaIe DIMENSIONS (mm are me original dimensions) UNIT Am “I h h‘ D E e L L‘ max. 050 020 055 062 m2 030 030 mm 046 003 012 M7 055 095 ”35 5 022 022 Male 1 IncImmg pIaImg |hIckneSS OUTLINE REF "555 EUROPEAN VERSION IEC JEDEC Em PROJECTION SOTEBG SC Im E @ 2:709:09: ISSUE DATE 2004 Ju‘ 30 9
2004 Jul 30 9
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A1
max.
A(1) bb
1e1
eLL
1
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.50
0.46 0.20
0.12 0.55
0.47
0.03 0.62
0.55 0.35 0.65
DIMENSIONS (mm are the original dimensions)
Note
1. Including plating thickness
0.30
0.22
0.30
0.22
SOT883 SC-101 03-02-05
03-04-03
DE
1.02
0.95
L
E
2
3
1
b
b1
A1
A
D
L1
0 0.5 1 mm
scale
L
eadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm SOT88
3
e
e1
DIMENSIONS (mm mm o g al dimensions) 25 scaIe 5mm L m uNn A h h‘ c D d E e 2‘ L ”I” 52 GAS 066 045 45 I7 A2 145 ’“m 50 M0 055 035 4A IA as 254 ‘27 127 25 Male I TermmaI dImensIDns mm m: lune ave uncummlled \u allow var IIuw oI pIasIIc and IeImInal IrreguIauues OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION .5; JEDEC J5,” PROJECTION W SOTSA T0792 3043»: E} @ nuns 2004 JU‘ 30 10
2004 Jul 30 10
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 5.2
5.0
b
0.48
0.40
c
0.45
0.38
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
L
14.5
12.7
e
2.54
e1
1.27
L1(1)
max.
2.5
b1
0.66
0.55
DIMENSIONS (mm are the original dimensions)
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
SOT54 TO-92 SC-43A 04-06-28
04-11-16
A L
0 2.5 5 mm
scale
b
c
D
b1L1
d
E
Plastic single-ended leaded (through hole) package; 3 leads SOT5
4
e1
e
1
2
3
n 1 2mm scawe DIMENSIONS (mm amine or 9 al A] UNIT A max up c u E e 91 RE LP a v w H 045 ms 30 14 25 0A5 055 mm 09 01 038 009 28 12 ‘9 ”95 21 m5 045 02 0‘ REFERENCES OUTLINE EUROPEAN “55'0" IEc JEDEC JEITA PROJECYION 'SSUE DATE W some ToeasAB a @ 0670346 2004 Ju‘ 30 1 1
2004 Jul 30 11
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A
1
max. b
p
cDE e
1
H
E
L
p
Qwv
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
04-11-04
06-03-16
IEC JEDEC JEITA
mm 0.1 0.48
0.38 0.15
0.09 3.0
2.8 1.4
1.2 0.95
e
1.9 2.5
2.1 0.55
0.45 0.1
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
SOT23 TO-236AB
bp
D
e1
e
A
A1
Lp
Q
detail X
HE
E
w
M
v
M
A
B
AB
0 1 2 mm
scale
A
1.1
0.9
c
X
12
3
Plastic surface-mounted package; 3 leads SOT2
3
DIMENSIONS (mm are me or 9 al dimensions) sca‘e 2mm ‘1 UNIT A max up c D E e 2‘ NE LI) 0 v w H 04 025 22 135 22 045 023 mm as 0‘ 03 (no 18 115 ‘3 "65 20 015 013 02 02 REFERENCES OUTLINE EUROPEAN “55'0" IEc JEDEC JEITA PROJECTION '55“ ”ME somza 50770 E @ Q“ a” 2004 Ju‘ 30 12
2004 Jul 30 12
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
UNIT A1
max bpcD Ee1HELpQwv
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.1
1.1
0.8 0.4
0.3 0.25
0.10 2.2
1.8 1.35
1.15 0.65
e
1.3 2.2
2.0 0.23
0.13 0.20.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
SOT323 SC-70
w
M
bp
D
e1
e
A
B
A1
Lp
Q
detail X
c
HE
E
v
M
A
AB
y
0 1 2 mm
scale
A
X
12
3
Plastic surface-mounted package; 3 leads SOT32
3
04-11-04
06-03-16
2004 Jul 30 13
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩPDTA115E series
DATA SHEET STATUS
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
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accurate and reliable. However, NXP Semiconductors
does not give any representations or warranties,
expressed or implied, as to the accuracy or completeness
of such information and shall have no liability for the
consequences of use of such information.
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
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equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
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accepts no liability for inclusion and/or use of NXP
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applications and therefore such inclusion and/or use is at
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Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) may cause permanent damage to
the device. Limiting values are stress ratings only and
operation of the device at these or any other conditions
above those given in the Characteristics sections of this
document is not implied. Exposure to limiting values for
extended periods may affect device reliability.
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regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
founded by PHILIPS
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under patent- or other industrial or intellectual property rights.
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands R75/03/pp14 Date of release: 2004 Jul 30 Document order number: 9397 750 13648

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