SI3932DV Datasheet by Vishay Siliconix

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Si3932DV
www.vishay.com Vishay Siliconix
S10-0642-Rev. A, 22-Mar-10 1Document Number: 65736
For technical questions, contact: pmostechsupport@vishay.com
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Dual N-Channel 30 V (D-S) MOSFET
Marking code: MH
FEATURES
• TrenchFET® power MOSFET
100% Rg tested
Material categorization:
for definitions of compliance please see
www.vishay.com/doc?99912
APPLICATIONS
Load switch for portable applications
•DC/DC converters
Notes
a. TC = 25 °C
b. Surface mounted on 1" x 1" FR4 board
c. t = 5 s
d. Maximum under steady state conditions is 150 °C/W
PRODUCT SUMMARY
VDS (V) 30
RDS(on) max. () at VGS = 10 V 0.058
RDS(on) max. () at VGS = 4.5 V 0.073
Qg typ. (nC) 1.8
ID (A) a3.7
Configuration Dual
Top View
TSOP-6 Dual
1
G1
2
S2
3
G2
D1
6
S1
5
D2
4
N-Channel MOSFETN-Channel MOSFET
G
1
D
1
S
1
G
2
D
2
S
2
ORDERING INFORMATION
Package TSOP-6
Lead (Pb)-free and halogen-free Si3932DV-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 30 V
Gate-source voltage VGS ± 20
Continuous drain current (TJ = 150 °C)
TC = 25 °C
ID
3.7
A
TC = 70 °C 3
TA = 25 °C 3.4 b, c
TA = 70 °C 2.7 b, c
Pulsed drain current IDM 15
Continuous source-drain diode current TC = 25 °C IS
1.17
TA = 25 °C 0.95 b, c
Maximum power dissipation
TC = 25 °C
PD
1.4
W
TC = 70 °C 0.9
TA = 25 °C 1.14 b, c
TA = 70 °C 0.73 b, c
Operating junction and storage temperature range TJ, Tstg -55 to +150 °C
Soldering recommendations (peak temperature) d, e 260
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum junction-to-ambient b, d t 5 s RthJA 93 110 °C/W
Maximum junction-to-foot Steady state RthJF 75 90
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Si3932DV
www.vishay.com Vishay Siliconix
S10-0642-Rev. A, 22-Mar-10 2Document Number: 65736
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2%
b. Guaranteed by design, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 30 - - V
VDS temperature coefficient VDS/TJID = 250 μA -29-
mV/°C
VGS(th) temperature coefficient VGS(th)/TJ--4-
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 1.2 - 2.2 V
Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
Zero gate voltage drain current IDSS
VDS = 30 V, VGS = 0 V - - 1 μA
VDS = 30 V, VGS = 0 V, TJ = 55 °C - - 10
On-state drain current a ID(on) V
DS 5 V, VGS = 10 V 10 - - A
Drain-source on-state resistance a RDS(on)
VGS = 10 V, ID = 3.4 A - 0.047 0.058
VGS = 4.5 V, ID = 3 A - 0.058 0.073
Forward transconductance agfs VDS = 15 V, ID = 3.4 A - 10 - S
Dynamic b
Input capacitance Ciss
VDS = 15 V, VGS = 0 V, f = 1 MHz
- 235 -
pFOutput capacitance Coss -45-
Reverse transfer capacitance Crss -16-
Total gate charge Qg VDS = 15 V, VGS = 10 V, ID = 3.4 A -3.76
nC
VDS = 15 V, VGS = 4.5 V, ID = 3.4 A
-1.83
Gate-source charge Qgs -0.74-
Gate-drain charge Qgd -0.42-
Gate resistance Rgf = 1 MHz 1 5 10
Turn-on delay time td(on)
VDD = 15 V, RL = 5.6
ID 2.7 A, VGEN = 4.5 V, Rg = 1
-1020
ns
Rise time tr -1530
Turn-off delay time td(off) -1020
Fall time tf-1020
Turn-on delay time td(on)
VDD = 15 V, RL = 5.6
ID 2.7 A, VGEN = 10 V, Rg = 1
-510
Rise time tr -1530
Turn-off delay time td(off) -1020
Fall time tf-1020
Drain-Source Body Diode Characteristics
Continuous source-drain diode current ISTC = 25 °C - - 1.17 A
Pulse diode forward current ISM --15
Body diode voltage VSD IS = 2.7 A, VGS = 0 V - 0.85 1.2 V
Body diode reverse recovery time trr
IF = 2.7 A, di/dt = 100 A/μs,
TJ = 25 °C
-1020ns
Body diode reverse recovery charge Qrr -410nC
Reverse recovery fall time ta-6-
ns
Reverse recovery rise time tb-4-
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Si3932DV
www.vishay.com Vishay Siliconix
S10-0642-Rev. A, 22-Mar-10 3Document Number: 65736
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
3
6
9
12
15
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VGS =10Vthru4V
VGS =3V
VGS =2V
VDS- Drain-to-Source Voltage (V)
- Drain Current (A)ID
0.00
0.02
0.04
0.06
0.08
0.10
0 3 6 9 12 15
VGS =4.5V
VGS =10V
- On-Resistance (Ω)R DS(on)
ID- Drain Current (A)
0
2
4
6
8
10
01234
VDS=24V
ID=3.4A
VDS=7.5V
VDS=15V
- Gate-to-Source Voltage (V)
Qg- Total Gate Charge (nC)
VGS
0
1
2
3
4
5
0.0 0.5 1.0 1.5 2.0 2.5 3.0
TC= 25 °C
TC=125 °C
TC= - 55 °C
VGS -Gate-to-Source Voltage (V)
- Drain Current (A)ID
Crss
0
50
100
150
200
250
300
0 5 10 15 20 25 30
Ciss
Coss
VDS-Drain-to-Source Voltage (V)
C - Capacitance (pF)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
- 50 - 25 0 25 50 75 100 125 150
ID=3.4A
VGS =10V,V
GS =4.5V
TJ- Junction Temperature (°C)
(Normalized)
- On-Resistance
RDS(on)
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Si3932DV
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S10-0642-Rev. A, 22-Mar-10 4Document Number: 65736
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Source-Drain Diode Forward Voltage
Threshold Voltage
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power (Junction-to-Ambient)
Safe Operating Area, Junction-to-Ambient
0.1
1
10
100
0.0 0.2 0.4 0.6 0.8 1.0 1.2
TJ=25 °C
TJ= 150 °C
VSD-Source-to-Drain Voltage (V)
- Source Current (A)I S
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
- 50 - 25 0 25 50 75 100 125 150
ID= 250 μA
(V)VGS(th)
TJ- Temperature (°C)
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0246810
TJ=25 °C
ID=3.4A
TJ=125 °C
- On-Resistance (Ω)
RDS(on)
VGS -Gate-to-Source Voltage (V)
0
1
2
3
4
5
6
0.01 0.1 1 10 100 1000
Time (s)
Power (W)
100
1
0.1 1 10 100
0.01
10
0.1
TA=25 °C
Single Pulse
Limited by RDS(on)*
BVDSS Limited
1ms
100 μs
10 ms
VDS- Drain-to-Source Voltage (V)
*V
GS > minimum VGS at which RDS(on) isspecified
- Drain Current (A)
ID
DC
1s,10s
100 ms
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Si3932DV
www.vishay.com Vishay Siliconix
S10-0642-Rev. A, 22-Mar-10 5Document Number: 65736
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Current Derating aPower Derating
Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit
0
1
2
3
4
5
0 255075100125150
Package Limited
TC-Case Temperature (°C)
ID- Drain Current (A)
0.0
0.4
0.8
1.2
1.6
25 50 75 100 125 150
TC- Foot Temperature (°C)
Power Dissipation (W)
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Si3932DV
www.vishay.com Vishay Siliconix
S10-0642-Rev. A, 22-Mar-10 6Document Number: 65736
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for silicon
technology and package reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65736.
10-3 10-2 110 100010-1
10-4 100
0.2
0.1
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
t
1
t
2
Notes:
P
DM
1. Duty Cycle, D =
2. Per Unit Base=R
thJA
= 150 °C/W
3. T
JM
-T
A
=P
DM
Z
thJA(t)
t
1
t
2
4. Surface Mounted
Duty Cycle = 0.5
Single Pulse
0.02
0.05
10-3 10-2 01110-1
10-4
0.2
0.1
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1
0.1
0.01
0.05
Single Pulse
0.02
1 O l o EHH” EHHflH »—|:|—4 4 L— I—EI—I 4 L— - ADTSOP 6666666666
Vishay Siliconix
Package Information
Document Number: 71200
18-Dec-06
www.vishay.com
1
1 2 3
Gauge Plane
L
5 4
R
R
C 0.15 M B A
b
C 0.08
0.17 Ref
Seating Plane
-C-
Seating Plane
A
1
A
2 A
-A-
D
-B-
E
1 E
L
2
(L
1
)
c
4x 1
4x 1
e
e1
1 2 3
6 5 4
C 0.15 M B A
b
-B-
E
1 E
e
e1
5-LEAD TSOP 6-LEAD TSOP
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A 0.91 - 1.10 0.036 - 0.043
A
1 0.01 - 0.10 0.0004 - 0.004
A
2 0.90 - 1.00 0.035 0.038 0.039
b 0.30 0.32 0.45 0.012 0.013 0.018
c 0.10 0.15 0.20 0.004 0.006 0.008
D 2.95 3.05 3.10 0.116 0.120 0.122
E 2.70 2.85 2.98 0.106 0.112 0.117
E
1 1.55 1.65 1.70 0.061 0.065 0.067
e 0.95 BSC 0.0374 BSC
e
1 1.80 1.90 2.00 0.071 0.075 0.079
L 0.32 - 0.50 0.012 - 0.020
L
1 0.60 Ref 0.024 Ref
L
2 0.25 BSC 0.010 BSC
R 0.10 - - 0.004 - -
0 4 8 0 4 8
1 7 Nom 7 Nom
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
_ VISHAY 257 mum mm mm COOL seen 33 as as m 165 m 232 255 295 um us +—+ o 074 mm ”75 mzz i HHF was 0049 cam ‘25 ‘25 ms 3 ‘
AN823
Vishay Siliconix
Document Number: 71743
27-Feb-04
www.vishay.com
1
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
FIGURE 1. Recommended Copper Spreading Footprint
0.049
1.25
0.010
0.25
0.014
0.35
0.074
1.875 0.122
3.1
0.026
0.65
0.167
4.25
0.049
1.25
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components,thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Ramp-Up Rate +6_C/Second Maximum
Temperature @ 155 " 15_C120 Seconds Maximum
Temperature Above 180_C70 180 Seconds
Maximum Temperature 240 +5/0_C
Time at Maximum Temperature 20 40 Seconds
Ramp-Down Rate +6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
_ VISHAY
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Vishay Siliconix
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2
Document Number: 71743
27-Feb-04
255 260_C
1X4_C/s (max) 3-6_C/s (max)
10 s (max)
Reflow Zone
Pre-Heating Zone
3_C/s (max)
140 170_C
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
60-120 s (min)
217_C
60 s (max)
THERMAL PERFORMANCE
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rqjf 30_C/W
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
0.6
0.8
1.0
1.2
1.4
1.6
50 25 0 25 50 75 100 125 150
VGS = 4.5 V
ID = 6.1 A
On-Resistance vs. Junction Temperature
TJ Junction Temperature (_C)
FIGURE 4. Si3434DV
rDS(on) On-Resiistance
(Normalized)
Application Note 826 VISHAY Vishay Siliconix RECOMMENDED MINIMUM PADS FOR TSOP-G 0.099 (2 510} 0 119 (3 023) Recnmmendefl Mlmmum Pads Dimensmns m \nchesr‘(mm}
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72610
26 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.119
(3.023)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.099
(2.510)
0.064
(1.626)
0.028
(0.699)
0.039
(1.001)
0.020
(0.508)
0.019
(0.493)
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Revision: 01-Jan-2019 1Document Number: 91000
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