ESD7004 Datasheet by ON Semiconductor

View All Related Products | Download PDF Datasheet
ESD7004, SZESD7004 J 0N Semiconducior®
© Semiconductor Components Industries, LLC, 2013
October, 2017 Rev. 5
1Publication Order Number:
ESD7004/D
ESD7004, SZESD7004
SD Protection Diode
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD7004 surge protection is designed to protect high speed
data lines from ESD. Ultralow capacitance and low ESD clamping
voltage make this device an ideal solution for protecting voltage
sensitive high speed data lines. The flowthrough style package
allows for easy PCB layout and matched trace lengths necessary to
maintain consistent impedance between high speed differential lines
such as USB 3.0 and HDMI.
Features
Low Capacitance (0.4 pF Typical, I/O to GND)
Protection for the Following IEC Standards:
IEC 6100042 (Level 4)
Low ESD Clamping Voltage
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AECQ101 Qualified and
PPAP Capable
This is a PbFree Device
Typical Applications
USB 3.0
HDMI
Display Port
eSATA
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ55 to +125 °C
Storage Temperature Range Tstg 55 to +150 °C
Lead Solder Temperature
Maximum (10 Seconds)
TL260 °C
IEC 6100042 Contact (ESD)
IEC 6100042 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
UDFN10
CASE 517BB
PIN CONFIGURATION
AND SCHEMATIC
www.onsemi.com
ESD7004MUTAG UDFN10
(PbFree)
3000 /
Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
4M MG
G
4M = Specific Device Code (tbd)
M = Date Code
G= PbFree Package
I/O I/O I/OI/O GND
N/C N/C N/C N/CGND
14523
10 7 698
(Note: Microdot may be in either location)
Pin 1 Pin 2 Pin 4 Pin 5
Pins 3, 8
=
SZESD7004MUTAG UDFN10
(PbFree)
3000 /
Tape & Reel
TIkRun12 sacs/s Samllee mi le mm 2.50651: Samme m , n 1 W * W ¢ “M in] ‘Io.o‘ ‘ M mons‘ cm ‘4.s M In an; cm 1 791 av nsemi com
ESD7004, SZESD7004
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM I/O Pin to GND 5.0 V
Breakdown Voltage VBR IT = 1 mA, I/O Pin to GND 5.5 V
Reverse Leakage Current IRVRWM = 5 V, I/O Pin to GND 1.0 mA
Clamping Voltage (Note 1) VCIPP = 1 A, I/O Pin to GND (8 x 20 ms pulse) 10 V
Clamping Voltage (Note 2) VCIEC6100042, ±8 KV Contact See Figures 1 and 2 V
Clamping Voltage
TLP (Note 3)
See Figures 6 through 9
VCIPP = 8 A
IPP = 16 A
IPP = 8 A
IPP = 16 A
11.4
15.6
4.5
8.1
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins 0.2 0.3 pF
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND 0.4 0.5 pF
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Figure 1. IEC6100042 +8 KV Contact ESD
Clamping Voltage
Figure 2. IEC6100042 8 KV Contact
Clamping Voltage
www.cnsemi.com
ESD7004, SZESD7004
www.onsemi.com
3
IEC 6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC6100042 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 3. IEC6100042 Spec
Figure 4. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
The following is taken from Application Note
AND8308/D Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8 x 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
<— —4="" 10m52j="" vci="" figure="" 3.="" simplified="" schemat="" www.cnsemi.com="" a="">
ESD7004, SZESD7004
www.onsemi.com
4
Figure 6. Positive TLP IV Curve Figure 7. Negative TLP IV Curve
CURRENT (A)
VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
22
02468101214161820
CURRENT (A)
VOLTAGE (V)
0
2
4
6
8
10
12
14
16
18
20
22
0246810 12 14 16 18 20
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (IV) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP IV curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 6100042
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP IV curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. A typical TLP IV
curve for the ESD7004 is shown in Figures 6 and 7.
Figure 8. Simplified Schematic of a Typical TLP System
DUT
LS
÷
Oscilloscope
Attenuator
10 MW
VC
VM
IM
50 W Coax
Cable
50 W Coax
Cable
35 30 25 20 15 Current (A) —\ IECB kV —TLP8A \ —TLP 16A \ W 4O 60 80 100 120 Tlme (ns)
ESD7004, SZESD7004
www.onsemi.com
5
Figure 9. Comparison Between 8 kV IEC 6100042 and 8 A and 16 A TLP Waveforms
am. my Wm.” mmdammm W vm-mh. n, .zulmm. un- mum m wfin v. “1‘, mm We “gm 4 my, m-y mm; m n-rm- n.
ESD7004, SZESD7004
www.onsemi.com
6
With ESD7004Without ESD
Figure 10. USB3.0 Eye Diagram with and without ESD7004. 5.0 Gb/s, 400 mVPP
With ESD7004Without ESD
Figure 11. HDMI1.4 Eye Diagram with and without ESD7004. 3.4 Gb/s, 400 mVPP
With ESD7004
Without ESD
Figure 12. ESATA3.0 Eye Diagram with and without ESD7004. 6 Gb/s, 400 mVPP
m7 1n5 um 95 an 35 so 75 70 no 115 nu ms 95 as -2« a 2A a 72 as m 154 153 192 2m 2m 26¢ 45 www nnsem am
ESD7004, SZESD7004
www.onsemi.com
7
Test Board
Region
Test Board
Region
DUT
Region
TIME (ps)
Figure 13. USB TDR Measurement. 90 W Differential Impedance Target, 200 ps Rise Time
** USB spec requirement is 90 W ± 10%
TDR max = 92.7 W
DIFFERENTIAL IMPEDANCE (W)
Test Board
Region
Test Board
Region
DUT
Region
** HDMI spec requirement is 100 W ± 15%
TIME (ps)
DIFFERENTIAL IMPEDANCE (W)
TDR min = 97 W
Figure 14. HDMI TDR Measurement. 100 W Differential Impedance Target, 200 ps Rise Time
1 E+06 I E+07 |.E+0 Figure 15. ESD7004 www.cnsemi.com a
ESD7004, SZESD7004
www.onsemi.com
8
Figure 15. ESD7004 Insertion Loss
10
8
6
4
2
0
2
4
1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
ESD7004 IOGND
ESD7004 IOIO
FREQUENCY (Hz)
S21 INSERTION LOSS (dB)
Figure 16. USBGD Standard A Connector Layout Diagram
ESD7004, SZESD7004
www.onsemi.com
9
Figure 16. USB3.0 Standard A Connector Layout Diagram
Vbus
StdA_SSTX+
D
StdA_SSTX
D+
GND_DRAIN
GND
StdA_SSRX+
StdA_SSRX
USB 3.0 Type A
Connector
ESD7004
ESD7L5.0
Figure 17. USB3.0 Micro B Connector Layout Diagram
D
Vbus
ID
D+
MicB_SSTX
GND
GND_DRAIN
MicB_SSTX+
MicB_SSRX
USB 3.0 Micro B
Connector
MicB_SSRX+
ESD7004
ESD7004
-' IIIIIHIIH
ESD7004, SZESD7004
www.onsemi.com
10
Figure 18. HDMI Layout Diagram
HDMI
Type A Connector
SCL
5V
CEC
GND
D0
GND
D0+
D2
D2+
HPD (and HEC_DAT – HDMI1.4)
GND
SDA
CLK
CLK+
GND
D1+
D1
GND
N/C (or HEC_DAT – HDMI1.4)
ESD7004
ESD7004
NUP4114
A
A+
GND
B
B+
GND
GND
e S ATA
Connector
ESD7004
Figure 19. eSATA Layout Diagram
0N Semiwndudw" m o BOTTOM VIEW 1 fl ‘ r ON Samaanuuamn and are Mademavks av Semxcanduclur Cnmpunenls lndusmes LLC dba ON Semxcanduclar ar us suhsxdxanes m xna Umled sxaxaa andJm mhev commas ON Semxcunduclar vesewes ma th| to make changes wuhum Yunhev nauaa to any pruduns nanan ON Semanduc‘nv makes m7 wanamy represenlalmn m guarantee regardmg ma sumahmy at w; manuals can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy ansmg mac xna apphcahan m use no any pmduclnv mum and saaamcauy dwsc‘axms any and au Mammy mcmdmg wnnam nnmauan spema‘ cansequenha‘ m \nmdenla‘ damages ON Sannmnauaxar dues nn| aanyay any hcense under na pa|em nghls nar xna ngma av n|hers
UDFN10 2.5x1, 0.5P
CASE 517BB01
ISSUE O
DATE 17 NOV 2009
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
CSEATING
PLANE
DB
E
0.10 C
A3 A
A1
2X
2X 0.10 C
SCALE 4:1
DIM
A
MIN
MILLIMETERS
0.45
A1 0.00
A3 0.13 REF
b0.15
D2.50 BSC
b2 0.35
E1.00 BSC
e0.50 BSC
PIN ONE
REFERENCE
0.08 C
0.10 C
10X
A0.10 C
NOTE 3
L
e
b2
b
B
5
6
8X
1
10
10X
0.05 C
0.30
L
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
0.45
0.50
DIMENSIONS: MILLIMETERS
1.30
PITCH
0.25
XX MG
G
XXX = Specific Device Code
M = Date Code
G= PbFree Package
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
GENERIC
MARKING DIAGRAM*
10X
0.55
0.05
0.25
0.45
0.40
MAX
A1
A3
DETAIL B
MOLD CMPD
EXPOSED Cu
OPTIONAL
CONSTRUCTION
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
---
L1 0.05
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DETAIL B
DETAIL A
OUTLINE
PACKAGE
A
(Note: Microdot may be in either location)
2X
RECOMMENDED
2X
8X
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON47059E
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
UDFN10 2.5X1, 0.5P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 8002829855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative

Products related to this Datasheet

TVS DIODE 5VWM 10VC 10UDFN
TVS DIODE 5VWM 10VC 10UDFN
TVS DIODE 5VWM 10VC 10UDFN