L5972D Appl Note Datasheet by STMicroelectronics

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November 2013 DocID8827 Rev 3 1/30
AN1517
Application note
Designing with the STEVAL-ISA089V1 high efficiency DC-DC
converter
By Massimiliano Merisio
Introduction
The L5972D device is a step-down monolithic power switching regulator capable of
delivering up to 2 A at output voltages from 1.235 V to 35 V. The operating input voltage
ranges from 4.4 V to 36 V. The device has been designed using BCDV technology and the
power switching element is implemented through a P-channel DMOS transistor. It does not
require a bootstrap capacitor, and the duty cycle can range up to 100%. An internal
oscillator fixes the switching frequency at 250 kHz. This minimizes the LC output filter.
Pulse-by-pulse and frequency foldback overcurrent protection offer effective protection
against short-circuit. Other features are voltage feed-forward, protection against feedback
disconnection, and thermal shutdown. The device is housed in a thermally improved SO-8
package (with 4 pins connected to GND so that the thermal resistance junction to ambient is
reduced to approximately one-half compared with a standard SO-8 package.
Figure 1. Demonstration board
STEVAL-ISA089V1 (SO-8) board dimensions: 34 x 43 mm
Figure 2. Package Figure 3. Pin connection
SO-8
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Contents AN1517
2/30 DocID8827 Rev 3
Contents
1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.3 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID8827 Rev 3 3/30
AN1517 Contents
30
6 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 Buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Compensation network with MLCC (multiple layer ceramic capacitor)
at the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External soft-start network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
List of figures AN1517
4/30 DocID8827 Rev 3
List of figures
Figure 1. Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 3. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. Internal regulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Short-circuit current VIN = 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Short-circuit current VIN = 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. PCB layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. PCB layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19. PCB layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. Junction temperature vs. output current at VIN = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21. Junction temperature vs. output current at VIN = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22. Efficiency vs. output current at VIN = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 23. Efficiency vs. output current at VIN = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 24. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25. Buck-boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 26. Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. MLCC compensation network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 28. Soft-start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
94E}
DocID8827 Rev 3 5/30
AN1517 Pin functions
30
1 Pin functions
Pin description
Figure 4. Block diagram
Table 1. Pin description
N. Name Description
1 OUT Regulator output.
2GND
Ground. Lead connected directly to the frame in order to reduce the junction to ambient
thermal resistance.
3GND
Ground. Lead connected directly to the frame in order to reduce the junction to ambient
thermal resistance.
4 COMP E/A output to be used for frequency compensation.
5FB
Step-down feedback input. Connecting the output voltage directly to this pin results in
an output voltage of 1.235 V. An external resistor divider is required for higher output
voltages (the typical value for the resistor connected between this pin and ground is
4.7 k).
6GND
Ground. Lead connected directly to the frame in order to reduce the junction to ambient
thermal resistance.
7GND
Ground. Lead connected directly to the frame in order to reduce the junction to ambient
thermal resistance.
8V
CC Unregulated DC input voltage.
VOLTAGES
MONITOR
PEAK TO PEAK
CURRENT LIMIT
THERMAL
SHUTDOWN
E/A PWM
1.235V
+
-
-
+
OSCILLATOR
D
Ck
Q
FREQUENCY
SHIFTER
TRIMMING
SUPPLY
1.235V 3.5V
DRIVER
VREF
BUFFER
LPDMOS
POWER
FB
GND
COMP
GND
GND
GND OUT
VCC
AM00028v1
Functional description AN1517
6/30 DocID8827 Rev 3
2 Functional description
The main internal blocks are shown in the device block diagram in Figure 4. They are:
A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3 V
reference voltage is externally available.
A voltage monitor circuit which checks the input and internal voltages.
A fully integrated sawtooth oscillator with a frequency of 250 kHz ± 15%, including also
the voltage feed-forward function and an input/output synchronization pin.
Two embedded current limitation circuits which control the current that flows through
the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle
by cycle if the current reaches an internal threshold, while the frequency shifter reduces
the switching frequency in order to significantly reduce the duty cycle.
A transconductance error amplifier.
A pulse width modulation (PWM) comparator and the relative logic circuitry necessary
to drive the internal power.
A high-side driver for the internal P-MOS switch.
A circuit to implement the thermal protection function.
2.1 Power supply and voltage reference
The internal regulator circuit (shown in Figure 5) consists of a start-up circuit, an internal
voltage “Preregulator”, the “Bandgap voltage reference” and the “Bias block” that provides
current to all the blocks.
The “Starter” gives the start-up currents to the entire device when the input voltage goes
high and the device is enabled (inhibit pin connected to ground).
The “Preregulator block” supplies the “Bandgap cell” with a preregulated voltage VREG that
has a very low supply voltage noise sensitivity.
2.2 Voltages monitor
An internal block continuously senses the VCC, VREF and VBG
. If the voltages go higher than
their thresholds, the regulator begins operating. There is also a hysteresis on the VCC
(UVLO).
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AN1517 Functional description
30
Figure 5. Internal regulator circuit
2.3 Oscillator
Figure 6 shows the block diagram of the oscillator circuit.
The “Clock Generator” provides the switching frequency of the device, which is internally
fixed at 250 kHz. The “Frequency Shifter” block acts to reduce the switching frequency in
case of strong overcurrent or short-circuit. The clock signal is then used in the internal logic
circuitry and is the input of the “Ramp Generator”.
The “Ramp Generator” circuit provides the sawtooth signal, used to for PWM control and the
internal voltage feed-forward.
Figure 6. Oscillator circuit block diagram
2.4 Current protection
The L5972D device has two types of current limit protection: pulse-by-pulse and frequency
foldback.
The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in
Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors.
The smallest one includes a resistor in series, RSENSE. The current is sensed through
RSENSE and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is
switched off until the next falling edge of the internal clock pulse.
STARTER
IC BIAS
PREREGULATOR
BANDGAP
VREG
VREF
AM00006v1
VCC
FREQUENCY
SHIFTER
CLOCK
GENERATOR RAMP
GENERATOR
SYNCHRONIZATOR
CLOCK
RAMP
Ibias_osc
SYNC
t
AM00007v1
FREQUENCY
SHIFTER
CLOCK
GENERATOR RAMP
GENERATOR
SYNCHRONIZER
Functional description AN1517
8/30 DocID8827 Rev 3
Due to this reduction of the ON time, the output voltage decreases.
Since the minimum switch ON time (necessary to avoid a false overcurrent signal) is too
short to obtain a sufficiently low duty cycle at 250 kHz, the output current, in strong
overcurrent or short-circuit conditions, could increase again. For this reason the switching
frequency is also reduced, thus keeping the inductor current under its maximum threshold.
The Frequency Shifter (Figure 6) functions based on the feedback voltage. As the feedback
voltage decreases (due to the reduced duty cycle), the switching frequency decreases also.
Figure 7. Current limitation circuitry
2.5 Error amplifier
The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage
reference (1.235 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage. The output (COMP) is connected to the external
compensation network. The uncompensated error amplifier has the following
characteristics:
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
2.6 PWM comparator and power stage
This block compares the oscillator sawtooth and the error amplifier output signals
generating the PWM signal for the driving stage.
The power stage is a highly critical block, as it functions to guarantee a correct turn ON and
turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise
DRIVER
NOT
A1
PWM
VCC
OUT
A1/A2=95
IL
RSENSE
AM00008v1
IOFF
II
RTH
A2
Table 2. Uncompensated error amplifier characteristics
Description Values
Transconductance 2300 µS
Low frequency gain 65 dB
Minimum sink/source voltage 1500 µA/300 µA
Output voltage swing 0.4 V/3.65 V
Input bias current 2.5 µA
DocID8827 Rev 3 9/30
AN1517 Functional description
30
time of the current at turn ON, is a very critical parameter. At a first approach, it appears that
the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by
the recovery time of the recirculation diode.
In fact, when the current of the power element is equal to the inductor current, the diode
turns OFF and the drain of the power is able to go high. But during its recovery time, the
diode can be considered a high value capacitor and this produces a very high peak current,
responsible for many problems:
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the
board parasitics
Turn ON overcurrent leads to a decrease in the efficiency and system reliability
Major EMI problems
Shorter freewheeling diode life
The fall time of the current during the turn OFF is also critical, as it produces voltage spikes
(due to the parasitics elements of the board) that increase the voltage drop across the
PDMOS.
In order to minimize these problems, a new driving circuit topology has been used and the
block diagram is shown in Figure 8. The basic idea is to change the current levels used to
turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.
This circuitry allows the power switch to be turned OFF and ON quickly and addresses the
freewheeling diode recovery time problem. The gate clamp is necessary to avoid that VGS of
the internal switch goes higher than VGSmax. The ON/OFF Control block protects against
any cross conduction between the supply line and ground.
Figure 8. Driving circuitry
2.7 Thermal shutdown
The thermal shutdown block generates a signal that turns OFF the power stage if the
temperature of the chip goes higher than a fixed internal threshold (150 °C). The sensing
element of the chip is very close to the PDMOS area, ensuring fast and accurate
temperature detection. A hysteresis of approximately 20 °C avoids that the device turns ON
and OFF continuously.
Vgsmax
GATE
STOP
DRIVE
DRAIN
OFF
ON
PDMOS
VOUT
DRAIN
VCC
ILOAD
C
ESR
AM00009v1
IOFF
ION
ON/OFF
CONTROL
CLAMP
L
Additional features and protection AN1517
10/30 DocID8827 Rev 3
3 Additional features and protection
3.1 Feedback disconnection
If the feedback is disconnected, the duty cycle increases towards the maximum allowed
value, bringing the output voltage close to the input supply. This condition could destroy the
load.
To avoid this hazardous condition, the device is turned OFF if the feedback pin is left
floating.
3.2 Output overvoltage protection
Overvoltage protection, or OVP, is achieved by using an internal comparator connected to
the feedback, which turns OFF the power stage when the OVP threshold is reached. This
threshold is typically 30% higher than the feedback voltage.
When a voltage divider is required to adjusting the output voltage (Figure 14 on page 21),
the OVP intervention will be set at:
Equation 1
Where R1 is the resistor connected between the output voltage and the feedback pin, while
R2 is between the feedback pin and ground.
3.3 Zero load
Due to the fact that the internal power is a PDMOS, no bootstrap capacitor is required and
so the device works properly even with no load at the output. In this condition it works in
burst mode, with random burst repetition rate.
V50 Imernal swltch T LC liner external resistor divider w 5: error ampmler , Awmnm
DocID8827 Rev 3 11/30
AN1517 Closing the loop
30
4 Closing the loop
Figure 9. Block diagram of the loop
4.1 Error amplifier and compensation network
The output L-C filter of a step-down converter contributes with 180 degrees phase shift in
the control loop. For this reason a compensation network between the COMP pin and
GROUND is added. The simplest compensation network together with the equivalent circuit
of the error amplifier are shown in Figure 10. RC and CC introduce a pole and a zero in the
open loop gain. CP does not significantly affect system stability but it is useful to reduce the
noise of the COMP pin.
The transfer function of the error amplifier and its compensation network is:
Equation 2
where Avo = Gm · Ro
5,, AV —_ C; Amom m
Closing the loop AN1517
12/30 DocID8827 Rev 3
Figure 10. Error amplifier equivalent circuit and compensation network
The poles of this transfer function are (if Cc >> C0+CP):
Equation 3
Equation 4
where the zero is defined as:
Equation 5
FP1 is the low frequency which sets the bandwidth, while the zero FZ1 is usually put near to
the frequency of the double pole of the L-C filter (see Section 4.2: LC filter). FP2 is usually at
a very high frequency.
4.2 LC filter
The transfer function of the L-C filter is given by:
Equation 6
where RLOAD is defined as the ratio between VOUT and IOUT
.
FP1
1
2R0
Cc
-------------------------------------=
FP2
1
2Rc
C0Cp
+
--------------------------------------------------------=
iEsR- com: Nu 2 2- - L-C
DocID8827 Rev 3 13/30
AN1517 Closing the loop
30
If RLOAD >> ESR, the previous expression of ALC can be simplified and becomes:
Equation 7
The zero of this transfer function is given by:
Equation 8
F0 is the zero introduced by the ESR of the output capacitor and it is very important to
increase the phase margin of the loop.
The poles of the transfer function can be calculated through the following expression:
Equation 9
In the denominator of ALC, the typical second order system equation can be recognized:
Equation 10
If the damping coefficient is very close to zero, the roots of the equation become a double
root whose value is n.
Similarly, for ALC the poles can usually be defined as a double pole whose value is:
Equation 11
4.3 PWM comparator
The PWM gain is given by the following formula:
Equation 12
where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the
minimum value. A voltage feed-forward is implemented to ensure a constant GPWM. This is
obtained by generating a sawtooth waveform directly proportional to the input voltage VCC.
ALC s 1 ESR COUT
s+
LC
OUT
s2ESR COUT
s1++
----------------------------------------------------------------------------------------------=
FPLC1 2
ESR COUT ESR COUT
24LCOUT
2LCOUT
------------------------------------------------------------------------------------------------------------------------------------------=
FPLC
1
2 LC
OUT
----------------------------------------------=
Inn 6n ID I“) 1 m1 anmcy [Hz] 1-10‘ 140’ 110‘ AMaom an
Closing the loop AN1517
14/30 DocID8827 Rev 3
Equation 13
Where K is equal to 0.076. Therefore the PWM gain is also equal to:
Equation 14
This means that even if the input voltage changes, the error amplifier does not change its
value to keep the loop in regulation, thus ensuring a better line regulation and line transient
response.
To sum up, the open loop gain can be written as:
Equation 15
Example 1
Considering RC = 2.7 k, CC = 22 nF and CP = 220 pF, the poles and zeroes of A0 are:
FP1 = 9 Hz
FP2 = 256 kHz
FZ1 = 2.68 kHz
If L = 22 µH, COUT = 100 µF and ESR = 80 m, the poles and zeroes of ALC become:
FPLC = 3.39 kHz
F0 = 19.89 kHz
Finally R1 = 5.6 k and R2 = 3.3 k.
The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12.
Figure 11. Module plot
-1w am 1:: 1m 1 ln’ Flaw-r! [HI] 1 1n‘ A m‘ 1 m‘ AMODOI MA
DocID8827 Rev 3 15/30
AN1517 Closing the loop
30
Figure 12. Phase plot
The cut off frequency and the phase margin are:
Equation 16
FC = 22.8 KHz Phase margin = 39.8°
Application information AN1517
16/30 DocID8827 Rev 3
5 Application information
5.1 Component selection
5.1.1 Input capacitor
The input capacitor must be able to withstand the maximum input operating voltage and the
maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is
squared and the height of each pulse is equal to the output current. The input capacitor has
to absorb all this switching current, which can be up to the load current divided by two (worst
case, with duty cycle of 50%). For this reason, the quality of these capacitors has to be very
high to minimize its power dissipation generated by the internal ESR, thereby improving
system reliability and efficiency. The critical parameter is usually the RMS current rating,
which must be higher than the RMS input current.
The maximum RMS input current (flowing through the input capacitor) is:
Equation 17
Where is the expected system efficiency, D is the duty cycle and IO the output DC current.
This function reaches its maximum value at D = 0.5 and the equivalent RMS current is equal
to IO divided by 2 (considering = 1). The maximum and minimum duty cycles are:
Equation 18
where VF is the freewheeling diode forward voltage and VSW the voltage drop across the
internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max
IRMS going through the input capacitor. Capacitors that can be considered are:
Electrolytic capacitors: These are widely used due to their low price and their
availability in a wide range of RMS current ratings. The only drawback is that,
considering ripple current rating requirements, they are physically larger than other
capacitors.
Ceramic capacitors: If available for the required value and voltage rating, these
capacitors usually have a higher RMS current rating for a given physical dimension
(due to very low ESR). The drawback is the considerably high cost.
Tantalum capacitor: Good, small tantalum capacitors with very low ESR are becoming
more available. However, they can occasionally burn if subjected to very high current
during charge. Therefore, it is better to avoid this type of capacitor for the input filter of
the device. They can, however, be subjected to high surge current when connected to
the power supply.
IRMS IOD2D
2
------------------D2
-------+
=
DMAX
VOUT VF
+
VINMIN VSW
------------------------------------------ =DMIN
VOUT VF
+
VINMAX VSW
--------------------------------------------
=
and
DocID8827 Rev 3 17/30
AN1517 Application information
30
5.1.2 Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the
current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required.
Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain,
which helps to increase the phase margin of the system.
If the zero goes to a very high frequency, its effect is negligible. For this reason, ceramic
capacitors and very low ESR capacitors in general should be avoided.
Tantalum and electrolytic capacitors are usually good for this purpose.
Table 3 below provides a list of some tantalum capacitor manufacturers.
5.1.3 Inductor
The inductor value is very important because it fixes the ripple current flowing through
output capacitor.
The ripple current is usually fixed at 20-40% of IOmax, which is:
0.3 - 0.6 A with IOmax = 1.5 A.
The approximate inductor value is obtained using Equation 19:
Equation 19
where TON is the ON time of the internal switch, given by D · T.
For example, with VOUT = 3.3 V, VIN = 12 V and IO = 0.45 A, the inductor value is about
21 µH.
The peak current through the inductor is given by:
Equation 20
and it can be observed that if the inductor value decreases, the peak current (which must be
lower than the current limit of the device) increases. So, when the peak current is fixed,
a higher inductor value allows a higher value for the output current.
Table 3. Recommended output capacitors
Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)
AVX TPS 100 to 470 4 to 35 50 to 200
KEMET T494/5 100 to 470 4 to 20 30 to 200
Sanyo POSCAP (1)
1. POSCAP capacitors have characteristic very similar to tantalum ones.
TPA/B/C 100 to 470 4 to 16 40 to 80
Sprague 595D 220 to 390 4 to 20 160 to 650
L
VIN VOUT

I
---------------------------------------TON
=
IPK IO
I
2
-----+=
\ EDD RZD R1 \ W \ oo o o co m\ Gnd Ammsm
Application information AN1517
18/30 DocID8827 Rev 3
In Table 4, some inductor manufacturers are listed.
5.2 Layout considerations
The layout of switching DC-DC converters is very important to minimize noise and
interference. Power-generating portions of the layout are the main cause of noise and so
high switching current loop areas should be kept as small as possible and lead lengths as
short as possible.
High impedance paths (in particular the feedback connections) are susceptible to
interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 13.
The input and output loops are minimized to avoid radiation and high frequency resonance
problems. The feedback pin connections to the external divider are very close to the device
to avoid pick-up noise. Moreover, the GND pin of the device is connected to the ground
plane directly with VIA on the bottom side of the PCB.
Figure 13. Layout example
Table 4. Inductor selection
Manufacturer Series Inductor value (µH) Saturation current (A)
Coilcraft DO3316 33 to 47 1.6 to 2
Coiltronics UP2B 33 to 47 1.7 to 2
BI HM76-3 33 to 47 2 to 2.5
EPCOS B82476 33 to 47 1.6 to 2
Wurth Elektronik 744561 33 to 47 1.6 to 2
L5972D
Cin D Cout
L
to output voltage
Vin Vout
Gnd
R1
R2
1
45
8
VERY SMALL HIGH CURRENT
CIRCULATING PATH TO MINIMIZE
RADIATION AND HIGH FREQUENCY
RESONANCE PROBLEMS
OUTPUT CAPACITOR
DIRECTLY CONNECTED
TO HEAVY GROUND
COMPENSATION NETWORK FAR
FROM HIGH CURRENT PATHS
MINIMUN SIZE OF FEEDBACK
PIN CONNECTIONS TO AVOID
PICKUP
CONNECTION TO
GROUNDPLANE
THROUGH VIAS
AM00131v1
L5972D
DocID8827 Rev 3 19/30
AN1517 Application information
30
5.3 Thermal considerations
The dissipated power of the device is tie to three different sources:
switch losses due to the not negligible RDSON. These are equal to:
Equation 21
where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between VOUT and VIN, but in practice it is substantially higher than this value to
compensate for the losses of the overall application. For this reason, the switching losses
related to the RDSON increase compared to an ideal case.
Switching losses due to turning ON and OFF. These are derived using Equation 22:
Equation 22
Where TON and TOFF are the overlap times of the voltage across the power switch and the
current flowing into it during the turn ON and turn OFF phases. TSW is the equivalent
switching time.
Quiescent current losses.
Equation 23
where IQ is the quiescent current.
Example 2
–V
IN = 5 V
–V
OUT = 3.3 V
–I
OUT = 1.5 A
RDSON has a typical value of 0.25 at 25 °C and increases up to a maximum value of 0.5
at 150 °C. We can consider a value of 0.4 .
TSW is approximately 70 ns. IQ has a typical value of 2.5 mA at VIN = 12 V. The overall
losses are:
Equation 24
The junction temperature of device will be:
Equation 25
Where TA is the ambient temperature and RthJ-A is the thermal resistance junction to
ambient.
PON RDSON IOUT

2
D=
PSW VIN IOUT
TON TOFF
+
2
-----------------------------------------FSW
VIN IOUT
TSW
FSW
==
PQVIN IQ
=
PTOT RDSON IOUT

2DV
IN IOUT TSW FSW VIN IQ=++=
0.4 1.520.7 51.57010
9250 10352.510
30.9W+  +=
Application information AN1517
20/30 DocID8827 Rev 3
Considering that the device in SO-8 (4+2+2) package mounted on board with a good
groundplane has a thermal resistance junction to ambient (RthJ-A) of about 62 °C/W and
considering an ambient temperature of about 70 °C.
Equation 26
5.4 Short-circuit protection
In overcurrent protection mode, when the peak current reaches the current limit, the device
reduces the TON down to its minimum value (approximately 250 ns) and the switching
frequency to approximately one third of its nominal value (see Section 2.4: Current
protection on page 7). In these conditions, the duty cycle is strongly reduced and, in most
applications, this is enough to limit the current to ILIM. In any event, in case of heavy short-
circuit at the output (VOUT = 0 V) and depending on the application conditions (VCC value
and parasitic effect of external components), the current peak could reach values higher
than ILIM.
This can be understood considering the inductor current ripple during the ON and OFF
phases:
ON phase
Equation 27
OFF phase
Equation 28
where VD is the voltage drop across the diode, and DCRL is the series resistance of the
inductor.
In short-circuit conditions VOUT is negligible. So, during the TOFF
, the voltage applied to the
inductor is very small and it may be that the current ripple in this phase does not
compensate for the current ripple during the TON.
The maximum current peak can be easily measured through the inductor with VOUT = 0 V
(short-circuit) and VCC = VINmax. In cases where the application must sustain the short-
circuit condition for an extended period, the external components (mainly the inductor and
diode) must be selected based on this value.
TJ70 0.9 62 128C+=
IL
VIN Vout DCRLI
L
---------------------------------------------------------------------TON
=
IL
VDVout DCRLI++
L
------------------------------------------------------------------ TOFF
=
\ \ a -\ x q Minx] xx $13M 4 J A \l_\ ¢ I} 34:05 nu mm II >—:r—| f
DocID8827 Rev 3 21/30
AN1517 Application information
30
Figure 14. Short-circuit current VIN = 25 V
Figure 15. Short-circuit current VIN = 30 V
In Figure 14 and Figure 15, for example, it can be observed that when the input voltage
increases for a given component list, the current peak increases also. The current limit is
immediately triggered but the current peak increases until the current ripple during the TOFF
is equal to the current ripple during the TON.
5.5 Application circuit
Figure 16 shows the demonstration board application circuit for the device in the SMD
version, where the input supply voltage, VCC, can range from 4.4 V to 25 V due to the rated
voltage of the input capacitor and the output voltage is adjustable from 1.235 V to VCC.
Figure 16. Demonstration board application circuit
I
L
Vout
I
LIMIT
I
L
Vout
I
LIMIT
8
2
45
1
7
L5972D
C1
10μF
25V
CERAMIC
C2
100μF
10V
VOUT=3.3V
VIN = 4.4V to 25V
R1
5.6K
R2
3.3K
R3
4.7K
C4
22nF
C3
220pF
3
L1 33μH
6
D1
STPS2L25U
COMP
VCC OUT
FB
GND
AM00027v1
L5972D
Application information AN1517
22/30 DocID8827 Rev 3
Table 5. Component list
Reference Part number Description Manufacturer
C1 10 µF, 25 V Tokin
C2 POSCAP 10TPB100M 100 µF, 10 V SANYO
C3 C1206C221J5GAC 220 pF, 5%, 50 V KEMET®
C4 C1206C223K5RAC 22 nF, 10%, 50 V KEMET
R1 5.6 K, 1%, 0.1 W 0603 Neohm®
R2 3.3 K, 1%, 0.1 W 0603 Neohm
R3 4.7 K, 1%, 0.1 W 0603 Neohm
D1 STPS2L25U 2 A, 25 V STMicroelectronics®
L1 DO3316P-333 33 µH, 2.1 A Coilcraft
317:3ng Kyl®
DocID8827 Rev 3 23/30
AN1517 Application information
30
Figure 17. PCB layout (component side)
Figure 18. PCB layout (bottom side)
Figure 19. PCB layout (front side)
Application information AN1517
24/30 DocID8827 Rev 3
In Figure 20 to Figure 23 are some graphs showing the Tj versus output current in different
input and output voltage conditions.
Figure 20. Junction temperature vs. output
current at VIN = 5 V
Figure 21. Junction temperature vs. output
current at VIN = 12 V
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io(A)
TJ(°C)
Vin=5V
Tamb.=25 °C
Vo=1.8V
Vo=2.5V Vo=3.3V
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io(A)
TJ(°C)
Vo=2.5V
Vo=3.3V
Vo=5V
Vin=12V
Tamb= 25°C
Figure 22. Efficiency vs. output current
at VIN = 5 V
Figure 23. Efficiency vs. output current
at VIN = 12 V
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7
Io (A)
Efficiency (%)
Vo=1.8V
Vo=2.5V
Vo=3.3V
Vin=5V
Vo=1.8V
Vo=2.5V
Vo=3.3V
70
72
74
76
78
80
82
84
86
88
90
92
94
96
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7
Io (A)
Efficiency (%)
Vin=12V
Vo=2.5V
Vo=3.3V
Vo=5V
Vin=12V
Vo=2.5V
Vo=3.3V
Vo=5V
gll—r EC \ 5g 331
DocID8827 Rev 3 25/30
AN1517 Application ideas
30
6 Application ideas
Positive buck-boost regulator
The device can be used to implement an step-up/down converter with a positive output
voltage. Figure 24 shows the schematic diagram of this topology for an output voltage of
12 V.
The input voltage can range from 5 V and 35 V. The output voltage is given by
VO = VIN · D / (1 - D), where D is the duty cycle. The maximum output current is given by
IOUT = 1 × (1 - D). The current capability is reduced by the term (1 - D) and so, for example,
with a duty cycle of 0.5, the maximum output current deliverable to the load is 0.75 A. This is
due to the fact that the current flowing through the internal power switch is delivered to the
output only during the OFF phase.
Figure 24. Positive buck-boost regulator
7 Buck-boost regulator
In Figure 25, the schematic circuit for a standard buck-boost topology is shown. The output
voltage is given by VO = -VIN · D / (1 - D). The maximum output current is equal to
IOUT = 1 × (1 - D), for the same reason as that of the up-down converter. An important thing
to take in account is that the ground pin of the device is connected to the negative output
voltage. Therefore, the device is subjected to a voltage equal to VIN - VO, which has to be
lower than 36 V (the maximum operating input voltage).
Figure 25. Buck-boost regulator
VIN=5V
C1
10uF
10V
Ceramic
D1
STPS2L25U
Vcc
COMP
GND
OUT
FB
L5972D
1
3
75
6
4
8
2
R3
4.7k
L1
33uH
24k
2.7k
C3
22nF
C4
100uF
16V
VOUT=12V/0.45A
C2
220pF
D2
STPS2L25U
M1
STN4NE03L
AM00136v1
L5972D
VIN=5V
C1
10uF
10V
Ceramic
D1
STPS2L25U
Vcc
COMP
GND
OUT
FB
L5972D
1
3
7
5
6
4
8
2
R3
4.7k
L1
33uH
2.7k
24k
C4
22nF
C5
100uF
16V
VOUT=-12V/0.45A
C3
220pF
C2
10uF
25V
Ceramic
AM00135v1
L5972D
Buck-boost regulator AN1517
26/30 DocID8827 Rev 3
Dual output voltage with auxiliary winding
When two output voltages are required, it is possible to create a dual output voltage
converter by using a coupled inductor. During the ON phase the current is delivered to VOUT
while D2 is reverse-biased.
During the OFF phase, the current is delivered through the auxiliary winding to the output
voltage VOUT1. This is possible only if the magnetic core has stored sufficient energy. So, to
be certain that the application is working properly, the load related to the second output
VOUT1 should be much lower than the load related to VOUT
.
Figure 26. Dual output voltage with auxiliary winding
VIN=12V
C1
10uF
25V
D1
STPS2L25U
Vcc
COMP
GND
OUT
FB
L5972D
1
3
7
5
6
4
8
2
R3
4.7k
C3
22nF
C4
100uF
10V
VOUT=3.3V
C2
220pF
VOUT1=5V
50mA
D2
STPS2L25U
C5
47uF
10V
N1
N2
n=N1/N2=2
AM00137v1
L5972D
DocID8827 Rev 3 27/30
AN1517 Compensation network with MLCC (multiple layer ceramic capacitor) at the output
30
8 Compensation network with MLCC (multiple layer
ceramic capacitor) at the output
MLCCs with values in the range of 10 µF - 22 µF and rated voltages in the range of
10 V - 25 V are available today at relatively low cost from many manufacturers.
These capacitors have very low ESR values (a few m) and thus are occasionally used for
the output filter in order to reduce the voltage ripple and the overall size of the application.
However, a very low ESR value affects the compensation of the loop (see Section 4:
Closing the loop on page 11) and in order to keep the system stable, a more complicated
compensation network may be required. Figure 27 shows an example of compensation
network that stabilizes the system with ceramic capacitors at the output (the optimum
component value depends on the application).
Figure 27. MLCC compensation network example
External soft-start network
At the startup, the device can quickly increase the current up to the current limit in order to
charge the output capacitor. If a soft ramp-up of the output voltage is required, an external
soft-start network can be implemented as shown in Figure 28. The capacitor C is charged
up to an external reference (through R), and the BJT clamps the COMP pin.
This clamps the duty cycle, limiting the slew rate of the output voltage.
4.7uH
L1
VIN=5V
C1
MLCC
10uF
D1
Vcc
COMP
GND
OUT
FB
1
37 5
6
4
8
2
R3=2.2K
Coilcraft
C4=4.7nF C2
MLCC
22uF
6.3V
L5972D
VOUT=2.1V
C5=2.7nF
R4=470
R1=3.3K
C3=220pF
R2=4K7
STPS2L25U
4.7uH
L1
VIN=5V
C1
MLCC
10uF
D1
Vcc
COMP
GND
OUT
FB
1
37 5
6
4
8
2
R3=2.2K
Coilcraft
C4=4.7nF C2
MLCC
22uF
6.3V
L5972D
VOUT=2.1V
C5=2.7nF
R4=470
R1=3.3K
C3=220pF
R2=4K7
STPS2L25U
AM00138v1
L5972D
Compensation network with MLCC (multiple layer ceramic capacitor) at the output AN1517
28/30 DocID8827 Rev 3
Figure 28. Soft-start network example
L1
VIN=4.4V to 25V
C1
10uF
25V
CERAMIC
D1
STPS2L25U
Vcc
COMP
GND
OUT
FB
1
3
7
5
6
4
8
2
R3=4.7K
33uH
Coilcraft
C4=22nF C2
100uF
10V
L5972D
VOUT=3.3V
C3=220pF
VREF
R=4K7
Css=2.7nF
BC327
R1=5.6K
R2=3.3K
L1
VIN=4.4V to 25V
C1
10uF
25V
CERAMIC
D1
STPS2L25U
Vcc
COMP
GND
OUT
FB
1
3
7
5
6
4
8
2
R3=4.7K
33uH
Coilcraft
C4=22nF C2
100uF
10V
L5972D
VOUT=3.3V
C3=220pF
VREF
R=4K7
VREF
R=4K7
Css=2.7nF
BC327
R1=5.6K
R2=3.3K
AM00139v1
L5972D
DocID8827 Rev 3 29/30
AN1517 Revision history
30
9 Revision history
Table 6. Document revision history
Date Revision Changes
08-Nov-2006 1 First issue
28-May-2007 2
The document has been reformatted
Section 4: Closing the loop modified
Minor text changes
13-Nov-2013 3
Updated title and Figure 1 on page 1 (replaced L5970 by STEVAL-
ISA089V1).
Updated Figure 17, Figure 18 and Figure 19 on page 23 (replaced
L5970 by L5972D device).
Updated Figure 3 (replaced SYNC, INH, and VREF pins by GND,
minor corrections).
Updated Section 2.4 (replaced L5973AD device by L5972D
device).
Updated titles of Figure 20 to Figure 23 (added VIN = 5/12 V, in
Figure 22 replaced junction temperature by efficiency).
Minor modifications throughout document.
AN1517
30/30 DocID8827 Rev 3
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