MCP6H01,2,4 Datasheet by Microchip Technology

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MCP6H01I2I4 MICROCHIP BEES EEE4 mEEEEEE
2010-2011 Microchip Technology Inc. DS22243D-page 1
MCP6H01/2/4
Features:
Input Offset Voltage: ±0.7 mV (typical)
Quiescent Current: 135 µA (typical)
Common Mode Rejection Ratio: 100 dB (typical)
Power Supply Rejection Ratio: 102 dB (typical)
Rail-to-Rail Output
Supply Voltage Range:
- Single-Supply Operation: 3.5V to 16V
- Dual-Supply Operation: ±1.75V to ±8V
Gain Bandwidth Product: 1.2 MHz (typical)
Slew Rate: 0.8V/µs (typical)
Unity Gain Stable
Extended Temperature Range: -40°C to +125°C
No Phase Reversal
Applications:
Automotive Power Electronics
Industrial Control Equipment
Battery Powered Systems
Medical Diagnostic Instruments
Design Aids:
SPICE Macro Models
•FilterLab
® Software
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
Description:
Microchip’s MCP6H01/2/4 family of operational amplifi-
ers (op amps) has a wide supply voltage range of 3.5V
to 16V and rail-to-rail output operation. This family is
unity gain stable and has a gain bandwidth product of
1.2 MHz (typical). These devices operate with a
single-supply voltage as high as 16V, while only
drawing 135 µA/amplifier (typical) of quiescent current.
The MCP6H01/2/4 family is offered in single
(MCP6H01), dual (MCP6H02) and quad (MCP6H04)
configurations. All devices are fully specified in
extended temperature range from -40°C to +125°C.
Package Types
Difference Amplifier
R1
VOUT
R2
R1
VREF
R2
VDD
V1
V2
MCP6H01
* Includes Exposed Thermal Pad (EP); see Table 3-1.
1
2
3
4
8
7
6
5
EP
9
VDD
VOUT
NC
NC
VIN+
VIN
VSS
NC 1
2
3
4
8
7
6
5
EP
9
VOUTB
VINB
VINB+
VDD
VINA+
VINA
VSS
VOUTA
VINA+
VINA
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB
VINB+
VIN+
VIN
VSS
1
2
3
4
8
7
6
5
NC NC
VDD
VOUT
NC
MCP6H01
SOIC
MCP6H02
SOIC
MCP6H01
2x3 TDFN
MCP6H02
2x3 TDFN
MCP6H04
SOIC, TSSOP
VINA+
VINA
VDD
1
2
3
4
14
13
12
11
VOUTA VOUTD
VIND
VIND+
VSS
VINB+510 VINC+
VINB69
VOUTB 7 8 VOUTC
VINC
VIN+VIN
1
2
3
5
4
VDD
VOUT
MCP6H01
SC70-5, SOT 23-5
VSS
1.2 MHz, 16V Op Amps
MCP6H01/2/4
DS22243D-page 2 2010-2011 Microchip Technology Inc.
NOTES:
VCM VDD our VDD VL VDD RL Vos TA
2010-2011 Microchip Technology Inc. DS22243D-page 3
MCP6H01/2/4
1.0 ELECTRICAL CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD – VSS..........................................................................17V
Current at Input Pins......................................................±2 mA
Analog Inputs (VIN+, VIN-)††.............VSS 1.0V to VDD +1.0V
All Other Inputs and Outputs ............VSS 0.3V to VDD +0.3V
Difference Input Voltage..........................................VDD – VSS
Output Short-Circuit Current...................................continuous
Current at Output and Supply Pins ..............................±65 mA
Storage Temperature.....................................-65°C to +150°C
Maximum Junction Temperature (TJ)...........................+150°C
ESD protection on all pins (HBM; MM) 2 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See 4.1.2 “Input Voltage Limits”.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V, VSS = GND, TA= +25°C,
VCM =V
DD/2 – 1.4V, VOUT VDD/2, VL=V
DD/2 and RL=10kto VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -3.5 ±0.7 +3.5 mV
Input Offset Drift with Temperature VOS/TA—±2.5µV/°CT
A= -40°C to +125°C
Power Supply Rejection Ratio PSRR 87 102 dB
Input Bias Current and Impedance
Input Bias Current IB—10pA
IB—600—pAT
A= +85°C
IB—1025nAT
A= +125°C
Input Offset Current IOS —±1pA
Common Mode Input Impedance ZCM —10
13||6 — ||pF
Differential Input Impedance ZDIFF —10
13||6 — ||pF
Common Mode
Common Mode Input Voltage Range VCMR VSS 0.3 — VDD 2.3 V
Common Mode Rejection Ratio CMRR 78 93 dB VCM = -0.3V to 1.2V,
VDD =3.5V
82 98 dB VCM = -0.3V to 2.7V,
VDD =5V
84 100 dB VCM = -0.3V to 12.7V,
VDD =15V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 95 115 dB 0.2V < VOUT <(VDD
0.2V)
VCM VDD OUT VDD VL VDD DD VCM VDD
MCP6H01/2/4
DS22243D-page 4 2010-2011 Microchip Technology Inc.
AC ELECTRICAL SPECIFICATIONS
Output
High-Level Output Voltage VOH 3.490 3.495 V VDD =3.5V
0.5V input overdrive
4.985 4.993 V VDD =5V
0.5V input overdrive
14.970 14.980 V VDD =15V
0.5V input overdrive
Low-Level Output Voltage VOL 0.005 0.010 V VDD =3.5V
0.5 V input overdrive
0.007 0.015 V VDD =5V
0.5 V input overdrive
0.020 0.030 V VDD =15V
0.5 V input overdrive
Output Short-Circuit Current ISC —±27mAV
DD =3.5V
—±45mAV
DD =5V
—±50mAV
DD =15V
Power Supply
Supply Voltage VDD 3.5 16 V Single-supply operation
±1.75 ±8 V Dual-supply operation
Quiescent Current per Amplifier IQ 125 175 µA IO=0, V
DD =3.5V
VCM =V
DD/4
130 180 µA IO=0, V
DD =5V
VCM =V
DD/4
135 185 µA IO=0, V
DD =15V
VCM =V
DD/4
Electrical Characteristics: Unless otherwise indicated, TA= +25°C, VDD = +3.5V to +16V, VSS = GND,
VCM =V
DD/2 - 1.4V, VOUT VDD/2, VL=V
DD/2, RL=10kto VL and CL= 60 pF. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP 1.2 MHz
Phase Margin PM 57 °C G = +1V/V
Slew Rate SR 0.8 V/µs
Noise
Input Noise Voltage Eni 12 µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —35—nV/Hz f = 1 kHz
—30nV/Hz f = 10 kHz
Input Noise Current Density ini —1.9fA/Hz f = 1 kHz
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V, VSS = GND, TA= +25°C,
VCM =V
DD/2 – 1.4V, VOUT VDD/2, VL=V
DD/2 and RL=10kto VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
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2010-2011 Microchip Technology Inc. DS22243D-page 5
MCP6H01/2/4
TEMPERATURE SPECIFICATIONS
1.2 Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT (refer to Equation 1-1). Note that VCM is not the
circuit’s common mode voltage ((VP+V
M)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
EQUATION 1-1:
FIGURE 1-1: AC and DC Test Circuit for
Most Specifications.
Electrical Characteristics: Unless otherwise indicated, VDD = +3.5V to +16V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 +125 °C Note 1
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 JA —331°C/W
Thermal Resistance, 5L-SOT-23 JA —256°C/W
Thermal Resistance, 8L-2x3 TDFN JA —41°C/W
Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W
Thermal Resistance, 14L-SOIC JA —95.3°C/W
Thermal Resistance, 14L-TSSOP JA —100°C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
GDM RFRG
=
VCM VPVDD 2+2=
VOUT VDD 2VPVM
VOST 1GDM
+++=
Where:
GDM = Differential Mode Gain (V/V)
VCM = Op Amp’s Common Mode
Input Voltage (V)
VOST = Op Amp’s Total Input Offset
Voltage (mV)
VOST VINVIN+
=
VDD
RGRF
VOUT
VM
CB2
CL
RL
VL
CB1
100 k
100 k
RGRF
VDD/2
VP
100 k
100 k
60 pF10 k
F100 nF
VIN–
VIN+
CF
6.8 pF
CF
6.8 pF
MCP6H0X
MCP6H01/2/4
DS22243D-page 6 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS22243D-page 7
MCP6H01/2/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +3.5V to +16V, VSS = GND, VCM =V
DD/2 - 1.4V, VOUT VDD/2,
VL=V
DD/2, RL=10kto VL and CL=60pF.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage.
FIGURE 2-4: Input Offset Voltage vs.
Common Mode Input Voltage.
FIGURE 2-5: Input Offset Voltage vs.
Common Mode Input Voltage.
FIGURE 2-6: Input Offset Voltage vs.
Output Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
3%
6%
9%
12%
15%
18%
21%
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Input Offset Voltage (mV)
Percentage of Occurences
2550 Samples
0%
5%
10%
15%
20%
25%
30%
35%
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
Input Offset Voltage Drift (µV/°C)
Percentage of Occurences
2550 Samples
TA = - 40°C to +125°C
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.50.00.51.01.52.02.5
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 3.5V
Representative Part
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 5V
Representative Part
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.5 1.5 3.5 5.5 7.5 9.5 11.5 13.5 15.5
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
T
A = +125°C
T
A = +85°C
T
A = +25°C
T
A = -40°C
VDD = 15V
Representative Part
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
0 2 4 6 8 10121416
Output Voltage (V)
Input Offset Voltage (µV)
V
DD = 15V
VDD = 3.5V
Representative Part
VDD = 5V
MCP6H01/2/4
DS22243D-page 8 2010-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +3.5V to +16V, VSS = GND, VCM =V
DD/2 - 1.4V, VOUT VDD/2,
VL=V
DD/2, RL=10kto VL and CL=60pF.
FIGURE 2-7: Input Offset Voltage vs.
Power Supply Voltage.
FIGURE 2-8: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-9: Input Noise Voltage Density
vs. Common Mode Input Voltage.
FIGURE 2-10: CMRR, PSRR vs.
Frequency.
FIGURE 2-11: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-12: Input Bias, Offset Currents
vs. Ambient Temperature.
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
024681012141618
Power Supply Voltage (V)
Input Offset Voltage (µV)
TA = +12C
TA = +85°C
TA = +25°C
TA = -40°C
Representative Part
10
100
1,000
1 10 100 1000 10000 100000
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
1 10 100 1k 10k 100k
10
15
20
25
30
35
40
45
50
-113579111315
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/ Hz)
f = 1 kHz
VDD = 16V
20
30
40
50
60
70
80
90
100
110
120
10 100 1000 10000 100000 1000000
Frequency (Hz)
CMRR, PSRR (dB)
10 100 1k 10k 100k 1M
CMRR
PSRR+
PSRR-
Representative Part
50
60
70
80
90
100
110
120
130
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CMRR, PSRR (dB)
PSRR
CMRR @ VDD = 15V
@ VDD = 5V
@ VDD = 3.5V
1
10
100
1000
10000
100000
25
35
45
55
65
75
85
95
105
115
125
Ambient Temperature (°C)
Input Bias and Offset Currents
(A)
Input Bias Current
Input Offset Current
VDD = 15V
100n
10n
1n
100p
10p
1p
Frequency (Hzp
2010-2011 Microchip Technology Inc. DS22243D-page 9
MCP6H01/2/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +3.5V to +16V, VSS = GND, VCM =V
DD/2 - 1.4V, VOUT VDD/2,
VL=V
DD/2, RL=10kto VL and CL=60pF.
FIGURE 2-13: Input Bias Current vs.
Common Mode Input Voltage.
FIGURE 2-14: Quiescent Current vs.
Ambient Temperature.
FIGURE 2-15: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-16: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-17: DC Open-Loop Gain vs.
Power Supply Voltage.
FIGURE 2-18: DC Open-Loop Gain vs.
Output Voltage Headroom.
1
10
100
1000
10000
100000
0 2 4 6 8 10 12 14 16
Common Mode Input Voltage (V)
Input Bias Current (A)
TA = +125°C
TA = +85°C
VDD = 15V
100n
10n
1n
100
p
10
p
1p
80
90
100
110
120
130
140
150
160
170
180
190
200
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Quiescent Current
(µA/Amplifier)
VDD = 15V
VDD = 5V
VDD = 3.5V
0
20
40
60
80
100
120
140
160
180
200
0 2 4 6 8 10121416
Power Supply Voltage (V)
Quiescent Current
(µA/Amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Open-Loop Gain
Open-Loop Phase
0.1 1 10 100 1k 10k 100k 1M 10M
80
90
100
110
120
130
140
150
160
3 5 7 9 11131517
Power Supply Voltage (V)
DC-Open Loop Gain (dB)
VSS + 0.2V < VOUT < VDD - 0.2V
80
90
100
110
120
130
140
150
0.00 0.05 0.10 0.15 0.20 0.25 0.30
Output Voltage Headroom (V)
VDD - VOH or VOL - VSS
DC-Open Loop Gain (dB)
VDD = 15V
VDD = 5V
VDD = 3.5V
Frequency (Hz)
MCP6H01/2/4
DS22243D-page 10 2010-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +3.5V to +16V, VSS = GND, VCM =V
DD/2 - 1.4V, VOUT VDD/2,
VL=V
DD/2, RL=10kto VL and CL=60pF.
FIGURE 2-19: Channel-to-Channel
Separation vs. Frequency (MCP6H02 only).
FIGURE 2-20: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-21: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-22: Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-23: Output Voltage Swing vs.
Frequency.
FIGURE 2-24: Output Voltage Headroom
vs. Output Current.
40
60
80
100
120
140
160
100 1000 10000 100000
Frequency (Hz)
Channel to Channel
Separation (dB)
100 1k 10k 100k
Input Referred
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
0
20
40
60
80
100
120
140
160
180
Phase Margin (°)
Gain Bandwidth Product
Phase Margin
DD = 3.5V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
0
20
40
60
80
100
120
140
160
180
Phase Margin (°)
Gain Bandwidth Product
Phase Margin
V
DD = 15V
0
10
20
30
40
50
60
70
0 2 4 6 8 10 12 14 16
Power Supply Voltage (V)
Output Short Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.1
1
10
100
100 1000 10000 100000 1000000
Frequency (Hz)
Output Voltage Swing (VP-P)
VDD = 3.5V
VDD = 5V
100 1k 10k 100k 1M
VDD = 15V
1
10
100
1000
10000
0.01 0.1 1 10 100
Output Current (mA)
Output Voltage Headroom (mV)
VDD - VOH
VOL - V
SS
VDD = 15V
%
2010-2011 Microchip Technology Inc. DS22243D-page 11
MCP6H01/2/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +3.5V to +16V, VSS = GND, VCM =V
DD/2 - 1.4V, VOUT VDD/2,
VL=V
DD/2, RL=10kto VL and CL=60pF.
FIGURE 2-25: Output Voltage Headroom
vs. Output Current.
FIGURE 2-26: Output Voltage Headroom
vs. Output Current.
FIGURE 2-27: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-28: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-29: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-30: Slew Rate vs. Ambient
Temperature.
0.1
1
10
100
1000
0.01 0.1 1 10 100
Output Current (mA)
Output Voltage Headroom (mV)
VDD - VOH
VOL - V
SS
VDD = 5V
0.1
1
10
100
1000
0.0 0.1 1.0 10.0
Output Current (mA)
Output Voltage Headroom (mV)
VDD - VOH
VOL - V
SS
VDD = 3.5V
15
16
17
18
19
20
21
22
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom (mV)
VDD - VOH
VOL - VSS
VDD = 15V
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom (mV)
VDD - VOH
VOL - VSS
VDD = 5V
2
3
4
5
6
7
8
-50-250 255075100125
Ambient Temperature (°C)
Output Voltage Headroom (mV)
VDD - VOH
VOL - VSS VDD = 3.5V
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling Edge, VDD = 15V
Rising Edge, VDD = 15V
MCP6H01/2/4
DS22243D-page 12 2010-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +3.5 V to +16 V, VSS = GND, VCM =V
DD/2 - 1.4V, VOUT VDD/2,
VL=V
DD/2, RL=10kto VL and CL=60pF.
FIGURE 2-31: Slew Rate vs. Ambient
Temperature.
FIGURE 2-32: Small Signal Non-Inverting
Pulse Response.
FIGURE 2-33: Small Signal Inverting Pulse
Response.
FIGURE 2-34: Large Signal Non-Inverting
Pulse Response.
FIGURE 2-35: Large Signal Inverting Pulse
Response.
FIGURE 2-36: The MCP6H01/2/4 Shows
No Phase Reversal.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling Edge, VDD = 5V
Rising Edge, VDD = 5V
Falling Edge, VDD = 3.5V
Rising Edge, VDD = 3.5V
Time (2 µs/div)
Output Voltage (20 mv/div)
VDD = 15V
G = +1V/V
Time (2 µs/div)
Output Voltage (20 mv/div)
VDD = 15V
G = -1V/V
0
2
4
6
8
10
12
14
16
Time (20 µs/div)
Output Voltage (V)
VDD = 15V
G = +1V/V
0
2
4
6
8
10
12
14
16
Time (20 µs/div)
Output Voltage (V)
VDD = 15V
G = -1V/V
-1
1
3
5
7
9
11
13
15
17
Time (0.1 ms/div)
Output Voltage (V)
VDD = 15V
G = +2V/V
OUT
VIN
2010-2011 Microchip Technology Inc. DS22243D-page 13
MCP6H01/2/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +3.5 V to +16 V, VSS = GND, VCM =V
DD/2 - 1.4V, VOUT VDD/2,
VL=V
DD/2, RL=10kto VL and CL=60pF.
FIGURE 2-37: Closed Loop Output
Impedance vs. Frequency.
FIGURE 2-38: Measured Input Current vs.
Input Voltage (below VSS).
1
10
100
1000
1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Frequency (Hz)
Closed Loop Output
Impedance ()
GN:
101V/V
11V/V
1V/V
10 100 1k 10k 100k 1M
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VIN (V)
-IIN (A)
1m
100
µ
10
µ
100n
10n
1n
100
p
10
p
1p
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
MCP6H01/2/4
DS22243D-page 14 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS22243D-page 15
MCP6H01/2/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.3 Power Supply Pins
The positive power supply (VDD) is 3.5V to 16V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts can be used in single-supply
operation or dual-supply operation. Also, VDD will need
bypass capacitors.
3.4 Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
MCP6H01 MCP6H02 MCP6H04
Symbol Description
SC70-5,
SOT-23-5 SOIC2x3TDFNSOIC2x3TDFN SOIC,
TSSOP
16611 1V
OUT, VOUTA Analog Output (op amp A)
42222 2V
IN–, VINA Inverting Input (op amp A)
33333 3V
IN+, VINA+ Non-inverting Input (op amp A)
57788 4 V
DD Positive Power Supply
——— 5 5 5 V
INB+ Non-inverting Input (op amp B)
——— 6 6 6 VINBInverting Input (op amp B)
——— 7 7 7 V
OUTB Analog Output (op amp B)
——— 8 V
OUTC Analog Output (op amp C)
——— 9 V
INC Inverting Input (op amp C)
——— 10 V
INC+ Non-inverting Input (op amp C)
24444 11 V
SS Negative Power Supply
——— 12 V
IND+ Non-inverting Input (op amp D)
——— 13 V
IND Inverting Input (op amp D)
——— 14 V
OUTD Analog Output (op amp D)
1, 5, 8 1, 5, 8 NC No Internal Connection
9 9 EP Exposed Thermal Pad (EP); must
be connected to VSS.
MCP6H01/2/4
DS22243D-page 16 2010-2011 Microchip Technology Inc.
NOTES:
2010-2011 Microchip Technology Inc. DS22243D-page 17
MCP6H01/2/4
4.0 APPLICATION INFORMATION
The MCP6H01/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-power, high-precision
applications.
4.1 Inputs
4.1.1 PHASE REVERSAL
The MCP6H01/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-36 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”).
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors against many (but not all)
over-voltage conditions, and to minimize the input bias
current (IB).
FIGURE 4-1: Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go well above VDD. Their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
overvoltage (beyond VDD) events. Very fast ESD
events (that meet the specification) are limited so that
damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-2 shows one approach to protecting these
inputs.
FIGURE 4-2: Protecting the Analog
Inputs.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS), see Figure 2-38.
4.1.3 INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute
Maximum Ratings †).
Figure 4-3 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
currents in or out of the input pins (and the ESD diodes,
D1 and D2). The diode currents will go through either
VDD or VSS.
FIGURE 4-3: Protecting the Analog
Inputs.
4.1.4 NORMAL OPERATION
The inputs of the MCP6H01/2/4 op amps connect to a
differential PMOS input stage. It operates at a low
common mode input voltage (VCM), including ground.
With this topology, the device operates with a VCM up
to VDD – 2.3V and 0.3V below VSS (refer to Figure 2-3
through 2-5). The input offset voltage is measured at
VCM =V
SS 0.3V and VDD 2.3V to ensure proper
operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN
V1
VDD
D1
V2
D2
MCP6H0X
VOUT
V1R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
R2>VSS – (minimum expected V2)
2mA
V2R2
D2
R3
VOUT
MCP6H0X
MCP6H01/2/4
DS22243D-page 18 2010-2011 Microchip Technology Inc.
For a unity gain buffer, VIN must be maintained below
VDD – 2.3V for correct operation.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6H01/2/4 op amps
is 0.020V (typical) and 14.980V (typical) when
RL=10k is connected to VDD/2 and VDD =15V.
Refer to Figures 2-24 through 2-29 for more
information.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1V/V) is the
most sensitive to capacitive loads, all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = + 1V/V), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitance load.
FIGURE 4-4: Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-5 gives the recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1 + |Signal Gain| (e.g., -1V/V gives GN = +2V/V).
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6H01/2/4 SPICE macro
model are helpful.
FIGURE 4-5: Recommended RISO Values
for Capacitive Loads.
4.4 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
4.5 Unused Op Amps
An unused op amp in a quad package (MCP6H04)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp, and the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-6: Unused Op Amps.
VIN
RISO
VOUT
CL
+
MCP6H0X
1
10
100
1000
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Normalized Load Capacitance; CL/GN (F)
Recommended R ISO ()
GN:
1 V/V
2 V/V
5 V/V
VDD = 16V
RL = 10 k
10p 100p 1n 10n 0.1µ
1µ
1k
VDD
VDD
R1
R2
VDD
VREF
VREF VDD
R2
R1R2
+
--------------------
=
¼ MCP6H04 (A) ¼ MCP6H04 (B)
2010-2011 Microchip Technology Inc. DS22243D-page 19
MCP6H01/2/4
4.6 PCB Surface Leakage
In applications where low input bias current is critical,
PCB surface leakage effects need to be considered.
Surface leakage is caused by humidity, dust or other
contamination on the board. Under low-humidity condi-
tions, a typical resistance between nearby traces is
1012. A 15V difference would cause 15 pA of current
to flow; which is greater than the MCP6H01/2/4 family’s
bias current at +25°C (10 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
FIGURE 4-7: Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Trans-impedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
4.7 Application Circuits
4.7.1 DIFFERENCE AMPLIFIER
The MCP6H01/2/4 op amps can be used in current
sensing applications. Figure 4-8 shows a resistor
(RSEN) that converts the sensor current (ISEN) to
voltage, as well as a difference amplifier that amplifies
the voltage across the resistor while rejecting common
mode noise. R1 and R2 must be well matched to obtain
an acceptable Common Mode Rejection Ratio
(CMRR). Moreover, RSEN should be much smaller than
R1 and R2 in order to minimize the resistive loading of
the source.
To ensure proper operation, the op amp common mode
input voltage must be kept within the allowed range.
The reference voltage (VREF) is supplied by a
low-impedance source. In single-supply applications,
VREF is typically VDD/2.
.
FIGURE 4-8: High Side Current Sensing
Using Difference Amplifier.
Guard Ring VIN–V
IN+ VSS
R1
VOUT
R2
R1
RSEN ISEN
RSEN << R1, R2
VOUT V1V2

R2
R1
------

VREF
+=
VREF
R2
VDD
MCP6H01
MCP6H01/2/4
DS22243D-page 20 2010-2011 Microchip Technology Inc.
4.7.2 TWO OP AMP INSTRUMENTATION
AMPLIFIER
The MCP6H01/2/4 op amps are well suited for
conditioning sensor signals in battery-powered
applications. Figure 4-9 shows a two op amp
instrumentation amplifier using the MCP6H02, which
works well for applications requiring rejection of
common mode noise at higher gains.
To ensure proper operation, the op amp common mode
input voltage must be kept within the allowed range.
The reference voltage (VREF) is supplied by a low-
impedance source. In single-supply applications, VREF
is typically VDD/2.
FIGURE 4-9: Two Op Amp
Instrumentation Amplifier.
To obtain the best CMRR possible, and not limit the
performance by the resistor tolerances, set a high gain
with the RG resistor.
4.7.3 PHOTODETECTOR AMPLIFIER
The MCP6H01/2/4 op amps can be used to easily
convert the signal from a sensor that produces an
output current (such as a photo diode) into voltage (a
trans-impedance amplifier). This is implemented with a
single resistor (R2) in the feedback loop of the
amplifiers shown in Figure 4-10. The optional capacitor
(C2) sometimes provides stability for these circuits.
A photodiode configured in Photovoltaic mode has a
zero voltage potential placed across it. In this mode,
the light sensitivity and linearity is maximized, making it
best suited for precision applications. The key amplifier
specifications for this application are: low input bias
current, common mode input voltage range (including
ground), and rail-to-rail output.
FIGURE 4-10: Photodetector Amplifier.
VOUT V1V2
1R1
R2
------2R1
RG
---------++


VREF
+=
VREF R1R2R2R1
VOUT
RG
V2
V1
½
MCP6H02 ½
MCP6H02
D1
Light
VOUT
VDD
R2
C2
ID1
VOUT = ID1*R2
+
MCP6H01
2010-2011 Microchip Technology Inc. DS22243D-page 21
MCP6H01/2/4
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6H01/2/4 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP6H01/2/4
op amp is available on the Microchip web site at
www.microchip.com. The model was written and tested
in PSPICE owned by Orcad (Cadence). For other
simulators, it may require translation.
The model covers a wide aspect of the op amp’s
electrical specifications. Not only does the model cover
voltage, current and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside the specification range listed in the op
amp data sheet. The model behaviors under these con-
ditions cannot be guaranteed to match the actual op
amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2 FilterLab Software
Microchip’s FilterLab software is an innovative software
tool that simplifies analog active filter (using op amps)
design. Available at no cost from the Microchip web site
at www.microchip.com/filterlab, the FilterLab design
tool provides full schematic diagrams of the filter circuit
with component values. It also outputs the filter circuit
in SPICE format, which can be used with the macro
model to simulate actual filter performance.
5.3 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, MAPS is an overall selection tool for Microchip’s
product portfolio that includes analog, memory, MCUs
and DSCs. Using this tool, you can define a filter to sort
features for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for data sheets, purchases and
sampling of Microchip parts.
5.4 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are designed
to help you achieve faster time to market. For a com-
plete listing of these boards and their corresponding
user’s guides and technical information, visit the
Microchip web site: www.microchip.com/analogtools.
Some boards that are especially useful include:
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
5.5 Application Notes
The following Microchip analog design note and appli-
cation notes are available on the Microchip web site at
www.microchip.com/appnotes, and are recommended
as supplemental reference resources.
ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
AN990: “Analog Sensor Conditioning Circuits
An Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
AN1297: “Microchip’s Op Amp SPICE Macro
Models”’ DS01297
AN1332: “Current Sensing Circuit Concepts and
Fundamentals”DS01332
These application notes and others are listed in:
“Signal Chain Design Guide”, DS21825
MCP6H01/2/4
DS22243D-page 22 2010-2011 Microchip Technology Inc.
NOTES:
XXNN UUU UUU W W W W UUU UUU HHHH HHHH ()6 0N9; UUUU UUUU YWW LNN L»— r r1r1r r1r1r1r1 \plm \PIN1 NNN
2010-2011 Microchip Technology Inc. DS22243D-page 23
MCP6H01/2/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
5-Lead SC-70
(MCP6H01)
Example
8-Lead SOIC (150 mil) (MCP6H01, MCP6H02) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6H01E
SN^^ 1103
256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
Example:8-Lead 2x3 TDFN (MCP6H01, MCP6H02)
Example:
Device Code
MCP6H01 2ANN
Note: Applies to 5-Lead SOT-23.
Device Code
MCP6H01 DHNN
Note: Applies to 5-Lead SC-70.
DH25
XXNN
XXNN
2A25
5-Lead SOT-23 (MCP6H01)
AAL
103
25
H H H H H H H OfiV m HHHHHHH “\v C) HUUUHUU ILiLiLllililjl E/SL 08‘ WW HHHHHHH £9 C) HUUHUHU
MCP6H01/2/4
DS22243D-page 24 2010-2011 Microchip Technology Inc.
Package Marking Information
14-Lead TSSOP (MCP6H04)Example:
14-Lead SOIC (150 mil) (MCP6H04)Example:
XXXXXXXXXXX
YYWWNNN
XXXXXXXX
YYWW
NNN
6H04E/ST
1103
256
XXXXXXXXXXX MCP6H04
1103256
E/SL^^
3
e
2010-2011 Microchip Technology Inc. DS22243D-page 25
MCP6H01/2/4
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   
D
b
1
23
E1
E
45
ee
c
L
A1
AA2
   
5-Lead Plastic Small Outline Transistor (LT) [SC70] SiLK SCREEN X RECOMMENDED LAND PATTERN Units MiLLIMETERS Dimension Litnits AM i NOM i MAX Contact Pitcn E 0.65 BSC Contact Pad Spacing c 2.20 Contact Pad Width x 0.45 Contact Pad Lengtn v 0.95 Distance Between Pads 6 1.25 Distance Between Pads Gx 0.20 Notes 1 Dimensicning and tolerancing perASME Y1A SM 550 Basic Dimension Theoreticaiiy exact vaiue shown wilhum tolerances Microchip Technoiogy Drawing No comzoetA
MCP6H01/2/4
DS22243D-page 26 2010-2011 Microchip Technology Inc.
 

2010-2011 Microchip Technology Inc. DS22243D-page 27
MCP6H01/2/4
 !
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   
   
   
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
   
5-Lead Plastic Small Outline Transistor (OT) [SOT-23] x r Y C G / SILK— SCREEN GX _. E .— RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MN | NOM l MAX Contact pitcn E o 95 BSC CDnlacl Pad Spacing C 2 50 CDnlact Pad Width (x5) x a 60 Contact Pad Length (x5) v i 10 Distance Between Pads G 1.70 Distance Between Pads ex 0 35 Overall Wldlh Z 3 90 Notes- 1 Dimensioning and tuierancing perASME YM 5M BSC: Basic Dimension. Tneoreticaily exact vaiue snown Without toierances. Microchip Technology Drawing No cm-zosiA
MCP6H01/2/4
DS22243D-page 28 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] El WM‘ ' ///////// 7/2??? 1 Q 0.10 c D U M ' LL 2x 1 2‘ ‘3 E-l NOT“ El _ . 2x N/Z TIPS _. <_ nxb="" '5="" *="" llozs®="" topview="" a="" a2="" side="" view="" view="" a-a="" mmrocmp="" technology="" drawmg="" no.="" 50470570="" sheet="" 1="" of="" 2="">
2010-2011 Microchip Technology Inc. DS22243D-page 29
MCP6H01/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
B-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Units MILLlMETERS Dimension Limits MIN l NOM l MAX Numberat Pins N s Pitch e 1.27 ssc Overall Height A . . 1.75 Molded Package Thickness A2 1.25 . . Stands" § A1 0.10 . 0.25 Overall width E 5.00 BSC Malded Package widtn E1 3.90 850 Overall Length D 4.90 BSC Chamler (Optional) n 0.25 . 0.50 Fool Length L 0.40 . 1.27 Foolprlnl L1 1.04 REF Foot Angle #7 0° — a“ Lead Thickness c 0.17 — 0.25 Lead width b 0.31 — 0.51 Maid malt Angle Top a 5” — 15° Maid Dian Angle Bollom 13 5” — 15° Notes: 1. Pin 1 visual lndex fealure may vary. bul musl be located within the hatched area 2. § Slgniflcanl Characteristic 3 Dlmenslans D and E1 do not lnclude mold flash or pmlruslons Mold flash or protrusions shall not exceed c.15rnrn per side 4. Dimensicning and tolerancing per ASME v14 SM 050: Basic Dimension Theoretically exact value shown wrtnout tolerances REF: Relerence Dimension, usually wrtnout tolerance. tor inlarmation purposes only Microchip Technology Drawing No c047057c Sheet 2 at 2
MCP6H01/2/4
DS22243D-page 30 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Notes. L4 UDE / S‘LK SCREEN LJ BEE: X1 RECOMMENDED LAND PATTERN Umts MlLL‘METERS Dwmension Lvmts MIN \ NOM \ MAX Contact Pitch E 1.27 BSC Comacl Pad Spacmg c 5.40 Contact Pad Wwdth (xa) x1 0.60 Comacl Pad Length (X8) v1 1.55 1 Dimenswonlng and ta‘eranclng per ASME v14 SM 380 Basic Dimensmn. Theoretwca‘ly exam value Shawn wwthout to‘erances. Microcmp Technology Drawmg No. 504720st
2010-2011 Microchip Technology Inc. DS22243D-page 31
MCP6H01/2/4
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
8-Lead Plastic Dual Flat, No Lead Package (MN) 7 2x3x0.75mm Body [TDFN] TOP VIEW // 0 10 z: ‘ A l SEATWG PLANE MI E f SIDE V‘EW D2 EXPOSED V/ pm { / \ NOTE 1 8Xb——‘ <— $="" bottom="" view="" chrochwp="" technology="" drawwng="" no="" 004—1290="">
MCP6H01/2/4
DS22243D-page 32 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Dual Flat, No Lead Package (MN) — 2x3x0.75mm Body [TDFN] NOTE 2 Uniis MILLIMETERS Dimension Limits MIN i NOM I MAX Number of Pins N B Pitch e 0 50 BSC Overaii Height A 0.70 0.75 0.80 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overaii Lengih D 2.00 BSC Overaii Width E 3.00 BSC Exposed Pad Length D2 1.20 - 1.60 Exposed Pad Width E2 1.20 , 1.60 Comact Width b 0.20 0.25 0.30 Contaci Lengih L 0.25 0.30 0.45 ContacI-Io-Exposed Pad K 0 20 - - Notes: 1. Pin 1 visual Index iealure may vary, bul must be located Within the hatched area. 2. Package may have one or more exposed tie bars ai ends 3. Package is saw Singuiaied 4. Dimensioning and ioierancing perASME Yi4.5M 550. Basic Dimension Theareticaiiy exact Value sthn wilnoul iolerances. REF' Reference Dimension, usuaiiy Wiinout tolerance, ior information purposes oniy Microchip Teennoiegy Drawing No. (20471290 sneei 2 of 2
2010-2011 Microchip Technology Inc. DS22243D-page 33
MCP6H01/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
‘— WZ —’ SILKSCREEN #le‘h am C1 T2 WTLEU D D: _. E X. _.| L_ RECOMMENDED LAND PATTERN Umts MILLIMETERS Dimenston Lnnuts NHN \ NOM \ MAX Contact Pncn E o 50 Bsc Opttonat Center Pad Wtdtn W2 1 45 Opttonat Center Pad Length T2 1 35 Contact Pad Spacing 01 3.00 Contact Pad Widtn (xa) x1 0.30 Contact Pad Length (X8) Y1 0.75 Dtstance Between Pads G 0.20 Notes. 1 Dimenstunmg and tolerancmg per ASME Y14 SM 550. Bastc Dtmension. TheoreticaHy exact vatue shown wilhom tolerances. Mtcrocmp Technotogy Drawing No (30472129A
MCP6H01/2/4
DS22243D-page 34 2010-2011 Microchip Technology Inc.
"+,%-./# 0!0&()+,
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14-Lead Plastic Small Outline (0D) - Narrow, 3.90 mm Body [SOIC] E 2X DOWCD NOTE 1 TOP VIEW " SEAT‘NG PLANE i A1 7 SIDE VIEW SEE VIEW C VIEW A-A Mmrochlp Tschnc‘ogy Drawmg No GOA-0650 Sheet 1 of 2
2010-2011 Microchip Technology Inc. DS22243D-page 35
MCP6H01/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Small Outline (0D) - Narrow, 3.90 mm Body [SOIC] Akfl/‘X , L .7 (L1) <7 4x="" 1‘?="" «="" view="" 0="" unils="" mlllimeters="" dimenslon="" lirnils="" mln="" l="" nom="" l="" max="" number="" ol="" fins="" n="" 14="" pltch="" e="" 1.27="" bsc="" overall="" helght="" a="" .="" .="" 1="" 75="" molded="" package="" thlclmess="" a2="" 1.25="" .="" .="" standofl="" §="" a1="" 0.10="" .="" 0="" 25="" overall="" widlh="" e="" 0.00="" esc="" molded="" package="" widll'l="" e1="" 3.90="" esc="" overall="" length="" d="" 8.65="" esc="" chamfer="" (opllonal)="" n="" 0.25="" -="" 0="" 50="" fool="" length="" l="" 0.40="" -="" 1="" 27="" foolonnt="" l1="" 1.04="" ref="" lead="" angle="" e="" 0"="" -="" -="" fool="" angle="" la="" 0-="" -="" a"="" lead="" thlckness="" c="" 010="" -="" 0="" 25="" lead="" wrdtn="" b="" 0="" 31="" -="" 0="" 51="" mold="" drafl="" angle="" top="" or="" 5“="" -="" 15"="" mold="" drafl="" angle="" bottom="" 19="" 5“="" -="" 15"="" noles:="" 1.="" 2="" 3="" pl"="" 1="" vlsual="" lndex="" feature="" may="" vary.="" but="" must="" be="" located="" wrthin="" the="" hatched="" area.="" §="" srgnlllcanl="" charactenstlc="" dlmenslon="" d="" does="" not="" lnclvde="" meld="" flash,="" protrvslons="" or="" gate="" burrs,="" whlcn="" shall="" hol="" exceed="" 015="" mm="" per="" end="" dlmension="" e1="" does="" not="" lnclvde="" lnterlead="" flash="" or="" prolmsion.="" which="" shall="" not="" exceed="" 0.25="" mm="" per="" slde.="" ormenslonlng="" and="" tolerancrng="" perasme="" v14="" sm="" 050="" basic="" oimehslon.="" theoretlcally="" exam="" value="" shown="" wrtnout="" tolerances.="" ref="" reference="" dlmensiun‘="" usually="" wilnout="" tolerance,="" ler="" inlormation="" purposes="" only="" datvms="" a="" a.="" b="" to="" be="" determined="" at="" datum="" h.="" mlcrochlp="" tecnndlogy="" drawlng="" no="" 004-0550="" sheet="" 2="" at="" 2="">
MCP6H01/2/4
DS22243D-page 36 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Small Outline (SL) - Narrow. 3.90 mm Body [SOIC] ”1‘6 Gx ‘ ‘ SW C S / SCREEN t _T V E E E 4 EX 1 RECOMMENDED LAND PATTERN Umts MILLtMETERS Dtmension Ltmtts MW \ NOM \ MAX Contact Pitch E 1 27 BBC Contact Pad Spaclng c 5.40 Contact Pad Widlh x o 60 Contact Pad Lengln V 1 50 Distance Between Pads Ex 0 67 Distance Between Pads (3 3 90 Notes: 1. Dimenstomng and tolerancmg per ASME Y14.5M BSC Basic Dtmenston. Theorettcauy exacl value shown without toterances. Mtorocmp Technology Drawmg No cotzoem
2010-2011 Microchip Technology Inc. DS22243D-page 37
MCP6H01/2/4
 

14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] TOP VIEW E0 SEATING PLANE. """ SIDE VIEW Mmcmu Technulogy Drawmg comma Sheen 1 of 2
MCP6H01/2/4
DS22243D-page 38 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] Unlls MlLLIMETERS Dlmenslon lells MIN | NOM | MAX Number of Plns N 14 Pltch e o 65 ESE Overall Helghl A , , 1 20 Molded Package Thlckness A2 0 80 1 00 1 05 Standoff A1 0 05 , 0 15 Overall W1dlh E e 40 Bsc Molded Package Width E1 4 30 4 40 4 50 Molded Package Lenglh D 4 90 5 00 510 Pool Lenglh L 0 45 o 60 0 75 Foolprinl (L1) 1.00 REF Fool Angle «J 0“ , 8° Lead Thlckness c o 09 , 0 20 Lead Widih b 019 , 0 30 Notes 1 Pm 1 Vlsual Index ieature may vary‘ but must be localed Wllnln lhe nalcneo area 2. Dimenslons D and E1 do nol lnclude mold llash or prolrusions Mold flash or prolruslons shall not exceed U15mm per slde 3. Dimenslonlng and lolerancing per ASME Y14.5M BSC Basic Dimenslon. Theorellcally exacl value shown wlthoul loleranoes. REF Reierence Dlmension, usually without lolerance, lor iniormalion purposes only. Mlcrochlp Technology Drawlng No c04-os7c Sheet 2 of 2
2010-2011 Microchip Technology Inc. DS22243D-page 39
MCP6H01/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] c1 . l l |::| |::| ’ E |:| |:| 7 e X‘ ’ l:| l:| SILK SCREEN RECOMMENDED LAND PATTERN Unils MlLLIMETERS Dimensmn Limils MIN | NOM | MAX Cunlact Pllch E D 65 BSC Canlacl Pad Spacmg c1 5 so Canlact Pad Wldth (X14) X1 0 45 Cunlact Pad Lengm (x14) v1 1 A5 Dlstance Between Pads (3 U 20 Notes: 1. Dlmensioning and lolerancmg per ASME Y14.5M BSC: Basm Dimensmn Theorellcally exact value shown wnmm tolerances Mlcrochlp Technology Drawing No C04-2087A
MCP6H01/2/4
DS22243D-page 40 2010-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2011 Microchip Technology Inc. DS22243D-page 41
MCP6H01/2/4
APPENDIX A: REVISION HISTORY
Revision D (December 2011)
The following is the list of modifications:
1. Added the SC70-5 and SOT-23-5 packages for
the MCP6H01 device and updated all related
information throughout the document.
Revision C (March 2011)
The following is the list of modifications:
1. Added new device MCP6H04.
2. Updated Table 3-1 with MCP6H04 pin names
and details.
Revision B (October 2010)
The following is the list of modifications:
1. Updated Section 4.1 “Inputs”.
Revision A (March 2010)
Original Release of this Document.
MCP6H01/2/4
DS22243D-page 42 2010-2011 Microchip Technology Inc.
NOTES:
PART NO. v lxx
2010-2011 Microchip Technology Inc. DS22243D-page 43
MCP6H01/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6H01T: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
MCP6H01: Single Op Amp
MCP6H01T: Single Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
MCP6H02: Dual Op Amp
MCP6H02T: Dual Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
MCP6H04: Quad Op Amp
MCP6H04T: Quad Op Amp (Tape and Reel) (SOIC
and TSSOP)
Temperature Range: E = -40°C to +125°C
Package: LT = Plastic Package (SC-70), 5-lead
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
MNY * = Plastic Dual Flat, No Lead, (2x3 TDFN) 8-lead
SN = Lead Plastic Small Outline (150 mil Body), 8-lead
SL = Plastic Small Outline, (150 mil Body), 14-lead
ST = Plastic Thin Shrink Small Outline (150 mil Body),
14-lead
* Y = Nickel palladium gold manufacturing designator. Only
available on the TDFN package.
PART NO. /XX
PackageTemperature
Range
Device
Examples:
a) MCP6H01T-E/LT: Tape and Reel,
5LD SC70 pkg
b) MCP6H01T-E/OT: Tape and Reel,
5LD SOT-23 pkg
c) MCP6H01-E/SN: 8LD SOIC pkg
d) MCP6H01T-E/SN: Tape and Reel,
8LD SOIC pkg
e) MCP6H01T-E/MNY: Tape and Reel,
8LD 2x3 TDFN pkg
f) MCP6H02-E/SN: 8LD SOIC pkg
g) MCP6H02T-E/SN: Tape and Reel,
8LD SOIC pkg
h) MCP6H02T-E/MNY: Tape and Reel
8LD 2x3 TDFN pkg
i) MCP6H04-E/SL: 14LD SOIC pkg
j) MCP6H04T-E/SL: Tape and Reel,
14LD SOIC pkg
k) MCP6H04-E/ST: 14LD SOIC pkg
l) MCP6H04T-E/ST: Tape and Reel,
14LD TSSOP pkg
-X
MCP6H01/2/4
DS22243D-page 44 2010-2011 Microchip Technology Inc.
NOTES:
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 169492009:
2010-2011 Microchip Technology Inc. DS22243D-page 45
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-927-4
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
6‘ MICRDCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS22243D-page 46 2010-2011 Microchip Technology Inc.
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11/29/11

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