DS1878 Datasheet by Maxim Integrated

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lVI/JXI/VI [MAXI/VI
General Description
The DS1878 controls and monitors all functions for SFF,
SFP, and SFP+ modules including all SFF-8472 func-
tionality. The combination of the DS1878 with Maxim
laser driver/limiting amplifier solutions supports VCSEL,
DFB, and EML-based solutions. The device provides
APC loop, modulation current control, and eye safety
functionality. It continuously monitors for high output
current, high bias current, and low and high transmit
power to ensure that laser shutdown for eye safety
requirements are met without adding external compo-
nents. Six ADC channels monitor VCC, temperature,
and four external monitor inputs (MON1–MON4) that
can be used to meet all monitoring requirements.
MON3 is differential with support for common mode to
VCC. Two digital-to-analog (DAC) outputs with tempera-
ture-indexed lookup tables (LUTs) are available for
additional control functionality.
Applications
SFF, SFP, and SFP+ Transceiver Modules
Features
Meets All SFF-8472 Control and Monitoring
Requirements
Laser Bias Controlled by APC Loop and
Temperature LUT to Compensate for Tracking
Error
Laser Modulation Controlled by Temperature LUT
Six Analog Monitor Channels: Temperature, VCC,
MON1–MON4
MON1–MON4 Support Internal and External
Calibration
Scalable Dynamic Range
Internal Direct-to-Digital Temperature Sensor
Alarm and Warning Flags for All Monitored
Channels
Two 9-Bit Delta-Sigma Outputs with 36 Entry
Temperature LUTs
Digital I/O Pins: Five Inputs, Four Outputs
Comprehensive Fault-Measurement System with
Maskable Laser Shutdown Capability
Flexible, Two-Level Password Scheme Provides
Three Levels of Security
256 Additional Bytes Located at A0h Slave
Address
I2C-Compatible Interface
3-Wire Master to Communicate with a Maxim
Laser Driver/Limiting Amplifier
+2.85V to +5.5V Operating Voltage Range
-40°C to +95°C Operating Temperature Range
28-Pin TQFN (5mm x 5mm x 0.75mm) Package
DS1878
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-5537; Rev 1; 8/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
DS1878T+ -40°C to +95°C 28 TQFN-EP*
DS1878T+T&R -40°C to +95°C 28 TQFN-EP*
SFP+ Controller with Digital LDD Interface
[VIIJXIIM
DS1878
2 _______________________________________________________________________________________
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DAC1, DAC2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Input Characteristics (MON2, TXP HI, TXP LO, HBIAS, LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Control Loop and Quick-Trip Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3-Wire Digital Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
I2C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Nonvolatile Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3-Wire DAC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
BIAS Register/APC Control, 3-Wire Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MODULATION Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
BIAS and MODULATION Control During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
BIAS and MODULATION Registers as a Function of Transmit Disable (TXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
APC and Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Five Quick-Trip Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Six ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Enhanced RSSI Monitoring (Dual-Range Functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Power-On Analog (POA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Delta-Sigma Outputs (DAC1 and DAC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
LOS, LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
IN1, RSEL, RSELOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
TXD, TXDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
TABLE OF CONTENTS
SFP+ Controller with Digital LDD Interface
DS1878
Transmit Fault (TXFOUT) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3-Wire Master for Controlling the Maxim Laser Driver and Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3-Wire Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DS1878 Master Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Manual Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Register Map and DS1878 Corresponding Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
I2C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I2C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
I2C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 07h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 08h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Auxiliary A0h Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Lower Memory Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 04h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table 06h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table 07h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 08h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Auxiliary Memory A0h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
TABLE OF CONTENTS (continued)
SFP+ Controller with Digital LDD Interface
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
4 _______________________________________________________________________________________
Figure 1. Modulation LUT Loading to a Maxim Laser Driver MOD DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 2. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3. TXD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. APC Loop and Quick-Trip Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 5. ADC Round-Robin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 6. MON2 VCC or GND Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. MON3 Differential Input for High-Side RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 8. RSSI with Crossover Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 9. RSSI with Crossover Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 10. Low-Voltage Hysteresis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 11. Recommended RC Filter for DAC1/DAC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 12. Delta-Sigma Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 13. DAC1/DAC2 LUT Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 14. 3-Wire Communication on RSELOUT Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 15. Logic Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 16. Logic Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 17a. TXFOUT Nonlatched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 17b. TXFOUT Latched Operation and TXD_TXFEN = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 17c. TXFOUT When TXD_TXFEN = 0 on Fast Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 17d. TXFOUT When TXD_TXFEN = 0 on Slow Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 18. 3-Wire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 19. 3-Wire State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 20. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 21. Example I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 22. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 2. Update Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 4. MON3 Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 5. MON3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
LIST OF FIGURES
LIST OF TABLES
[VI/JXI [VI
DS1878
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on MON1–MON4, RSEL, CSEL1OUT,
CSEL2OUT, SCLOUT, SDAOUT, TXDOUT, IN1,
LOS, TXF, TXFOUT, and TXD Pins
Relative to Ground .................................-0.5V to (VCC + 0.5V)*
Voltage Range on VCC, SDA, SCL, RSELOUT,
and LOSOUT Pins Relative to Ground ..................-0.5V to +6V
Continuous Power Dissipation (TA= +70°C)
28 Pin TQFN (derate 34.5mW/°C above +70°C) .....2758.6mW
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +95°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Main Supply Voltage VCC (Note 1) 2.85 5.5 V
High-Level Input Voltage
(SDA, SCL, SDAOUT) VIH:1 0.7 x
VCC
VCC +
0.3 V
Low-Level Input Voltage
(SDA, SCL, SDAOUT) VIL:1 -0.3 0.3 x
VCC V
High-Level Input Voltage
(TXD, TXF, RSEL, IN1, LOS) VIH:2 2.0 VCC +
0.3 V
Low-Level Input Voltage
(TXD, TXF, RSEL, IN1, LOS) VIL:2 -0.3 +0.8 V
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, unless otherwise noted.)
*
Subject to not exceeding +6V.
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +95°C, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
SFP+ Controller with Digital LDD Interface
_______________________________________________________________________________________ 5
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC (Notes 1, 2) 2.5 4 mA
Output Leakage
(SDA, SDAOUT, RSELOUT,
LOSOUT, TXFOUT)
ILO 1 μA
IOL = 4mA 0.4
Low-Level Output Voltage (SDA,
SDAOUT, SCLOUT, CSEL1OUT,
CSEL2OUT, RSELOUT, LOSOUT,
TXDOUT, DAC1, DAC2, TXFOUT)
VOL
IOL = 6mA 0.6
V
High-Level Output Voltage
(DAC1, DAC2, SCLOUT,
SDAOUT, CSEL1OUT,
CSEL2OUT, TXDOUT)
VOH I
OH = 4mA VCC -
0.4 V
TXDOUT Before EEPROM Recall
DAC1 and DAC2 Before Recall High impedance before recall 55 550 100 M
Input Leakage Current
(IN1, LOS, RSEL, SCL, TXD, TXF) ILI 1 μA
Digital Power-On Reset POD 1.0 2.2 V
Analog Power-On Reset POA 2.0 2.75 V
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
6 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC Resolution 13 Bits
Input/Supply Accuracy
(MON1–MON4, VCC)ACC At factory setting 0.25 0.5 %FS
Sample Rate for Temperature,
MON1MON4, and VCC tRR 64 75 ms
Input/Supply Offset
(MON1–MON4, VCC)VOS (Note 5) 0 5 LSB
MON1MON4 2.5
VCC 6.5536 V
Factory Setting Full-Scale
(Note 6)
MON3 Fine 312.5 μV
ANALOG VOLTAGE MONITORING CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MON2, TXP HI, TXP LO, HBIAS,
LOS Full-Scale Voltage (Note 3) 1.25 V
MON2 Input Resistance 35 50 65 k
Resolution (Note 3) 8 Bits
Error TA = +2C (Note 4) ±2 %FS
Integral Nonlinearity -1 +1 LSB
Differential Nonlinearity -1 +1 LSB
Temperature Drift -2.5 +2.5 %FS
ANALOG INPUT CHARACTERISTICS (MON2, TXP HI, TXP LO, HBIAS, LOS)
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Main Oscillator Frequency fOSC 5 MHz
Delta-Sigma Input-Clock
Frequency fDS 1.25 MHz
Reference Voltage Input (REFIN) VREFIN Minimum 0.1μF to GND 2 VCC V
Output Range 0 VREFIN V
Output Resolution See the Delta-Sigma Outputs (DAC1 and
DAC2) section for details 9 Bits
Output Impedance RDS 35 100
DAC1, DAC2 ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, unless otherwise noted.)
mg POA [VI/JXI [VI
DS1878
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLOUT Clock Frequency fSCLOUT 833 kHz
SCLOUT Duty Cycle t3WDC 50 %
SDAOUT Setup Time tDS 100 ns
SDAOUT Hold Time tDH 100 ns
CSEL1OUT, CSEL2OUT Pulse-
Width Low tCSW 500 ns
CSEL1OUT, CSEL2OUT Leading
Time Before the First SCLOUT
Edge
tL 500 ns
CSEL1OUT, CSEL2OUT Trailing
Time After the Last SCLOUT
Edge
tT 500 ns
SDAOUT, SCLOUT Load CB3W Total bus capacitance on one line 10 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output-Enable Time Following POA tINIT (Note 7) 20 ms
Binary Search Time tSEARCH (Note 11) 8 10 BIAS
Samples
3-WIRE DIGITAL INTERFACE SPECIFICATION
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (Figure 17)
SFP+ Controller with Digital LDD Interface
_______________________________________________________________________________________ 7
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TXD Enable tOFF From rising TXD to rising TXDOUT 5 μs
Recovery from TXD Disable tON From falling TXD to falling TXDOUT 5 μs
tINITR1 From falling TXD 131
Fault Reset Time
(to TXFOUT = 0) tINITR2 On power-up or falling TXD, when VCC LO
alarm is detected (Note 7) 161 ms
Fault Assert Time
(to TXFOUT = 1) tFAULT After HTXP, LTXP, HBATH, IBIASMAX
(Note 8) 6.4 55 μs
LOSOUT Assert Time tLOSS_ON LLOS (Notes 8, 9) 6.4 55 μs
LOSOUT Deassert Time tLOSS_OFF HLOS (Notes 8, 10) 6.4 55 μs
CONTROL LOOP AND QUICK-TRIP TIMING CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, unless otherwise noted.)
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Thermometer Error TERR -40°C to +95°C -3 +3 °C
DIGITAL THERMOMETER CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, unless otherwise noted.)
[VIIJXIIM
Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2: Inputs are at supply rail. Outputs are not loaded.
Note 3: Eight ranges allow the full-scale range to change from 312mV to 1.25V.
Note 4: The output impedance of the device is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance is 1.5kΩ.
Note 5: This parameter is guaranteed by design.
Note 6: Full-scale is programmable.
Note 7: A temperature conversion is completed and the MODULATION register value is recalled from the LUT and VCC has been
measured to be above the VCC LO alarm.
Note 8: The timing is determined by the choice of the SAMPLE RATE setting (see Table 02h, Register 88h).
Note 9: This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
Note 10: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Note 11: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be within 3% within the time specified by the binary search time. See the
BIAS and MODULA-
TION Control During Power-Up
section.
Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard-mode timing.
Note 13: CB—the total capacitance of one bus line in pF.
Note 14: EEPROM write begins after a STOP condition occurs.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 12) 0 400 kHz
Clock Pulse-Width Low tLOW 1.3 μs
Clock Pulse-Width High tHIGH 0.6 μs
Bus-Free Time Between STOP and START
Condition tBUF 1.3 μs
START Hold Time tHD:STA 0.6 μs
START Setup Time tSU:STA 0.6 μs
Data In Hold Time tHD:DAT 0 0.9 μs
Data In Setup Time tSU:DAT 100 ns
Rise Time of Both SDA and SCL Signals tR (Note 13) 20 + 0.1CB 300 ns
Fall Time of Both SDA and SCL Signals tF (Note 13) 20 + 0.1CB 300 ns
STOP Setup Time tSU:STO 0.6 μs
Capacitive Load for Each Bus Line CB 400 pF
EEPROM Write Time tWR (Note 14) 20 ms
DS1878
SFP+ Controller with Digital LDD Interface
8 _______________________________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +5.5V, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
At +25°C 200,000
EEPROM Write Cycles At +85°C 50,000
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA= -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (Figure 19)
[VI/IX I [VI
DS1878
SFP+ Controller with Digital LDD Interface
_______________________________________________________________________________________
9
Typical Operating Characteristics
(VCC = +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DS1878 toc01
VCC (V)
SUPPLY CURRENT (mA)
3.853.603.10 3.35
1.7
1.9
2.1
2.3
2.7
2.5
2.9
1.5
2.85
+95°C
SDA = SCL = VCC
-40°C
+25°C
SUPPLY CURRENT
vs. TEMPERATURE
DS1878 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
806040200-20
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.0
-40
VCC = 3.3V
VCC = 3.9V
VCC = 2.85V
SDA = SCL = VCC
MON1–MON4 INL
DS1878 toc03
MON1–MON4 INPUT VOLTAGE (V)
MON1–MON4 INL (LSB)
2.01.51.00.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2.5
VCC = 3.3V
USING FACTORY-PROGRAMMED FULL-SCALE
VALUE OF 2.5V
MON1–MON4 DNL
DS1878 toc04
MON1–MON4 INPUT VOLTAGE (V)
MON1–MON4 DNL (LSB)
2.01.51.00.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2.5
VCC = 3.3V
USING FACTORY-PROGRAMMED FULL-SCALE
VALUE OF 2.5V
DAC1 AND DAC2 DNL
DS1878 toc05
DAC1 AND DAC2 POSITION (DEC)
DAC1 AND DAC2 DNL (LSB)
500400300200100
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0
DAC1 AND DAC2 INL
DS1878 toc06
DAC1 AND DAC2 POSITION (DEC)
DAC1 AND DAC2 INL (LSB)
500400100 200 300
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
0
[MAXI/III [VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
10 ______________________________________________________________________________________
Pin Description
Pin Configuration
PIN NAME FUNCTION
1 RSELOUT Rate-Select Output
2 SCL I2C Serial-Clock Input
3 SDA I2C Serial-Data Input/Output
4 TXFOUT Transmit Fault Output, Open Drain
5 LOS Loss of Signal Input
6 IN1
Digital Input. General-purpose
input, AS1 in SFF-8079, or RS1 in
SFF-8431.
7 TXD Transmit Disable Input
8, 17, 21 GND Ground Connection
9 RSEL Rate-Select Input
10 TXDOUT Transmit Disable Output
11 MON4 External Monitor Input 4
12, 13 MON3P,
MON3N
Differential External Monitor Input 3
and LOS Quick Trip
14 MON1
External Monitor Input 1 and
HBATH Quick Trip
15, 23 VCC Power-Supply Input
16 MON2
External Monitor Input 2, Feedback
Voltage for APC Loop, and TXP
HI/TXP LO Quick Trip
PIN NAME FUNCTION
18 REFIN
Reference Input for DAC1 and
19 DAC1 Delta-Sigma Output 1
20 DAC2 Delta-Sigma Output 2
22 CSEL2OUT
Chip-Select Output 2. Part of 3-wire
interface to a laser driver/limiting
amplifier.
24 CSEL1OUT
Chip-Select Output 1. Part of 3-wire
interface to a laser driver/limiting
amplifier.
25 SCLOUT
Serial-Clock Output. Part of 3-wire
interface to a laser driver/limiting
amplifier.
26 SDAOUT
Serial-Data Input/Output. Part of
3-wire interface to a laser
driver/limiting amplifier.
27 LOSOUT Receive Loss-of-Signal Output
28 TXF Transmit Fault Input
EP Exposed Pad. Connect to ground.
THIN QFN
(5mm
×
5mm
×
0.75mm)
TOP VIEW
26
27
25
24
10
9
11
SCL
TXFOUT
LOS
IN1
TXD
12
RSELOUT
DAC2
REFIN
GND
GND
MON2
VCC
12
SCLOUT
4567
2021 19 17 16 15
SDAOUT
LOSOUT
MON3P
MON4
TXDOUT
RSEL
SDA DAC1
3
18
28 8
TXF GND
CSEL1OUT
23 13 MON3N
VCC
22 14 MON1
CSEL2OUT
DS1878
EP
+
[III/[XVIII [VI/JXIIVI ,iiiiiii—,
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 11
Block Diagram
ANALOG MUX
MAIN MEMORY
EEPROM/SRAM
ADC CONFIGURATION/RESULTS,
SYSTEM STATUS/CONTROL BITS,
ALARMS/WARNINGS,
LOOKUP TABLES,
USER MEMORY
I2C
INTERFACE
3-WIRE
INTERFACE
TEMPERATURE
SENSOR
CONFIGURABLE
LOGIC
POWER-ON
ANALOG
INTERRUPT
EEPROM
256 BYTES
AT A0h
SDA
SCL
VCC
VCC
VCC
MON1
MON2
MON4
MON3P
MON3N
CONFIGURABLE
LOGIC
9-BIT
DELTA-SIGMA
9-BIT
DELTA-SIGMA
APC
INTEGRATOR
13-BIT
ADC
8-BIT
QTs
DAC1
DAC2
SDAOUT
SCLOUT
CSEL1OUT
CSEL2OUT
TXFOUT
REFIN
TXDOUT
RSELOUT
LOSOUT
TXD
TXF
RSEL
IN1
LOS
GND
DS1878
VCC
VCC
ll/I/lXIIVI [MAXI/III ll/l/le/l/I |:| i CE [VIIJXIIM
LOS
TXF
TXDOUT
TXD
FAULT
DISABLE
RSEL
RSELOUT
LOS
LOSOUT
TXFOUT TX_FAULT
SDA
SCL
MODE_DEF2 (SDA)
RATE SELECT
LOS
MODE_DEF1 (SCL)
TX_DISABLE
MODE
DAC
BIAS
DAC
LDD
EEPROM
QUICK
TRIP
LOS
ADC
I2C
3W
3W
CS1
DS1878
MAX3946
3W
CS2
MAX3945
MON1
MON2
MON3
BMON
RMON
680Ω
+3.3V
RBD
LA
PIN-ROSA
DFB TOSA
DS1878
SFP+ Controller with Digital LDD Interface
12 ______________________________________________________________________________________
Detailed Description
The DS1878 integrates the control and monitoring func-
tionality required to implement a VCSEL-based or DFB-
based SFP or SFP+ system using Maxim’s limiting
amplifiers and laser drivers. Key components of the
device are shown in the
Block Diagram
and described
in subsequent sections.
3-Wire DAC Control
The device controls two 9-bit DACs inside the Maxim
laser drivers. One DAC is used for laser bias control,
while the other is used for modulation amplitude control.
The device communicates with the laser driver over a 3-
wire digital interface (see the
3-Wire Master for
Controlling the Maxim Laser Driver
section). The com-
munication between the device and Maxim laser driver
and/or limiting amplifier is transparent to the end user.
Typical Operating Circuit
[VI/JXI [VI
BIAS Register/APC Control, 3-Wire Mode
A Maxim laser driver controls its laser bias current DAC
using the APC loop within the device. The APC loop’s
feedback to the device is the monitor diode (MON2)
current, which is converted to a voltage using an exter-
nal resistor. The feedback is sampled by a comparator
and compared to a digital set-point value. The output of
the comparator has three states: up, down, or no-oper-
ation. The no-operation state prevents the output from
excessive toggling once steady state is reached. As
long as the comparator output is in either the up or
down states, the bias is adjusted by writing increment
and decrement values to the Maxim laser driver
through the BIASINC register.
The device has an LUT to allow the APC set point to
change as a function of temperature to compensate for
tracking error (TE). The APC LUT has 36 entries that
determine the APC setting in 4°C windows between
-40°C and +100°C.
MODULATION Control
A Maxim laser driver controls the laser modulation
using the internal temperature-indexed LUT within the
device. The modulation LUT is programmed in 2°C
increments over the -40°C to +102°C range to provide
temperature compensation for the laser’s modulation.
The modulation is updated after each temperature con-
version using the 3-wire interface that connects to the
Maxim laser driver. A Maxim laser driver include a 9-bit
DAC. The modulation LUT is 8 bits.
Figure 1 demonstrates how the 8-bit LUT controls the
9-bit DAC with the use of a temperature control bit
DS1878
______________________________________________________________________________________ 13
Table 1. Acronyms
ACRONYM DEFINITION
ADC Analog-to-Digital Converter
AGC Automatic Gain Control
APC Automatic Power Control
APD Avalanche Photodiode
ATB Alarm Trap Bytes
BM Burst Mode
DAC Digital-to-Analog Converter
DFB Distributed Feedback Laser
LDD Laser Diode Driver
LOS Loss of Signal
LUT Lookup Table
NV Nonvolatile
QT Quick Trip
TE Tracking Error
TIA Transimpedance Amplifier
ROSA Receiver Optical Subassembly
SEE Shadowed EEPROM
SFF Small Form Factor
SFF-8472 Document Defining Register Map of SFPs
and SFFs
SFP Small Form Factor Pluggable
SFP+ Enhanced SFP
TOSA Transmit Optical Subassembly
TXP Transmit Power
VCSEL Vertical Cavity Self-Emitting Laser
SFP+ Controller with Digital LDD Interface
MOD LUT
LOADED TO [7:0]
MOD LUT
LOADED TO [7:0]
MODTI
8
7
6
5
4
3
2
1
0
MODTI
MODTC = 0
TEMPERATURE (°C)
-40 +102 TEMPERATURE (°C)
-40 +102
MODTC = 1
MOD LUT
LOADED TO [8:1]
(DAC BIT 0 = 0)
MOD LUT
LOADED TO [8:1]
(DAC BIT 0 = 0)
MAX3798 DAC BIT
8
7
6
5
4
3
2
1
0
MAX3798 DAC BIT
Figure 1. Modulation LUT Loading to a Maxim Laser Driver MOD DAC
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
14 ______________________________________________________________________________________
(MODTC, Table 02h, Register C6h) and a temperature
index register (MODTI, Table 02h, Register C2h).
BIAS and MODULATION Control
During Power-Up
The device has two internal registers, MODULATION
and BIAS, that represent the values written to the Maxim
laser driver’s modulation DAC and bias DAC through
the 3-wire interface. On power-up, the device sets the
MODULATION and BIAS registers to 0. When VCC is
above POA, the device initializes the Maxim laser driver.
After a temperature conversion is completed and if the
VCC LO alarm is enabled, an additional VCC conversion
above the customer-defined VCC LO alarm level is
required before a Maxim laser driver MODULATION
register is updated with the value determined by the
temperature conversion and the modulation LUT.
When the MODULATION register is set, the BIAS regis-
ter is set to a value equal to ISTEP (see Figure 2). The
startup algorithm verifies whether this bias current caus-
es a feedback voltage above the APC set point, and if
not, it continues increasing the BIAS register by ISTEP
until the APC set point is exceeded. When the APC set
point is exceeded, the device begins a binary search to
quickly reach the bias current corresponding to the
proper power level. After the binary search is complet-
ed, the APC integrator is enabled and single LSB steps
are used to tightly control the average power.
The TXP HI, TXP LO, and BIAS MAX QT alarms are
masked until the binary search is completed. However,
the BIAS MAX alarm is monitored during this time to
prevent the BIAS register from exceeding
IBIASMAX. During the bias current initialization, the
BIAS register is not allowed to exceed IBIASMAX. If this
occurs during the ISTEP sequence, then the binary
search routine is enabled. If IBIASMAX is exceeded
during the binary search, the next smaller step is acti-
vated. ISTEP or binary increments that would cause the
BIAS register to exceed IBIASMAX are not taken.
Masking the alarms until the completion of the binary
search prevents false positive alarms during startup.
ISTEP is a value controlled by registers ISTEPH,
ISTEPL, and ISTEPTI (Table 02h, Registers BAh, BBh,
and C5h, respectively). See the register descriptions for
more information. During the first steps, a Maxim laser
driver’s bias DAC is directly written using SET_IBIAS.
ISTEP should be programmed to the maximum safe
increase that is allowable during startup. If this value is
programmed too low, the device still operates, but it
could take significantly longer for the algorithm to con-
verge and hence to control the average power.
If a fault is detected, and TXD is toggled to reenable
the outputs, the device powers up following a similar
sequence to an initial power-up. The only difference is
that the device already has determined the present
12345678910111213
VPOA
MODULATION REGISTER
BIAS REGISTER
VCC
BIAS SAMPLE
tINIT
tSEARCH
BINARY SEARCH
APC INTEGRATOR ON
4x ISTEP
3x ISTEP
2x ISTEP
ISTEP
Figure 2. Power-Up Timing
[VI/JXI [VI
temperature, so the tINIT time is not required for the device
to recall the APC and MOD set points from EEPROM.
BIAS and MODULATION Registers as a
Function of Transmit Disable (TXD)
If TXD is asserted (logic 1) during normal operation,
the 3-wire master writes the laser driver bias and
MODULATION DACs to 0. When TXD is deasserted
(logic 0), the device sets the MODULATION register
with the value associated with the present temperature,
and initializes the BIAS register using the same search
algorithm as done at startup. When asserted, soft TXD
(TXDC) (Lower Memory, Register 6Eh) would allow a
software control identical to the TXD pin (see Figure 3).
APC and Quick-Trip Timing
As shown in Figure 4, the device’s input comparator is
shared between the APC control loop and the quick-
trip alarms (TXP HI, TXP LO, LOS, BIAS HI, and IBIAS
MAX). The comparator polls the alarms in a multiplexed
sequence. Five of every eight comparator readings are
used for APC loop bias-current control. The other three
updates are used to check the HTXP/LTXP (monitor
diode voltage), the HBATH (MON1), and LOS (MON3)
signals against the internal APC, BIAS, and MON3 ref-
erence, respectively. If the last APC comparison was
higher than the APC set point, it makes an HTXP com-
parison, and if it is lower, it makes an LTXP compari-
son. Depending on the results of the comparison, the
corresponding alarms and warnings (TXP HI, TXP LO)
are asserted or deasserted.
The device has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options and time
delays resulting from writing values to the laser driver’s
bias DAC. The SAMPLE RATE register (Table 02h,
Register 88h) determines the sampling time. Samples
occur at a regular interval, tREP. Table 2 shows the
sample rate options available. Any quick-trip alarm that
is detected by default remains active until a subse-
quent comparator sample shows the condition no
longer exists. A second bias current monitor (BIAS
MAX) compares a Maxim laser driver’s BIAS DAC’s
code to a digital value stored in the IBIASMAX register.
This comparison is made at every bias current update
to ensure that a high-bias current is quickly detected.
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 15
APC QUICK-TRIP SAMPLE TIMES HBIAS
SAMPLE
HBIAS
SAMPLE
LOS
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
HTXP/LTXP
SAMPLE
tREP
Figure 4. APC Loop and Quick-Trip Sample Timing
Table 2. Update Rate Timing
APC_SR[2:0] SAMPLE PERIOD (tREP)
(ns)
000b 800
001b 1200
010b 1600
011b 2000
100b 2800
101b 3200
110b 4400
111b 6400
tOFF tON
TXD
TXDOUT
Figure 3. TXD Timing
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
16 ______________________________________________________________________________________
An APC sample that requires an update of the BIAS
register causes subsequent APC samples to be
ignored until the end of the 3-wire communication that
updates the laser driver’s BIAS DAC, plus an additional
16 sample periods (tREP).
Monitors and Fault Detection
Monitors
Monitoring functions on the device include five quick-trip
comparators and six ADC channels. This monitoring
combined with the alarm enables (Table 01h/05h) deter-
mines when/if the device turns off the Maxim laser dri-
ver’s DACs and triggers the TXFOUT and TXDOUT
outputs. All the monitoring levels and interrupt masks are
user programmable.
Five Quick-Trip Monitors and Alarms
Five quick trip monitors are provided to detect potential
laser safety issues and LOS status. These monitor the
following:
1) High Bias Current (HBATH), causing QT BIAS HI
2) Low Transmit Power (LTXP), causing QT TXP LO
3) High Transmit Power (HTXP), causing QT TXP HI
4) Max Output Current (IBIASMAX), causing QT BIAS
MAX
5) Loss of Signal (LLOS), causing QT LOS LO
The high and low transmit power quick-trip registers
(HTXP and LTXP) set the thresholds used to compare
against the MON2 voltage to determine if the transmit
power is within specification. The HBATH quick trip
compares the MON1 input (generally from a Maxim
laser driver bias monitor output) against its threshold
setting to determine if the present bias current is above
specification. The user can program up to eight differ-
ent temperature-indexed threshold levels for HBATH
(Table 02h, Registers D0h–D7h).
The BIAS MAX quick trip compares the BIAS register
with the MON2 voltage and determines if the BIAS reg-
ister is above specification. The BIAS register is not
allowed to exceed the value set in the IBIASMAX regis-
ter. When the device detects the bias is at the limit, it
sets the BIAS MAX status bit and holds the BIAS regis-
ter setting at the IBIASMAX level.
The LOS LO quick trip compares the MON3 input
against its threshold setting (LLOS) to determine if the
present received power is below the specification. The
LOS RANGING register allows the LOS threshold value
to scale. The LOS LO quick trip can be used to set the
LOSOUT pin. LOS HI does not set LOSOUT. See the
description of the LOS LO and LOS HI bits (Table 01h,
Register FBh) for further details of operation.
The quick trips are routed to create TXFOUT through
interrupt masks to allow combinations of these alarms
to be used to trigger the outputs.
Six ADC Monitors and Alarms
The ADC monitors six channels that measure tempera-
ture (internal temp sensor), VCC, and MON1–MON4
using an analog multiplexer to measure them round
robin with a single ADC (see the
ADC Timing
section).
The five voltage channels have a customer-programma-
ble full-scale range and all channels have a customer-
programmable offset value that is factory programmed to
default value (see Table 3). Additionally, MON1–MON4
can right-shift results by up to 7 bits before the results
are compared to alarm thresholds or read over the I2C
bus. This allows customers with specified ADC ranges to
calibrate the ADC full scale to a factor of 1/2nof their
specified range to measure small signals. The device
can then right-shift the results by n bits to maintain the bit
weight of their specification (see the
Right-Shifting ADC
Result
and
Enhanced RSSI Monitoring (Dual-Range
Functionality)
sections).
The ADC results (after right-shifting, if used) are com-
pared to the alarm and warning thresholds after each
conversion, and the corresponding alarms are set,
which can be used to trigger the TXFOUT output.
These ADC thresholds are user programmable, as are
the masking registers that can be used to prevent the
alarms from triggering the TXFOUT output.
ADC Timing
There are six analog channels that are digitized in a
round-robin fashion in the order shown in Figure 5. The
total time required to convert all six channels is tRR (see
the
Analog Voltage Monitoring Characteristics
for
details).
Table 3. ADC Default Monitor Full-Scale Ranges
SIGNAL (UNITS) +FS SIGNAL +FS HEX -FS SIGNAL -FS HEX
Temperature C) 127.996 7FFF -128 8000
VCC (V) 6.5528 FFF8 0 0000
MON1MON4 (V) 2.4997 FFF8 0 0000
ii [VI/JXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 17
Right-Shifting ADC Result
If the weighting of the ADC digital reading must con-
form to a predetermined full-scale (PFS) value defined
by a standard’s specification (e.g., SFF-8472), then
right-shifting can be used to adjust the PFS analog
measurement range while maintaining the weighting of
the ADC results. The device’s range is wide enough to
cover all requirements; when the maximum input value
is 1/2 of the FS value, right-shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8 the specified PFS value, so only
1/8 the converter’s range is effective over this range.
An alternative is to calibrate the ADC’s full-scale range
to 1/8 the readable PFS value and use a right-shift
value of 3. With this implementation, the resolution of
the measurement is increased by a factor of 8, and
because the result is digitally divided by 8 by right-
shifting, the bit weight of the measurement still meets
the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of right-shift control registers
(Table 02h, Registers 8Eh–8Fh) in EEPROM. Three ana-
log channels, MON1–MON3, each have 3 bits allocated
to set the number of right-shifts. Up to seven right-shift
operations are allowed and are executed as a part of
every conversion before the results are compared to
the high-alarm and low-alarm levels, or loaded into their
corresponding measurement registers (Lower Memory,
Registers 64h–6Bh). This is true during the setup of
internal calibration as well as during subsequent data
conversions.
V
CC
or GND Referenced MON2 Input
The device offers a configurable input for MON2.
MON2 can either be referenced to VCC or GND, as
shown in Figure 6. This enables compatibility with dif-
ferent TOSA monitor diode configurations.
Differential MON3 Input
The device offers a fully differential input for MON3.
This enables high-side monitoring of RSSI, as shown in
Figure 7. This reduces board complexity by eliminating
the need for a high-side differential amplifier or a cur-
rent mirror.
DS1878
MON3P
MON3N ADC
680Ω
ROSA
VCC
Figure 7. MON3 Differential Input for High-Side RSSI
MON2
BMD
ADC
VCC
VCC
1kΩ
MON2
BMD
ADC
VCC
VCC
1kΩ
Figure 6. MON2 V
CC
or GND Reference
TEMP VCC MON1 MON2 MON3 MON4 TEMP
ONE ROUND-ROBIN ADC CYCLE
tRR
NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC
IS ABOVE THE VCC ALARM LOW THRESHOLD.
Figure 5. ADC Round-Robin Timing
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
18 ______________________________________________________________________________________
Enhanced RSSI Monitoring (Dual-Range
Functionality)
The device offers a feature to improve the accuracy
and range of MON3, which is most commonly used for
monitoring RSSI. Using a traditional input, the accuracy
of the RSSI measurements is increased at the cost of
reduced input signal swing. The device eliminates this
trade-off by offering “dual range” calibration on the
MON3 channel.
The dual-range calibration can operate in two modes:
crossover enabled and crossover disabled.
Crossover Enabled: For systems with a nonlinear
relationship between the ADC input and desired ADC
result, the mode should be set to crossover enabled
(Figure 8). The RSSI measurement of an APD receiv-
er is one such application. Using the crossover
enabled mode allows a piecewise linear approxima-
tion of the nonlinear response of the APD’s gain fac-
tor. The crossover point is the point between fine and
coarse points. The ADC result transitions between the
fine and coarse ranges with no hysteresis. Right-shift-
ing, slope adjustment, and offset are configurable for
both the fine and coarse ranges. The XOVER FINE
register determines the maximum results returned by
fine ADC conversions, before right-shifting. The
XOVER COARSE register determines the minimum
results returned by coarse ADC conversions, before
right-shifting.
• Crossover Disabled: The crossover disabled mode
is intended for systems with a linear relationship
between the MON3 input and desired ADC result.
The ADC result transitions between the fine and
coarse ranges with hysteresis (Figure 9). In crossover
disabled mode, the thresholds between coarse and
fine mode are a function of the number of right-shifts
being used. With the use of right-shifting, the fine-
mode full scale is programmed to (1/2nth) of the
coarse-mode full scale. The device now auto ranges
to choose the range that gives the best resolution for
the measurement. Table 4 shows the threshold val-
ues for each possible number of right-shifts.
CROSSOVER POINT
RSSI RESULT
IDEAL RESPONSE MON3 INPUT
Figure 8. RSSI with Crossover Enabled
Table 5. MON3 Configuration Registers
REGISTER FINE MODE COARSE MODE
GAIN 98h–99h, Table 02h 9Ch–9Dh, Table 02h
OFFSET A8hA9h, Table 02h AChADh, Table 02h
RIGHT-SHIFT08Fh, Table 02h 8Fh, Table 02h
CNFGC
(RSSI_FC and
RSSI_FF Bits)
8Bh, Table 02h
UPDATE
(RSSIR Bit) 6Fh, Lower Memory
MON3 VALUE 68h–69h, Lower Memory
NUMBER OF
RIGHT-SHIFTS
FINE MODE
MAX (HEX)
COARSE MODE
MIN* (HEX)
0 FFF8 F000
1 7FFC 7800
2 3FFE 3C00
3 1FFF 1E00
4 0FFF 0F00
5 07FF 0780
6 03FF 03C0
7 01FF 01E0
Table 4. MON3 Hysteresis Threshold Values
*
This is the minimum reported coarse-mode conversion.
[VI/JXI [VI
DS1878
Low-Voltage Operation
The device contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the
supply voltage rises above POA, the outputs are dis-
abled, all SRAM locations are set to their defaults,
shadowed EEPROM (SEE) locations are zero, and all
analog circuitry is disabled. When VCC reaches POA,
the SEE is recalled, and the analog circuitry is enabled.
While VCC remains above POA, the device is in its nor-
mal operating state, and it responds based on its non-
volatile configuration. If during operation VCC falls
below POA, but is still above POD, then the SRAM
retains the SEE settings from the first SEE recall, but the
device analog is shut down and the outputs disabled. If
the supply voltage recovers back above POA, then the
device immediately resumes normal operation. If the
supply voltage falls below POD, then the device SRAM
is placed in its default state and another SEE recall is
required to reload the nonvolatile settings. The
EEPROM recall occurs the next time VCC exceeds
POA. Figure 10 shows the sequence of events as the
voltage varies.
Any time VCC is above POD, the I2C interface can be
used to determine if VCC is below the POA level. This is
accomplished by checking the RDYB bit in the STATUS
(Lower Memory, Register 6Eh) byte. RDYB is set when
VCC is below POA; when VCC rises above POA, RDYB
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 19
VPOA
VPOD
VCC
SEE RECALLED VALUE RECALLED VALUE
PRECHARGED
TO 0
PRECHARGED
TO 0
PRECHARGED TO 0
SEE RECALL SEE RECALL
Figure 10. Low-Voltage Hysteresis Example
RSSI RESULT
FINE FULL-SCALE RESPONSE
COARSE FULL-SCALE RESPONSE
FINE RIGHT-SHIFT = 3
MON3 INPUT
FINE COARSE
HYSTERESIS
Figure 9. RSSI with Crossover Disabled
fl U \ IT U LJLL [MAXI/VI [VIIJXIIM
DS1878
is timed (within 500µs) to go to 0, at which point the
part is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCC exceeds POA, allowing the device address to
be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the device in reset until VCC is at a suitable
level (VCC > POA) for the device to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because VCC cannot be measured by the
ADC when VCC is less than POA, POA also asserts the
VCC LO alarm, which is cleared by a VCC ADC conver-
sion greater than the customer-programmable VCC LO
ADC limit. This allows a programmable limit to ensure
that the headroom requirements of the transceiver are
satisfied during a slow power-up. The TXFOUT output
does not latch until there is a conversion above the
VCC LO limit. The POA alarm is nonmaskable. The TXF
output is asserted when VCC is below POA. See the
Low-Voltage Operation
section for more information.
Delta-Sigma Outputs (DAC1 and DAC2)
Two delta-sigma outputs are provided, DAC1 and
DAC2. With the addition of an external RC filter, these
outputs provide two 9-bit resolution analog outputs with
the full-scale range set by the input REFIN. Each output
is either manually controlled or controlled using a tem-
perature-indexed LUT. A delta-sigma is a digital output
using pulse-density modulation. It provides much lower
output ripple than a standard digital PWM output given
the same clock rate and filter components. Before tINIT,
the DAC1 and DAC2 outputs are high impedance.
The external RC filter components are chosen based
on ripple requirements, output load, delta-sigma fre-
quency, and desired response time. A recommended
filter is shown in Figure 11.
The device’s delta-sigma outputs are 9 bits. For illustra-
tive purposes, a 3-bit example is provided in Figure 12.
20 ______________________________________________________________________________________
DS1878
DAC
3.24kΩ3.24kΩ
0.01μF 0.01μF
VOLTAGE OUTPUT
DS1878
DAC
1kΩ1kΩ
0.1μF 0.1μF
CURRENT SINK
2kΩ
SFP+ Controller with Digital LDD Interface
O
1
2
3
4
5
6
7
Figure 12. Delta-Sigma Outputs
Figure 11. Recommended RC Filter for DAC1/DAC2
[VI/JXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 21
LUT LOADED TO [7:0] LUT LOADED TO [7:0]
DAC[1/2]TI
8
7
6
5
4
3
2
1
0
DAC[1/2]TI
DAC[1/2]TC = 0
TEMPERATURE (°C)
-40 +102 TEMPERATURE (°C)
-40 +102
DAC[1/2]TC = 1
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
DELTA-SIGMA DACA OR DACB
8
7
6
5
4
3
2
1
0
DELTA-SIGMA DACA OR DACB
Figure 13. DAC1/DAC2 LUT Assignments
In LUT mode, DAC1 and DAC2 are each controlled by
a separate 8-bit, 4°C-resolution, temperature-
addressed LUT. The delta-sigma outputs use a 10-bit
structure. The 8-bit LUTs are either loaded directly into
the MSBs (8:1) or the LSBs (7:0). This is determined by
DAC1TI (Table 02h, Register C3h), DAC2TI (Table 02h,
Register C4h), DAC1TC (Table 02h, Register C6h, bit
6), and DAC2TC (Table 02h, Register C6h, bit 5). See
Figure 13 for more details. The DAC1 LUT (Table 07h)
and DAC2 LUT (Table 08h) registers are nonvolatile
and password-2 protected.
The reference input, REFIN, is the supply voltage for
the output buffer of DAC1 and DAC2. The voltage con-
nected to REFIN must be able to support the edge rate
requirements of the delta-sigma outputs. In a typical
application, a 0.1µF capacitor should be connected
between REFIN and ground.
Digital I/O Pins
Five digital input and four digital output pins are provid-
ed for monitoring and control.
LOS, LOSOUT
By default (LOSC = 1, Table 02h, Register 89h), the
LOS pin is used to convert a standard comparator out-
put for loss of signal (LOS) to an open-collector output.
This means the mux shown in the
Block Diagram
by
default selects the LOS pin as the source for the
LOSOUT output transistor. The output of the mux can
be read in the STATUS byte (Lower Memory,
Register 6Eh) as the RXL bit. The RXL signal can be
inverted (INV LOS = 1) before driving the open-drain
output transistor using the XOR gate provided. Setting
LOSC = 0 configures the mux to be controlled by LOS
LO, which is driven by the output of the LOS quick trip
(Table 02h, Registers BEh and BFh). The mux setting
(stored in EEPROM) does not take effect until VCC >
POA, allowing the EEPROM to recall.
[VIIJXIIM
DS1878
IN1, RSEL, RSELOUT
The digital input IN1 and RSEL pins primarily serve to
meet the rate-select requirements of SFP and SFP+.
They also serve as general-purpose inputs. RSELOUT is
driven by a combination of the RSEL and logic dictated
by control registers in the EEPROM (Figure 16). The lev-
els of IN1 and RSEL can be read using the STATUS reg-
ister (Lower Memory, Register 6Eh). The open-drain
RSELOUT output is software-controlled and/or inverted
through the STATUS register and CNFGA register
(Table 02h, Register 89h). External pullup resistors must
be provided on RSELOUT to realize a high logic level.
The RSEL pin determines the value sent by the 3-wire
master to the limiting amplifier’s SETLOS register. When
RSEL is high, SETLOSH is used. When RSEL is low,
SETLOSL is used. The DS1878 can transmit a bit on the
3-wire bus to Register 0x00 (bit 1) of the MAX3945,
MAX3798, MAX3799, or RXCTRL1 (Table 02h, Register
E8h) within 80ms of a transition (rising or falling) on the
RSELOUT. This bit indicates the status of RSELOUT.
This feature is user programmable. A bit (RSELPIN,
Table 02h, Register 89h) is provided to determine
whether the I2C register RXCTRL1 or the status of the
RSELOUT pin is transmitted. When RSELPIN is set to 1,
the status of RSELOUT is sent out. RSELOUT is deter-
mined by RSEL pin, RSELC control bit, and INVRSOUT
control bit as shown in Figure 14.
The INVRSOUT bit inverts the RSELOUT bit, and this
inversion is reflected when this bit is sent out on the 3-
wire bus. Figure 14 illustrates the timing for the 3-wire
communication when RSELPIN is set to 1.
TXD, TXDOUT
TXDOUT is generated from a combination of TXFOUT,
TXD, and the internal signal FETG. A software control
identical to TXD is available (TXDC, Lower Memory,
Register 6Eh). A TXD pulse is internally extended
(tINITR1) to inhibit the latching of low alarms and warn-
ings related to the APC loop to allow for the loop to sta-
bilize. The nonlatching alarms and warnings are TXP
SFP+ Controller with Digital LDD Interface
22 ______________________________________________________________________________________
VPOA
VCC
RSEL
RSELOUT
3W 0x00 BIT1
< 1μs
< 1μs
< 80ms
POV = 0
CONDITION: INVRSOUT = 0, RSELPIN = 1.
< 80ms
Figure 14. 3-Wire Communication on RSELOUT Transition
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 23
LO, LOS LO, and MON1–MON4 LO alarms and warn-
ings. In addition, TXP LO is disabled from creating
FETG. See the
Transmit Fault (TXFOUT) Output
section
for a detailed explanation of TXFOUT. Figure 15 shows
that the same signals and faults can also be used to
generate the internal signal FETG (Table 01h/05h,
Registers FAh–FBh). FETG is used to send a fast “turn-
off” command to the laser driver. The status of FTEG
can be read (Lower Memory, Register 71h). The intend-
ed use is a direct connection to the Maxim laser driver’s
TXD input if this is desired. When VCC < POA, TXDOUT
is high impedance.
Transmit Fault (TXFOUT) Output
TXFOUT can be triggered by TXF input and all alarms,
warnings, and quick trips (Figure 16). The six ADC
alarms, warnings, and the LOS quick trips require
enabling (Table 01h/05h, Registers F8h, FCh–FDh). See
Figures 17a and 17b for nonlatched and latched opera-
tion. Latching of the alarms is controlled by the CNFGB
and CNFGC registers (Table 02h, Registers 8Ah–8Bh).
INVRSOUT
RSELC
RSEL
RSELS
IN1S
RSELOUT
LOSC
MUX
LOS LO
RXL
SETLOSCTL
LOS
INV LOS
IN1
LOSOUT
PINS
Figure 16. Logic Diagram 2
C
C
D
Q
Q
S
R
OUT IN
TXDS
RPU
TXFS
TXFOUTS
SET BIAS REGISTER
AND MODULATION
REGISTER TO 0
TXD
TXFINT
TXP HI FLAG
TXP HI ENABLE
BIAS MAX
BIAS MAX ENABLE
HBAL FLAG
HBAL ENABLE
TXP LO FLAG
TXP LO ENABLE
tINITR1
TXDC
VCC
TXD
TXDOUT
TXDIO
TXDFG
FETG
TXDFLT
FAULT RESET TIMER
(130ms)
IN
OUT
POWER-ON
RESET PINS
INVTXF
TXF
TXFOUT
Figure 15. Logic Diagram 1
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
24 ______________________________________________________________________________________
DETECTION OF TXF FAULT
TXD OR TXF RESET
tINITR1/2
TXFOUT
(ONLY ALARM FAULTS PRESENT)
TXFOUT
(QT ALARMS PRESENT)
Figure 17b. TXFOUT Latched Operation and TXD_TXFEN = 1
DETECTION OF TXF FAULT
TXFOUT
Figure 17a. TXFOUT Nonlatched Operation
By default, TXD does not impact TXFOUT (TXD_TXFEN =
0). This is shown in the Figure 17c. When TXD_TXFEN
= 1, TXD affects TXFOUT. The particular behavior is
described in Figure 17a and 17b.
VCCTXF is a new control bit is required to enable/dis-
able VCC LO alarm/warning before the first VCC con-
version is complete. If VCCTXF = 1, VCC LO
alarm/warning does not generate TXFOUT before the
first VCC conversion (which takes approximately 13ms
to complete). When VCCTXF = 0, VCC LO alarm/warn-
ing generates TXFOUT before the first VCC conversion,
which is illustrated in Figure 17c and Figure 17d.
Two conditions are shown. In the first instance, VCC
powers on quickly and goes above the VCC LO thresh-
old before the first conversion is complete (approxi-
mately 13ms).
In the other instance, VCC would power up and go
above the VCC LO threshold after the first conversion is
complete. In this case TXFOUT behaves as in
Figure 17d.
[VI/JXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 25
Figure 17c. TXFOUT When TXD_TXFEN = 0 on Fast Power-On
VCC VCC LO (ASSUMES VCC LO > VPOA)
VCC LO (ASSUMES VCC LO > VPOA)
TXD OR
SOFT TXD
TXFOUT (1)
TXFOUT (2)
VCC LO
ALARM
VCC
TXD OR
SOFT TXD
TXFOUT (1)
TXFOUT (2)
VCC LO
ALARM
CONDITION 1: VCCTXF = 0, ANY STATE OF VCC LO ALARM OR WARNING FLAG.
CONDITION 2: VCCTXF = 1, ANY STATE OF VCC LO ALARM OR WARNING FLAG.
CONDITION 1: VCCTXF = 0, ANY STATE OF VCC LO ALARM OR WARNING FLAG.
CONDITION 2: VCCTXF = 1, ANY STATE OF VCC LO ALARM OR WARNING FLAG.
< 13ms
< 13ms
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
26 ______________________________________________________________________________________
Figure 17d. TXFOUT When TXD_TXFEN = 0 on Slow Power-On
Die Identification
The DS1878 has an ID hardcoded in its die. Two regis-
ters (Table 02h, Registers CEh–CFh) are assigned for
this feature. The CEh register reads 78h to identify the
part as the DS1878, while the CFh register reads the
current device version.
3-Wire Master for Controlling
the Maxim Laser Driver and
Limiting Amplifier
The device controls a Maxim laser driver and limiting
amplifier over a proprietary 3-wire interface. The device
acts as the master, initiating communication with and
generating the clock for the Maxim slave device(s). It is
a 3-pin interface consisting of SDAOUT (a bidirectional
data line), SCLOUT (clock signal), and a chip-select
output (active high). Two chip selects are provided.
CSEL1OUT is active during all communications.
CSEL2OUT is only active during communications to the
limiting amplifier. By connecting CSEL2OUT to a Maxim
limiting amplifier, there is less noise induced by the
communication interface on the limiting amplifier, since
none of the laser driver communications are processed
by the limiting amplifier.
Protocol
The device initiates a data transfer by asserting the
CSEL_OUT pin. It then starts to generate a clock signal
after CSEL_OUT has been set to 1. Each operation
consists of 16-bit transfers (15-bit address/data, 1-bit
RWN). All data transfers are MSB first.
Write Mode (RWN = 0): The master generates 16 clock
cycles at SCLOUT in total. It outputs 16 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
master closes the transmission by setting CSEL_OUT to
0.
Read Mode (RWN = 1): The master generates 16 clock
cycles at SCLOUT in total. It outputs 8 bits (MSB first)
to the SDAOUT line at the falling edge of the clock. The
SDAOUT line is released after the RWN bit has been
transmitted. The slave outputs 8 bits of data (MSB first)
at the rising edge of the clock. The master samples
SDAOUT at the falling edge of SCLOUT. The master
closes the transmission by setting CSEL_OUT to 0.
BIT NAME DESCRIPTION
15:9 Address 7-bit internal register address
8 RWN 0: write; 1: read
7:0 Data 8-bit read or write data
VPOA
VCC
TXD OR
SOFT TXD*
TXFOUT (1)
TXFOUT (2)
CONDITION 1: VCCTXF = 0, VCC LO ALARM OR WARNING FLAG ENABLED TO CREATE TXFOUT.
CONDITION 2: VCCTXF = 1 and (VCC LO ALARM OR WARNING FLAG IS ENABLED).
*DON'T CARE ABOUT TXD STATE.
VCC-LO
13ms
< tRR
[VI/JXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 27
CSEL_OUT
SCLOUT
SDAOUT
CSEL_OUT
NOTE: SEE THE 3-WIRE DIGITAL INTERFACE SPECIFICATION TABLE FOR DETAILS. CSEL_OUT IMPLIES CSEL1OUT OR CSEL2OUT.
SCLOUT
SDAOUT
12345678
A6
9 1011121314150
1234567891011121314150
A5 A4 A3 A2 A1 RWN D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0RWN
WRITE MODE
READ MODE
A0
A6 A5 A4 A3 A2 A1 A0
tLtCH tCL
tCH tCL
tL
tDS
tDH
tDS tRS
tDH
tT
tT
Figure 18. 3-Wire Timing
3-Wire Interface Timing
Figure 18 shows the 3-wire interface timing. Figure 19
shows the 3-wire state machine. See the
3-Wire Digital
Interface Specification
table for more information.
DS1878 Master Communication
Interface
Normal Operation
The majority of the communications consist of bias
adjustments for the APC loop. After each temperature
conversion, the laser modulation setting must be updat-
ed. All registers are rewritten after every temperature
conversion. Status registers TXSTAT1 and TXSTAT2 are
read between temperature updates at a regular inter-
val, tRR (see the
Analog Voltage Monitoring
Characteristics
table). The results are stored in 3W
TXSTAT1 and 3W TXSTAT2 (Table 02h, FCh–FDh). Two
chip selects are provided: CSEL1OUT and CSEL2OUT.
In the case where a separate limiting amplifier and
laser driver are used, CSEL2OUT should be connected
to the limiting amplifier. CSEL2OUT is only active when
receiver-related registers are accessed. This minimizes
noise caused by the digital interface.
Manual Operation
The master interface is controllable using four registers in
the device: 3WCTRL, ADDRESS, WRITE, and READ.
Commands can be manually issued while the device is
in normal operation mode. It is also possible to suspend
normal 3-wire commands so that only manual operation
commands are sent (3WCTRL, Table 02h, Register F8h).
Initialization
During initialization, the device transfers all its 3-wire
EEPROM control registers to a Maxim laser driver and
limiting amplifier. The 3-wire control registers include
the following:
• RXCTRL1
• RXCTRL2
• SETCML
• SETLOS
• TXCTRL
• IMODMAX
• IBIASMAX
• SETPWCTL
• SETTXDE
• SETTXEQ
• SETLOSTIMER
• RXCTRL3
• TXCTRL2
• TXCTRL3
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
28 ______________________________________________________________________________________
The control registers are first written once VCC exceeds
POA. They are also written after every temperature con-
version and on a rising edge of TXD. Any time one of
these events occurs, the device reads and updates
TXSTAT1 and TXSTAT2, and writes SET_IBIAS and
SET_IMOD to 0.
Slave Register Map and DS1878 Corresponding Location
SLAVE REGISTER
AND ADDRESS
DS1878
REGISTER
ACTIVE CHIP
SELECTS REGISTER FUNCTION DS1878 LOCATION
00h, RXCTRL1 RXCTRL1 1 and 2 Receiver Control Table 02h, E8h
01h, RXCTRL2 RXCTRL2 1 and 2 Receiver Control Table 02h, E9h
02h, RXSTAT STATUS 1 and 2 Receiver Status Lower Memory, 6Eh, Bit 1 comes from
the LOSOUT pin (Note 1)
03h, SET_CML SETCML 1 and 2
Output CML Level
Setting Table 02h, EAh
04h, SET_LOS SETLOSH,
SETLOSL 1 and 2 LOS Assert Level
Settings
Table 02h, EBh is SETLOSH,
Table 02h, F3h is SETLOSL (Note 2)
05h, TXCTRL TXCTRL 1 Only (Note 3) Transmitter Control Table 02h, ECh
06h, TXSTAT1 TXSTAT1 1 Only (Note 3) Transmitter Status Table 02h, FCh
07h, TXSTAT2 TXSTAT2 1 Only (Note 3) Transmitter Status Table 02h, FDh
08h, SET_IBIAS BIAS 1 Only (Note 3) BIAS Current Setting Table 02h, CBhCCh
09h, SET_IMOD MODULATION 1 Only (Note 3) MODULATION Current
Setting Table 02h, 82h–83h
0Ah, SET_IMODMAX IMODMAX 1 Only (Note 3) MODULATION Current
Limit Setting Table 02h, EDh
0Bh, SET_IBIASMAX IBIASMAX 1 Only (Note 3) BIAS Current Limit
Setting Table 02h, EEh
0Ch, MODINC MODINC 1 Only (Note 3) MODULATION Current
DAC Increment Setting
Automatically written after each
temperature conversion.
0Dh, BIASINC BIASINC 1 Only (Note 3) BIAS Current DAC
Increment Setting
Automatically performed by APC loop.
Disable APC before using 3-wire
manual mode.
0Eh, MODECTRL MODECTRL 1 and 2 General Control (Note 1)
0Fh, SET_PWCTRL SETPWCTRL 1 Only (Note 3) Tx Pulse Width Setting Table 02h, EFh
10h, SET_TXDE SETTXDE 1 Only (Note 3) Tx Deemphasis Setting Table 02h, F0h
11h, SET_TXEQ SETTXEQ 1 Only (Note 3) Tx Equalization Table 02h, F1h
12h, SET_LOSTIMER SETLOSTIMER 1 and 2 LOS Timer Table 02h, F2h
14h, TXTM TXTM 1 and 2 Tx Test Mode (Note 1)
15h, RXTM1 RXTM1 1 and 2 Rx Test Mode (Note 1)
16h, RXTM2 RXTM2 1 and 2 Rx Test Mode (Note 1)
17h, Reserved RXCTRL3 1 and 2 Receiver Control Table 02h, F4h
18h, Reserved TXCTRL2 1 Only (Note 3) Transmitter Control Table 02h, F5h
19h, Reserved TXCTRL3 1 Only (Note 3) Transmitter Control Table 02h, F6h
Note 1: This register is not present in the DS1878. To access this register the user must use manual operation (see the
Manual
Operation
section for details).
Note 2: Either SETLOSH or SETLOSL is written to the slave register SET_LOS. This is determined by the signal RSEL (see Figure 16).
Note 3: In manual 3-wire mode both chip selects are active for all registers.
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 29
POR OR TXD
READ TXPOR
3-WIRE STATE MACHINE
READ TXPOR
CONTROL/STATUS
INITIALIZATION
WAIT FOR MOD
(SET MOD_FLAG)
WRITE MOD
(RESET FLAGS)
TXD_STANDBY
(SET TXD_FLAG)
TXPOR = = 1?
MANMODE = = 1?
TXD_FLAG = = 1?
OR MOD_FLAG = 1?
OR DIS3W = 1?
BIASINC = = 1?
WAIT FOR BIAS
READ/WRITE
MANMODE
STANDBY
INCREMENT BIAS
CONTROL/STATUS
UPDATE
MODINC = = 1?
BIASINC = = 1?
TEMP_CONV = = 1?
AND DIS3W = 0
APC_BINARY = = 0?
TXD_ext = = 0?
TXPOR = = 1?
TXD = = 0?
TXD_FLAG = = 1?
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
MODINC = = 1?
YES
DIS3W = 1?
OR BIAS_MANUAL = 1?
TXD_FLAG = = 1?
OR MOD_FLAG = 1
INCREMENT
MODULATION
YES
YES
Figure 19. 3-Wire State Machine
DS1878
SFP+ Controller with Digital LDD Interface
30 ______________________________________________________________________________________
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP START REPEATED
START
tBUF
tHD:STA
tHD:DAT tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
Figure 20. I
2
C Timing
I2C Communication
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Master device: The master device controls the
slave devices on the bus. The master device gen-
erates SCL clock pulses and START and STOP
conditions.
Slave devices: Slave devices send and receive
data at the master’s request.
Bus idle or not busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
START condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 20 for applicable timing.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 20 for applicable timing.
Repeated START condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 20 for applicable timing.
Bit write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements
(Figure 20). Data is shifted into the device during the
rising edge of the SCL.
Bit read: At the end a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 20) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse and the data bit is valid at the rising edge
of the current SCL pulse. Remember that the master
generates all SCL clock pulses, including when it is
reading bits from the slave.
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not acknowledge (NACK) is
always the ninth bit transmitted during a byte trans-
fer. The device receiving data (the master during a
read or the slave during a write operation) performs
an ACK by transmitting a zero during the ninth bit. A
device performs a NACK by transmitting a one dur-
ing the 9th bit. Timing (Figure 20) for the ACK and
NACK is identical to all other bit writes. An ACK is
the acknowledgment that the device is properly
receiving data. A NACK is used to terminate a read
[VI/JXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 31
sequence or as an indication that the device is not
receiving data.
Byte write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write
definition and the acknowledgement is read using
the bit-read definition.
Byte read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave address byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/Wbit in the least significant bit.
The device responds to two slave addresses. The
auxiliary memory always responds to a fixed I2C
slave address, A0h. The Lower Memory and Tables
00h–08h respond to I2C slave addresses that can
be configured to any value between 00h–FEh using
the DEVICE ADDRESS byte (Table 02h, Register
8Ch). The user also must set the ASEL bit (Table
02h, Register 89h) for this address to be active. By
writing the correct slave address with R/W= 0, the
master indicates it will write data to the slave. If R/W
= 1, the master reads data from the slave. If an
incorrect slave address is written, the device
assumes the master is communicating with another
I2C device and ignores the communications until the
next START condition is sent. If the main device’s
slave address is programmed to be A0h, access to
the auxiliary memory is disabled.
Memory address: During an I2C write operation to
the device, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.
I2C Protocol
Writing a single byte to a slave: The master must
generate a START condition, write the slave address
byte (R/W= 0), write the memory address, write the
byte of data, and generate a STOP condition.
Remember the master must read the slave’s
acknowledgement during all byte-write operations.
Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W= 0),
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition. The device
writes 1 to 8 bytes (one page or row) with a single
write transaction. This is internally controlled by an
address counter that allows data to be written to
consecutive addresses without transmitting a memo-
ry address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages results in the address
counter wrapping around to the beginning of the
present row.
For example, a 3-byte write starts at address 06h
and writes 3 data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that address-
es 06h and 07h would contain 11h and 22h, respec-
tively, and the third data byte, 33h, would be written
to address 00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM
write time to elapse. Then the master can generate a
new START condition and write the slave address
byte (R/W= 0) and the first memory address of the
next memory row before continuing to write data.
Acknowledge polling: Any time a EEPROM page is
written, the device requires the EEPROM write time
(tWR) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write
time, the device does not acknowledge its slave
address because it is busy. It is possible to take
advantage of that phenomenon by repeatedly
addressing the device, which allows the next page to
be written as soon as the device is ready to receive
the data. The alternative to acknowledge polling is to
wait for maximum period of tWR to elapse before
attempting to write again to the device.
EEPROM write cycles: When EEPROM writes occur,
the device writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page
is written, bytes on the page that were not modified
during the transaction are still subject to a write
Emmmmmmm HH‘HH HH‘HH HH‘H H‘HH HH H H ‘ HH HH ‘ HH HH ‘ HH HH ‘ HH HH H H ‘ HH HH ‘ HH HH HH ‘ HH HH ‘ HH HH HH HH | [VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
32 ______________________________________________________________________________________
START
START STOP
SLAVE
ACK
SLAVE
ACK
STOP
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h
TO C8h AND C9h
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE READ
-READ C8h AND C9h
REPEATED
START
MASTER
NACK
10100010
A2h
10111010
BAh
SLAVE
ACK
START SLAVE
ACK
10100010
A2h
10100011
A3h
10111010
BAh
SLAVE
ACK
SLAVE
ACK
STOP
00000000
00h
STOP
SLAVE
ACK
STOP
01110101
75h
START SLAVE
ACK
10100010
A2h
11001000
C8h
SLAVE
ACK
SLAVE
ACK
00000001
01h
SLAVE
ACK DATA IN BAh
DATA
REPEATED
START
MASTER
ACK
START SLAVE
ACK
10100010
A2h
10100011
A3h
11001000
C8h
SLAVE
ACK
SLAVE
ACK DATA IN C8h
DATA
MASTER
NACK
DATA IN C9h
DATA
EXAMPLE I2C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
TYPICAL I2C WRITE TRANSACTION
A)
C)
B)
D)
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
REGISTER ADDRESS
MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ADDRESS*
1 0 1 0 0 0 1 R/W
MSB LSB
READ/
WRITE
Figure 21. Example I
2
C Timing
cycle. This can result in a whole page being worn out
over time by writing a single byte repeatedly. Writing
a page one byte at a time wears the EEPROM out
eight times faster than writing the entire page at
once. The device’s EEPROM write cycles are speci-
fied in the
Nonvolatile Memory Characteristics
table.
The specification shown is at the worst-case temper-
ature. It can handle approximately ten times that
many writes at room temperature. Writing to SRAM-
shadowed EEPROM memory with SEEB = 1 does not
count as an EEPROM write cycle when evaluating
the EEPROM’s estimated lifetime.
Reading a single byte from a slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the
slave, the master generates a START condition,
writes the slave address byte with R/W= 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the master
generates a START condition, writes the slave
address byte (R/W= 0), writes the memory address
where it desires to read, generates a repeated
START condition, writes the slave address byte (R/W
= 1), reads data with ACK or NACK as applicable,
and generates a STOP condition.
Memory Organization
The device features nine separate memory tables that
are internally organized into 8-byte rows.
The Lower Memory is addressed from 00h–7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the table-select byte.
Table 01h primarily contains user EEPROM (with PW1
level access) as well as alarm and warning-enable
bytes.
Table 02h is a multifunction space that contains config-
uration registers, scaling and offset values, passwords,
interrupt registers as well as other miscellaneous con-
trol bytes.
Table 04h contains a temperature-indexed LUT for
control of the modulation voltage. The modulation LUT
can be programmed in 2°C increments over the -40°C
to +102°C range.
[VI/JXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 33
Table 05h is empty by default. It can be configured to
contain the alarm- and warning-enable bytes from Table
01h, Registers F8h–FFh with the MASK bit enabled
(Table 02h, Register 89h). In this case Table 01h is
empty.
Table 06h contains a temperature-indexed LUT that
allows the APC set point to change as a function of
temperature to compensate for TE. The APC LUT has
36 entries that determine the APC setting in 4°C win-
dows between -40°C and +100°C.
Table 07h contains a temperature-indexed LUT for con-
trol of DAC1. The LUT has 36 entries that determine the
DAC setting in 4°C windows between -40°C and +100°C.
Table 08h contains a temperature-indexed LUT for con-
trol of DAC2. The LUT has 36 entries that determine the
DAC setting in 4°C windows between -40°C and +100°C.
Auxiliary Memory (device A0h) contains 256 bytes of
EE memory accessible from address 00h–FFh. It is
selected with the device address of A0h.
See the
Register Descriptions
section for more com-
plete details of each byte’s function, as well as for
read/write permissions for each byte.
Shadowed EEPROM
Many NV memory locations (listed within the
Register
Descriptions
section) are actually shadowed EEPROM
that are controlled by the SEEB bit in Table 02h,
Register 80h.
The device incorporates shadowed-EEPROM memory
locations for key memory addresses that can be writ-
ten many times. By default the shadowed-EEPROM bit,
SEEB, is not set and these locations act as ordinary
EEPROM. By setting SEEB, these locations function
like SRAM cells, which allow an infinite number of write
cycles without concern of wearing out the EEPROM.
Setting SEEB also eliminates the requirement for the
EEPROM write time, tWR. Because changes made with
SEEB enabled do not affect the EEPROM, these
changes are not retained through power cycles. The
power-on value is the last value written with SEEB dis-
abled. This function can be used to limit the number of
EEPROM writes during calibration or to change the
monitor thresholds periodically during normal opera-
tion helping to reduce the number of times EEPROM is
written.
EEPROM
(256 BYTES)
FFh
I2C ADDRESS A0h I2C ADDRESS A2h (DEFAULT)
AUXILIARY DEVICE
MAIN DEVICE
00h
ALARM-
ENABLE ROW
(8 BYTES)
PASSWORD ENTRY
(PWE) (4 BYTES)
TABLE-SELECT
BYTE
FFh
80h
F8h
TABLE 01h
EEPROM
(120 BYTES)
F7h
7Fh
00h
LOWER
MEMORY
3W CONFIG
FFh
80h
E8h
TABLE 02h
NONLOOKUP
TABLE CONTROL
AND
CONFIGURATION
REGISTERS
E7h
80h
TABLE 04h
MOD LUT
(72 BYTES)
C7h
F8h TABLE 05h
ALARM-ENABLE ROW
(8 BYTES) FFh
80h TABLE 06h
APC LUT
(36 BYTES) A3h
80h TABLE 07h
DAC1 LUT
(36 BYTES) A3h
80h TABLE 08h
DAC2 LUT
(36 BYTES) A3h
NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h.
IF ASEL = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN
TABLE 02h, REGISTER 8Ch.
NOTE 2: TABLE 00h DOES NOT EXIST.
NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE
MASK BIT IN TABLE 02h, REGISTER 89h.
Figure 22. Memory Map
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
34 ______________________________________________________________________________________
Register Descriptions
The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is locat-
ed in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two
memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For more
information about each of these bytes see the corresponding register description.
Lower Memory Register Map
LOWER MEMORY
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
00 <1>THRESHOLD0 TEMP ALARM HI TEMP ALARM LO TEMP WARN HI TEMP WARN LO
08 <1>THRESHOLD1 V
CC ALARM HI VCC ALARM LO VCC WARN HI VCC WARN LO
10 <1>THRESHOLD2 MON1 ALARM HI MON1 ALARM LO MON1 WARN HI MON1 WARN LO
18 <1>THRESHOLD3 MON2 ALARM HI MON2 ALARM LO MON2 WARN HI MON2 WARN LO
20 <1>THRESHOLD4 MON3 ALARM HI MON3 ALARM LO MON3 WARN HI MON3 WARN LO
28 <1>THRESHOLD5 MON4 ALARM HI MON4 ALARM LO MON4 WARN HI MON4 WARN LO
30–5F <1>EEPROM EE EE EE EE EE EE EE EE
60 <2>ADC
VALUES0TEMP VALUE VCC VALUE MON1 VALUE MON2 VALUE
68 <0>ADC
VALUES1
<2>MON3 VALUE <2>MON4 VALUE <2>RESERVED <0>STATUS <3>UPDATE
70 <2>ALARM/
WARN ALARM3ALARM2ALARM1 ALARM0 WARN3WARN2RESERVED
78 <0>TABLE
SELECT
<2>RESERVED <2>
RESERVED
<6>PWE MSW <6>PWE LSW <5>TBL
SEL
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
device
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
[VI/JXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 35
Table 01h Register Map
The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h
with the MASK bit (Table 02h, Register 89h). If the row is configured to exist in Table 05h, then these locations are
empty in Table 01h.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
TABLE 01h
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80BF <7>EEPROM EE EE EE EE EE EE EE EE
C0–F7 <8>EEPROM EE EE EE EE EE EE EE EE
F8 <8>ALARM
ENABLE
ALARM
EN3
ALARM
EN2
ALARM
EN1
ALARM
EN0WARN EN3WARN EN2RESERVED RESERVED
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
device
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
TBLSELFON < m="">DEVICE SETWVCTRL [VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
36 ______________________________________________________________________________________
Table 02h Register Map
TABLE 02h (PW2)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80 <0>CONFIG0<8>MODE <4>TINDEX <4>MODULATION
REGISTER
<4>DAC1 VALUE <4>DAC2 VALUE
88 <8>CONFIG1SAMPLE
RATE CNFGA CNFGB CNFGC DEVICE
ADDRESS RESERVED RSHIFT1RSHIFT0
90 <8>SCALE0XOVER COARSE VCC SCALE MON1 SCALE MON2 SCALE
98 <8>SCALE1MON3 FINE SCALE MON4 SCALE MON3 COARSE SCALE RESERVED
A0 <8>OFFSET0XOVER FINE VCC OFFSET MON1 OFFSET MON2 OFFSET
A8 <8>OFFSET1MON3 FINE OFFSET MON4 OFFSET MON3 COARSE OFFSET INTERNAL TEMP
OFFSET*
B0 <9>PWD VALUE PW1 MSW PW1 LSW PW2 MSW PW2 LSW
B8 <8>THRESHOLD LOS
RANGING
COMP
RANGING ISTEPH ISTEPL HTXP LTXP HLOS LLOS
C0 <8>PWD
ENABLE PW_ENA PW_ENB MODTI DAC1TI DAC2TI ISTEPTI LUTTC TBLSELPON
C8 <0>APC <4>MAN BIAS <4>MAN_
CNTL
<10>BIAS REGISTER <4>APC
DAC
<10>DEVICE
ID
<10>DEVICE
VER
D0 <8>HBATH
LUT HBATH HBATH HBATH HBATH HBATH HBATH HBATH HBATH
D8–E7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
E8 <8>3W
CONFIG0RXCTRL1 RXCTRL2 SETCML SETLOSL TXCTRL IMODMAX IBIASMAX SETPWCTRL
F0 <8>3W
CONFIG1SETTXDE SETTXEQ SETLOSTIMER SETLOSH RXCTRL3 TXCTRL2 TXCTRL3 3WSET
F8 <0>3W
CONFIG2
<8>3WCTRL <8>ADDRESS <8>WRITE <10>READ <10>TXSTAT1 <10>TXSTAT2 RESERVED RESERVED
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
device
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
*
The final result must be XORed with BB40h before writing to this register.
*
Do not write to this register.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
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SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 37
Table 04h Register Map
TABLE 04h (MODULATION LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–C7 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
device
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
Table 05h Register Map
Table 05h is empty by default. It can be configured to contain the alarm and warning-enable bytes from Table 01h,
Registers F8h–FFh with the MASK bit enabled (Table 02h, Register 89h). In this case Table 01h is empty.
TABLE 05h
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY
F8 <8>ALARM
ENABLE
ALARM
EN3
ALARM
EN2
ALARM
EN1
ALARM
EN0WARN EN3WARN EN2RESERVED RESERVED
Table 06h Register Map
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
TABLE 06h (APC LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–9F
<8>APC
LUT APC REF APC REF APC REF APC REF APC REF APC REF APC REF APC REF
A0
<8>APC
LUT APC REF APC REF APC REF APC REF RESERVED RESERVED RESERVED RESERVED
[VIIJXIIM
DS1878
SFP+ Controller with Digital LDD Interface
38 ______________________________________________________________________________________
Table 08h Register Map
TABLE 07h (DAC1 LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–9F <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
A0 <8>LUT7 DAC1 DAC1 DAC1 DAC1 RESERVED RESERVED RESERVED RESERVED
ACCESS
CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately PW2 N/A
All and
device
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
TABLE 08h (DAC2 LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–9F <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2
A0 <8>LUT8 DAC2 DAC2 DAC2 DAC2 RESERVED RESERVED RESERVED RESERVED
Table 07h Register Map
Auxiliary A0h Memory Register Map
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
AUXILIARY MEMORY (A0h)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
00–FF <5>AUX EE EE EE EE EE EE EE EE EE
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SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 39
Lower Memory Register Descriptions
Lower Memory, Register 00h–01h: TEMP ALARM HI
Lower Memory, Register 04h–05h: TEMP WARN HI
FACTORY DEFAULT 7FFFh
READ ACCESS All
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
00h, 04h S 26 2
5 2
4 2
3 2
2 2
1 2
0
01h, 05h 2-1 2
-2 2
-3 2
-4 2
-5 2
-6 2
-7 2
-8
BIT 7 BIT 0
Temperature measurement updates above this two’s complement threshold set corresponding alarm or warning
bits. Temperature measurement updates equal to or below this threshold clear alarm or warning bits.
Lower Memory, Register 02h–03h: TEMP ALARM LO
Lower Memory, Register 06h–07h: TEMP WARN LO
FACTORY DEFAULT 8000h
READ ACCESS All
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
02h, 06h S 26 2
5 2
4 2
3 2
2 2
1 2
0
03h, 07h 2-1 2
-2 2
-3 2
-4 2
-5 2
-6 2
-7 2
-8
BIT 7 BIT 0
Temperature measurement updates below this two’s complement threshold set corresponding alarm or warning
bits. Temperature measurement updates equal to or above this threshold clear alarm or warning bits.
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SFP+ Controller with Digital LDD Interface
40 ______________________________________________________________________________________
Lower Memory, Register 08h–09h: VCC ALARM HI
Lower Memory, Register 0Ch–0Dh: VCC WARN HI
Lower Memory, Register 10h–11h: MON1 ALARM HI
Lower Memory, Register 14h–15h: MON1 WARN HI
Lower Memory, Register 18h–19h: MON2 ALARM HI
Lower Memory, Register 1Ch–1Dh: MON2 WARN HI
Lower Memory, Register 20h–21h: MON3 ALARM HI
Lower Memory, Register 24h–25h: MON3 WARN HI
Lower Memory, Register 28h–29h: MON4 ALARM HI
Lower Memory, Register 2Ch–2Dh: MON4 WARN HI
FACTORY DEFAULT FFFFh
READ ACCESS All
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
08h, 0Ch,
10h, 14h, 18h,
1Ch, 20h,
24h, 28h, 2Ch
215 214 2
13 2
12 2
11 2
10 2
9 2
8
09h, 0Dh,
11h, 15h, 19h,
1Dh, 21h,
25h, 29h, 2Dh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Voltage measurement updates above this unsigned threshold set corresponding alarm or warning bits. Voltage
measurements equal to or below this threshold clear alarm or warning bits.
[VIIJXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 41
Lower Memory, Register 0Ah–0Bh: VCC ALARM LO
Lower Memory, Register 0Eh–0Fh: VCC WARN LO
Lower Memory, Register 12h–13h: MON1 ALARM LO
Lower Memory, Register 16h–17h: MON1 WARN LO
Lower Memory, Register 1Ah–1Bh: MON2 ALARM LO
Lower Memory, Register 1Eh–1Fh: MON2 WARN LO
Lower Memory, Register 22h–23h: MON3 ALARM LO
Lower Memory, Register 26h–27h: MON3 WARN LO
Lower Memory, Register 2Ah–2Bh: MON4 ALARM LO
Lower Memory, Register 2Eh–2Fh: MON4 WARN LO
FACTORY DEFAULT 0000h
READ ACCESS All
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
0Ah, 0Eh,
12h, 16h,
1Ah, 1Eh,
22h, 26h,
2Ah, 2Eh
215 214 2
13 2
12 2
11 2
10 2
9 2
8
0Bh, 0Fh,
13h, 17h,
1Bh, 1Fh,
23h, 27h,
2Bh, 2Fh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Voltage measurement updates below this unsigned threshold set corresponding alarm or warning bits. Voltage
measurements equal to or above this threshold clear alarm or warning bits.
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SFP+ Controller with Digital LDD Interface
42 ______________________________________________________________________________________
Lower Memory, Register 30h–5Fh: EE
FACTORY DEFAULT 00h
READ ACCESS All
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (EE)
30h5Fh EE EE EE EE EE EE EE EE
BIT 7 BIT 0
PW2 level access-controlled EEPROM.
POWER-ON VALUE 0000h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
60h S 26 2
5 2
4 2
3 2
2 2
1 2
0
61h 2-1 2
-2 2
-3 2
-4 2
-5 2
-6 2
-7 2
-8
BIT 7 BIT 0
Signed twos complement direct-to-temperature measurement.
Lower Memory, Register 60h–61h: TEMP VALUE
[VIIJXI [VI
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SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 43
Lower Memory, Register 6Ch–6Dh: RESERVED
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE
These registers are reserved.
POWER-ON VALUE 0000h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
62h, 64h,
66h, 68h,
6Ah
215 214 2
13 2
12 2
11 2
10 2
9 2
8
63h, 65h,
67h, 69h,
6Bh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Left-justified unsigned voltage measurement.
Lower Memory, Register 62h–63h: VCC VALUE
Lower Memory, Register 64h–65h: MON1 VALUE
Lower Memory, Register 66h–67h: MON2 VALUE
Lower Memory, Register 68h–69h: MON3 VALUE
Lower Memory, Register 6Ah–6Bh: MON4 VALUE
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SFP+ Controller with Digital LDD Interface
44 ______________________________________________________________________________________
POWER-ON VALUE X0XX 0XXXb
READ ACCESS All
WRITE ACCESS See below
MEMORY TYPE Volatile
Write Access N/A All N/A All All N/A N/A N/A
6Eh TXDS TXDC IN1S RSELS RSELC TXFOUTS RXL RDYB
BIT 7 BIT 0
BIT 7
TXDS: TXD Status Bit. Reflects the logic state of the TXD pin (read only).
0 = TXD pin is logic-low.
1 = TXD pin is logic-high.
BIT 6
TXDC: TXD Software Control Bit. This bit allows for software control that is identical to the TXD pin.
See the section on TXD for further information. Its value is wire-ORed with the logic value of the
TXD pin (writable by all users).
0 = (Default).
1 = Forces the device into a TXD state regardless of the value of the TXD pin.
BIT 5
IN1S: IN1 Status Bit. Reflects the logic state of the IN1 pin (read only).
0 = IN1 pin is logic-low.
1 = IN1 pin is logic-high.
BIT 4
RSELS: RSEL Status Bit. Reflects the logic state of the RSEL pin (read only).
0 = RSEL pin is logic-low.
1 = RSEL pin is logic-high.
BIT 3
RSELC: RSEL Software Control Bit. This bit allows for software control that is identical to the RSEL
pin. Its value is wire-ORed with the logic value of the RSEL pin to create the RSELOUT pins logic
value (writable by all users).
0 = (Default).
1 = Forces the device into a RSEL state regardless of the value of the RSEL pin.
BIT 2
TXFOUTS: TXFOUT Status. Indicates the state the open-drain output is attempting to achieve.
0 = TXFOUT is pulling low.
1 = TXFOUT is high impedance.
BIT 1
RXL: Reflects the driven state of the LOSOUT pin (read only).
0 = LOSOUT pin is driven low.
1 = LOSOUT pin is pulled high.
BIT 0
RDYB: Ready Bar.
0 = VCC is above POA.
1 = VCC is below POA and/or too low to communicate over the I2C bus.
Lower Memory, Register 6Eh: STATUS
[VIIJXI [VI
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 45
Lower Memory, Register 6Fh: UPDATE
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS All and device hardware
MEMORY TYPE Volatile
6Fh TEMP RDY VCC RDY MON1 RDY MON2 RDY MON3 RDY MON4 RDY RESERVED RSSIR
BIT 7 BIT 0
BITS 7:2
Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is
completed. These bits can be cleared so that a completion of a new conversion is verified.
BIT 1 RESERVED
BIT 0
RSSIR: RSSI Range. Reports the range used for conversion update of MON3.
0 = Fine range is the reported value.
1 = Coarse range is the reported value.
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SFP+ Controller with Digital LDD Interface
46 ______________________________________________________________________________________
POWER-ON VALUE 10h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
70h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
BIT 7
TEMP HI: High-alarm status for temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
TEMP LO: Low-alarm status for temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
VCC HI: High-alarm status for VCC measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
VCC LO: Low-alarm status for VCC measurement. This bit is set when the VCC supply is below the POA
trip point value. It clears itself when a VCC measurement is completed and the value is above the low
threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
BIT 3
MON1 HI: High-alarm status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 2
MON1 LO: Low-alarm status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 1
MON2 HI: High-alarm status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 0
MON2 LO: Low-alarm status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
Lower Memory, Register 70h: ALARM3
[VIIJXI [VI
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SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 47
Lower Memory, Register 71h: ALARM2
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
71h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED TXFS FETG TXFINT
BIT 7 BIT 0
BIT 7
MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 3 RESERVED
BIT 2
TXFS: Reflects the status of the TXF pin. The status also includes any inversion caused by the INVTXF
bit (read only).
0 = TXF pin is low (after any inversion caused by the INVTXF bit).
1 = TXF pin is high (after any inversion caused by the INVTXF bit).
BIT 1
FETG: Status of Internal Signal FETG. The FETG signal is part of the internal shutdown logic.
0 = FETG is low.
1 = FETG is high.
BIT 0
TXFINT: TXFOUT Interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with
their corresponding enable bits in addition to nonmaskable alarms TXP HI, TXP LO, BIAS MAX, and HBAL.
The enable bits are found in Table 01h/05h, Registers F8hFFh.
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SFP+ Controller with Digital LDD Interface
48 ______________________________________________________________________________________
Lower Memory, Register 72h: ALARM1
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
72h RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO
BIT 7 BIT 0
BITS 7:4 RESERVED
BIT 3
HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
BIT 2 RESERVED
BIT 1
TXP HI: High-Alarm Status TXP; Fast Comparison. A TXD event clears this alarm.
0 = (Default) Last comparison was below threshold setting.
1 = Last comparison was above threshold setting.
BIT 0
TXP LO: Low-Alarm Status TXP; Fast Comparison. A TXD event clears this alarm.
0 = (Default) Last comparison was above threshold setting.
1 = Last comparison was below threshold setting.
[VIIJXI [VI
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SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________ 49
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
73h LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED
BIT 7 BIT 0
BIT 7
LOS HI: High-Alarm Status for MON3; Fast Comparison. A TXD event does not clear this alarm.
0 = (Default) At POR, this is the state if the last comparison was below the HLOS threshold setting. See
the description of the set condition to determine what causes LOS HI to be reset.
1 = Last comparison was above the HLOS threshold setting. LOS HI stays set until the time MON3 goes
below the LLOS level, or a POR to the device causes LOS HI to reset if it is below the HLOS threshold.
BIT 6
LOS LO: Low-Alarm Status for MON3; Fast Comparison. A TXD event does not clear this alarm.
0 = (Default) At POR, this is the state if the last comparison was above the LLOS threshold setting. See
the description of the set condition to determine what causes LOS LO to be reset.
1 = Last comparison was below the LLOS threshold setting. LOS LO stays set until the time MON3 goes
above the HLOS level, or a POR to the device causes LOS LO to reset if it is below the LLOS threshold.
BITS 5:4 RESERVED
BIT 3
BIAS MAX: Alarm status for maximum digital setting of BIAS. A TXD event clears this alarm.
0 = (Default) The value for BIAS is equal to or below the IBIASMAX register.
1 = Requested value for BIAS is greater than the IBIASMAX register.
BITS 2:0 RESERVED
Lower Memory, Register 73h: ALARM0
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SFP+ Controller with Digital LDD Interface
50 ______________________________________________________________________________________
Lower Memory, Register 74h: WARN3
POWER-ON VALUE 10h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
74h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
BIT 7
TEMP HI: High-warning status for temperature measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
TEMP LO: Low-warning status for temperature measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
VCC HI: High-warning status for VCC measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
VCC LO: Low-warning status for VCC measurement. This bit is set when the VCC supply is below the POA
trip point value. It clears itself when a VCC measurement is completed and the value is above the low
threshold.
0 = Last measurement was equal to or above threshold setting.
1 = (Default) Last measurement was below threshold setting.
BIT 3
MON1 HI: High-warning status for MON1 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 2
MON1 LO: Low-warning status for MON1 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 1
MON2 HI: High-warning status for MON2 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 0
MON2 LO: Low-warning status for MON2 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
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SFP+ Controller with Digital LDD Interface
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Lower Memory, Register 75h: WARN2
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
75h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED
BIT 7 BIT 0
BIT 7
MON3 HI: High-warning status for MON3 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low-warning status for MON3 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High-warning status for MON4 measurement.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low-warning status for MON4 measurement.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BITS 3:0 RESERVED
POWER-ON VALUE 00h
READ ACCESS N/A
WRITE ACCESS N/A
MEMORY TYPE
These registers are reserved.
Lower Memory, Register 76h–7Ah: RESERVED
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SFP+ Controller with Digital LDD Interface
52 ______________________________________________________________________________________
Lower Memory, Register 7Bh–7Eh: PASSWORD ENTRY (PWE)
POWER-ON VALUE FFFF FFFFh
READ ACCESS N/A
WRITE ACCESS All
MEMORY TYPE Volatile
7Bh 231 230 2
29 2
28 227 2
26 2
25 2
24
7Ch 223 222 2
21 2
20 219 2
18 2
17 2
16
7Dh 215 214 2
13 2
12 2
11 2
10 2
9 2
8
7Eh 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
There are two passwords for the device. Each password is 4 bytes long. The lower level password (PW1) has all the
access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of
PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At
power-up, all PWE bits are set to 1. All reads at this location are 0.
POWER-ON VALUE TBLSELPON (Table 02h, Register C7h)
READ ACCESS All
WRITE ACCESS All
MEMORY TYPE Volatile
7Fh 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The upper memory tables of the device are accessible by writing the desired table value in this register. The power-on
value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h).
Lower Memory, Register 7Fh: TABLE SELECT (TBL SEL)
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Table 01h Register Descriptions
Table 01h, Register 80h–BFh: EEPROM
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A)
WRITE ACCESS PW2 or (PW1 and RWTBL1A)
MEMORY TYPE Nonvolatile (EE)
80hBFh EE EE EE EE EE EE EE EE
BIT 7 BIT 0
EEPROM for PW1 and/or PW2 level access.
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1B) or (PW1 and RTBL1B)
WRITE ACCESS PW2 or (PW1 and RWTBL1B)
MEMORY TYPE Nonvolatile (EE)
C0hF7h EE EE EE EE EE EE EE EE
BIT 7 BIT 0
EEPROM for PW1 and/or PW2 level access.
Table 01h, Register C0h–F7h: EEPROM
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Table 01h, Register F8h: ALARM EN3
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
F8h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h
or 05h.
BIT 7
TEMP HI:
0 = Disables interrupt from TEMP HI alarm.
1 = Enables interrupt from TEMP HI alarm.
BIT 6
TEMP LO:
0 = Disables interrupt from TEMP LO alarm.
1 = Enables interrupt from TEMP LO alarm.
BIT 5
VCC HI:
0 = Disables interrupt from VCC HI alarm.
1 = Enables interrupt from VCC HI alarm.
BIT 4
VCC LO:
0 = Disables interrupt from VCC LO alarm.
1 = Enables interrupt from VCC LO alarm.
BIT 3
MON1 HI:
0 = Disables interrupt from MON1 HI alarm.
1 = Enables interrupt from MON1 HI alarm.
BIT 2
MON1 LO:
0 = Disables interrupt from MON1 LO alarm.
1 = Enables interrupt from MON1 LO alarm.
BIT 1
MON2 HI:
0 = Disables interrupt from MON2 HI alarm.
1 = Enables interrupt from MON2 HI alarm.
BIT 0
MON2 LO:
0 = Disables interrupt from MON2 LO alarm.
1 = Enables interrupt from MON2 LO alarm.
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Table 01h, Register F9h: ALARM EN2
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
F9h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED
BIT 7 BIT 0
Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
BIT 7
MON3 HI:
0 = Disables interrupt from MON3 HI alarm.
1 = Enables interrupt from MON3 HI alarm.
BIT 6
MON3 LO:
0 = Disables interrupt from MON3 LO alarm.
1 = Enables interrupt from MON3 LO alarm.
BIT 5
MON4 HI:
0 = Disables interrupt from MON4 HI alarm.
1 = Enables interrupt from MON4 HI alarm.
BIT 4
MON4 LO:
0 = Disables interrupt from MON4 LO alarm.
1 = Enables interrupt from MON4 LO alarm.
BIT 3:0 RESERVED
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Table 01h, Register FAh: ALARM EN1
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
FAh RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO
BIT 7 BIT 0
Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see
Figure 15) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
BITS 7:4 RESERVED
BIT 3
HBAL:
0 = Disables interrupt from HBAL alarm.
1 = Enables interrupt from HBAL alarm.
BIT 2 RESERVED
BIT 1
TXP HI:
0 = Disables interrupt from TXP HI alarm.
1 = Enables interrupt from TXP HI alarm.
BIT 0
TXP LO:
0 = Disables interrupt from TXP LO alarm.
1 = Enables interrupt from TXP LO alarm.
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Table 01h, Register FBh: ALARM EN0
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
FBh LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED
BIT 7 BIT 0
Layout is identical to ALARM0 in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 89h) determines
whether this memory exists in Table 01h or 05h.
BIT 7
LOS HI: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS HI alarm.
1 = Enables interrupt from LOS HI alarm.
BIT 6
LOS LO: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS LO alarm.
1 = Enables interrupt from LOS LO alarm.
BITS 5:4 RESERVED
BIT 3
BIAS MAX: Enables alarm to create internal signal FETG (see Figure 15) logic.
0 = Disables interrupt from BIAS MAX alarm.
1 = Enables interrupt from BIAS MAX alarm.
BITS 2:0 RESERVED
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Table 01h, Register FCh: WARN EN3
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
F8h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO
BIT 7 BIT 0
Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h
or 05h.
BIT 7
TEMP HI:
0 = Disables interrupt from TEMP HI warning.
1 = Enables interrupt from TEMP HI warning.
BIT 6
TEMP LO:
0 = Disables interrupt from TEMP LO warning.
1 = Enables interrupt from TEMP LO warning.
BIT 5
VCC HI:
0 = Disables interrupt from VCC HI warning.
1 = Enables interrupt from VCC HI warning.
BIT 4
VCC LO:
0 = Disables interrupt from VCC LO warning.
1 = Enables interrupt from VCC LO warning.
BIT 3
MON1 HI:
0 = Disables interrupt from MON1 HI warning.
1 = Enables interrupt from MON1 HI warning.
BIT 2
MON1 LO:
0 = Disables interrupt from MON1 LO warning.
1 = Enables interrupt from MON1 LO warning.
BIT 1
MON2 HI:
0 = Disables interrupt from MON2 HI warning.
1 = Enables interrupt from MON2 HI warning.
BIT 0
MON2 LO:
0 = Disables interrupt from MON2 LO warning.
1 = Enables interrupt from MON2 LO warning.
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Table 01h, Register FDh: WARN EN2
POWER-ON VALUE 00h
READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
WRITE ACCESS PW2 or (PW1 and RWTBL1C)
MEMORY TYPE Nonvolatile (SEE)
F9h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED
BIT 7 BIT 0
Layout is identical to WARN2 in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory,
Register 71h) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or
05h.
BIT 7
MON3 HI:
0 = Disables interrupt from MON3 HI warning.
1 = Enables interrupt from MON3 HI warning.
BIT 6
MON3 LO:
0 = Disables interrupt from MON3 LO warning.
1 = Enables interrupt from MON3 LO warning.
BIT 5
MON4 HI:
0 = Disables interrupt from MON4 HI warning.
1 = Enables interrupt from MON4 HI warning.
BIT 4
MON4 LO:
0 = Disables interrupt from MON4 LO warning.
1 = Enables interrupt from MON4 LO warning.
BITS 3:0 RESERVED
POWER-ON VALUE 00h
READ ACCESS N/A
WRITE ACCESS N/A
MEMORY TYPE Nonvolatile (SEE)
These registers are reserved.
Table 01h, Register FEh–FFh: RESERVED
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Table 02h Register Descriptions
Table 02h, Register 80h: MODE
POWER-ON VALUE 3Fh
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RTBL246)
MEMORY TYPE Volatile
80h SEEB RESERVED DAC1 EN DAC2 EN AEN MOD EN APC EN BIAS EN
BIT 7 BIT 0
BIT 7
SEEB:
0 = (Default) Enables EEPROM writes to SEE bytes.
1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part
is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the
SEE locations again for data to be written to the EEPROM.
BIT 6 RESERVED
BIT 5
DAC1 EN:
0 = DAC1 VALUE is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the values for DAC1. The output is updated with the new
value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for DAC1 VALUE.
BIT 4
DAC2 EN:
0 = DAC2 VALUE is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the values for DAC2. The output is updated with the new
value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for DAC2 VALUE.
BIT 3
AEN:
0 = The temperature-calculated index value TINDEX is writable by users and the updates of
calculated indexes are disabled. This allows users to interactively test their modules by
controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC
registers after the next completion of a temperature conversion.
1 = (Default) The internal temperature sensor determines the value of TINDEX.
BIT 2
MOD EN:
0 = MODULATION register is writable by the user and the LUT recalls are disabled. This allows users
to interactively test their modules by writing the DAC value for modulation. The output is updated with
the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.
1 = (Default) Enables auto control of the LUT for modulation.
BIT 1
APC EN:
0 = APC DAC is writable by the user and the LUT recalls are disabled. This allows users to
interactively test their modules by writing the DAC value for APC reference. The output is updated with
the new value at the end of the write cycle through the 3-wire interface. The I2C STOP condition is the
end of the write cycle.
1 = (Default) Enables auto control of the LUT for APC reference.
BIT 0
BIAS EN:
0 = BIAS register is controlled by the user and the APC is in manual mode. The BIAS register value
is written with the use of the 3-wire interface. This allows the user to interactively test their modules
by writing the DAC value for bias.
1 = (Default) Enables auto control for the APC feedback.
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Table 02h, Register 81h: TEMPERATURE INDEX (TINDEX)
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL246 and AEN = 0)
MEMORY TYPE Volatile
81h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
Holds the calculated index based on the temperature measurement. This index is used for the address during
lookup of Tables 04h, 06h–08h. Temperature measurements below -40°C or above +102°C are clamped to 80h and
C7h, respectively. The calculation of TINDEX is as follows:
TINDEX =Temp _ Value +40°C
2°C
+80h
For the temperature-indexed LUTs, the index used during the lookup function for each table is as follows:
Table 04h (MOD) 1 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1 TINDEX0
Table 06h (APC) 1 0 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1
Table 07h (DAC1) 1 0 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1
Table 08h (DAC2) 1 0 TINDEX6 TINDEX5TINDEX4 TINDEX3 TINDEX2 TINDEX1
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS (PW2 and MOD EN = 0) or (PW1 and RWTBL246 and MOD EN = 0)
MEMORY TYPE Volatile
82h 0 0 0 0 0 0 0 28
83h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for MODULATION and recalled from Table 04h at the adjusted memory address found in
TINDEX. This register is updated at the end of the temperature conversion.
Table 02h, Register 82h–83h: MODULATION REGISTER
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Table 02h, Register 84h–85h: DAC1 VALUE
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS (PW2 and DAC1 EN = 0) or (PW1 and RWTBL246 and DAC1 EN = 0)
MEMORY TYPE Volatile
84h 0 0 0 0 0 0 0 28
85h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for DAC1 and recalled from Table 07h at the adjusted memory address found in TINDEX.
This register is updated at the end of the temperature conversion.
VDAC1 =REFIN
512
DAC1 VALUE
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS (PW2 and DAC2 EN = 0) or (PW1 and RWTBL246 and DAC2 EN = 0)
MEMORY TYPE Volatile
86h 0 0 0 0 0 0 0 28
87h 27 2
6 2
5 2
4 2
322 2
120
BIT 7 BIT 0
The digital value used for DAC2 and recalled from Table 08h at the adjusted memory address found in TINDEX. This
register is updated at the end of the temperature conversion.
VDAC2 =REFIN
512
DAC2 VALUE
Table 02h, Register 86h–87h: DAC2 VALUE
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Table 02h, Register 88h: SAMPLE RATE
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
88h SEE SEE SEE SEE SEE APC_SR2APC_SR1APC_SR0
BIT 7 BIT 0
BITS 7:3 SEE
BITS 2:0
APC_SR[2:0]: 3-bit sample rate for comparison of APC control. Defines the sample rate for comparison
of APC control.
APC_SR[2:0] SAMPLE PERIOD (tREP) (ns)
000b 800
001b 1200
010b 1600
011b 2000
100b 2800
101b 3200
110b 4400
111b 6400
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FACTORY DEFAULT 80h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
89h LOSC VCCTXF INV LOS ASEL MASK INVRSOUT RSELPIN INVTXF
BIT 7 BIT 0
BIT 7
LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 16).
0 = LOS LO alarm is used as the source.
1 = (Default) LOS input pin is used as the source.
BIT 6
VCCTXF:
0 = VCC LO Alarm is not masked on power-up. TXFOUT is high on power-on.
1 = VCC LO Alarm is masked on power-on. TXFOUT is low as soon as VCC > VPOD.
BIT 5
INV LOS: Inverts the buffered input pin LOS or LOS LO alarm to output pin LOSOUT (see Figure 16).
0 = Noninverted LOS or LOS LO alarm to LOSOUT pin.
1 = Inverted LOS or LOS LO alarm to LOSOUT pin.
BIT 4
ASEL: Address Select.
0 = Device address is A2h.
1 = Byte DEVICE ADDRESS in Table 02h, Register 8Ch is used as the device address.
BIT 3
MASK:
0 = Alarm-enable row exists at Table 01h, Registers F8h–FFh. Table 05h, Registers F8h–FFh are
empty.
1 = Alarm-enable row exists at Table 05h, Registers F8h–FFh. Table 01h, Registers F8h–FFh are
empty.
BIT 2
INVRSOUT: Allow for inversion of RSELOUT pin (see Figure 16).
0 = RSELOUT is not inverted.
1 = RSELOUT is inverted.
BIT 1
RSELPIN:
0 = Bit 6 of the RXCTRL1 register written to the MAX3945 is programmed by the user.
1 = Bit 6 of the RXCTRL1 register is determined by the RSELOUT pin polarity.
BIT 0
INVTXF: Allow for inversion of signal driven by the TXF input pin.
0 = (Default) TXF signal is not inverted.
1 = TXF signal is inverted.
Table 02h, Register 89h: CNFGA
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Table 02h, Register 8Ah: CNFGB
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
8Ah RESERVED RESERVED TXF_TXDEN RESERVED RESERVED ALATCH QTLATCH WLATCH
BIT 7 BIT 0
BITS 7:6 RESERVED
BIT 5
TXF_TXDEN:
0 = TXFOUT does not go high when TXD goes high.
1 = TXFOUT goes high when TXD goes high.
BITS 4:3 RESERVED
BIT 2
ALATCH: ADC Alarms Comparison Latch. Lower Memory, Registers 70h71h.
0 = ADC alarm flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
BIT 1
QTLATCH: Quick Trip’s Comparison Latch. Lower Memory, Registers 72h–73h.
0 = QT alarm flags reflect the status of the last comparison.
1 = QT alarm flags remain set.
BIT 0
WLATCH: ADC Warnings Comparison Latch. Lower Memory, Registers 74h–75h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
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Table 02h, Register 8Bh: CNFGC
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
8Bh XOVEREN INVMON2 TXDM34 TXDFG TXDFLT TXDIO RSSI_FC RSSI_FF
BIT 7 BIT 0
BIT 7
XOVEREN: Enables RSSI conversion to use the XOVER (Table 02h, Register 90h–91h) value during
MON3 conversions.
0 = Uses hysteresis for linear RSSI measurements.
1 = XOVER value is enabled for nonlinear RSSI measurements.
BIT 6
INVMON2:
0 = MON2 is referenced to GND.
1 = MON2 is referenced to VCC.
BIT 5
TXDM34: Enables TXD to reset alarms and warnings associated to MON3 and MON4 during a TXD
event.
0 = TXD event has no effect on the MON3 and MON4 alarms, warnings, and quick trips.
1 = MON3 and MON4 alarms, warnings, and quick trips are reset during a TXD event.
BIT 4
TXDFG: See Figure 15.
0 = FETG, an internal signal, has no effect on TXDOUT.
1 = FETG is enabled and ORed with other possible signals to create TXDOUT.
BIT 3
TXDFLT: See Figure 15.
0 = TXF pin has no effect on TXDOUT.
1 = TXF pin is enabled and ORed with other possible signals to create TXDOUT.
BIT 2
TXDIO: See Figure 15.
0 = (Default) TXD input signal is enabled and ORed with other possible signals to create TXDOUT.
1 = TXD input signal has no effect on TXDOUT.
BITS 1:0
RSSI_FC and RSSI_FF: RSSI Force Coarse and RSSI Force Fine. Control bits for RSSI mode of
operation on the MON3 conversion.
00b = Normal RSSI mode of operation (default).
01b = The fine settings of scale and offset are used for MON3 conversions.
10b = The coarse settings of scale and offset are used for MON3 conversions.
11b = Normal RSSI mode of operation.
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Table 02h, Register 8Dh: RESERVED
FACTORY DEFAULT 00h
READ ACCESS N/A
WRITE ACCESS N/A
MEMORY TYPE Nonvolatile (SEE)
This register is reserved.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
8Eh RESERVED MON12MON11MON10RESERVED MON22MON21MON20
BIT 7 BIT 0
Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the
measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted
to the correct LSB.
Table 02h, Register 8Eh: RIGHT-SHIFT1(RSHIFT1)
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
8Ch 2726 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
This value becomes the I2C slave address for the main memory when the ASEL (Table 02h, Register 89h) bit is
set. If A0h is programmed to this register, the auxiliary memory is disabled.
Table 02h, Register 8Ch: DEVICE ADDRESS
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FACTORY DEFAULT 30h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
8Fh RESERVED MON3C2MON3C1MON3C0RESERVED MON3F2MON3F1MON3F0
BIT 7 BIT 0
Allows for right-shifting the final answer of MON3 coarse (MON3C) and MON3 fine (MON3F) voltage measurements.
This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result
so the reading is weighted to the correct LSB.
Table 02h, Register 8Fh: RIGHT-SHIFT0(RSHIFT0)
Table 02h, Register 90h–91h: XOVER COARSE
FACTORY DEFAULT 0000h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
90h 215 214 213 212 211 210 2928
91h 272625242322210
BIT 7 BIT 0
Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to 1 (Table 02h,
Register 8Bh). MON3 coarse conversion results (before right-shifting) less than this register are clamped to the
value of this register.
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FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
These registers are reserved.
FACTORY CALIBRATED
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
92h, 94h,
96h, 98h,
9Ah, 9Ch
215 214 2
13 2
12 2
11 2
10 2
9 2
8
93h, 95h,
97h, 99h,
9Bh, 9Dh
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS
voltage of 6.5536V for VCC; 2.5V for MON1, MON2, MON4; and 0.3125V for MON3 fine.
Table 02h, Register 92h–93h: VCC SCALE
Table 02h, Register 94h–95h: MON1 SCALE
Table 02h, Register 96h–97h: MON2 SCALE
Table 02h, Register 98h–99h: MON3 FINE SCALE
Table 02h, Register 9Ah–9Bh: MON4 SCALE
Table 02h, Register 9Ch–9Dh: MON3 COARSE SCALE
Table 02h, Register 9Eh–9Fh: RESERVED
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FACTORY DEFAULT FFFFh
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS PW2 or (PW1 and RWTBL2)
MEMORY TYPE Nonvolatile (SEE)
A0h 215 214 213 212 211 210 2928
A1h 272625242322210
BIT 7 BIT 0
Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to 1 (Table 02h,
Register 8Bh). MON3 fine conversion results (before right-shifting) greater than this register require a MON3
coarse conversion.
Table 02h, Register A0h–A1h: XOVER FINE
Table 02h, Register A2h–A3h: VCC OFFSET
Table 02h, Register A4h–A5h: MON1 OFFSET
Table 02h, Register A6h–A7h: MON2 OFFSET
Table 02h, Register A8h–A9h: MON3 FINE OFFSET
Table 02h, Register AAh–ABh: MON4 OFFSET
Table 02h, Register ACh–ADh: MON3 COARSE OFFSET
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
A2h, A4h,
A6h, A8h,
AAh, ACh
S S 215 214 2
13 2
12 2
11 2
10
A3h, A5h,
A7h, A9h,
ABh, ADh
29 2
8 2
7 2
6 2
5 2
4 2
3 2
2
BIT 7 BIT 0
Allows for offset control of these voltage measurements if desired. This number is two’s complement.
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FACTORY CALIBRATED
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
AEh S 282726 2
5 2
4 2
3 2
2
AFh 21 2
0 2
-1 2
-2 2
-3 2
-4 2
-5 2
-6
BIT 7 BIT 0
Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h
before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius.
Table 02h, Register AEh–AFh: INTERNAL TEMP OFFSET
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Table 02h, Register B0h–B3h: PW1
FACTORY DEFAULT FFFF FFFFh
READ ACCESS N/A
WRITE ACCESS PW2 or (PW1 and WPW1)
MEMORY TYPE Nonvolatile (SEE)
B0h 231 230 2
29 2
28 2
27 2
26 2
25 2
24
B1h 223 2
22 2
21 2
20 2
19 2
18 2
17 2
16
B2h 215 214 2
13 2
12 2
11 2
10 2
9 2
8
B3h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the
PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without
writing the password entry. All reads of this register are 00h.
FACTORY DEFAULT FFFF FFFFh
READ ACCESS N/A
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
B4h 231 230 2
29 2
28 2
27 2
26 2
25 2
24
B5h 223 2
22 2
21 2
20 2
19 2
18 2
17 2
16
B6h 215 214 2
13 2
12 2
11 2
10 2
9 2
8
B7h 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the
PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without
writing the password entry. All reads of this register are 00h.
Table 02h, Register B4h–B7h: PW2
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Table 02h, Register B8h: LOS RANGING
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
B8h RESERVED HLOS2 HLOS1 HLOS0 RESERVED LLOS2 LLOS21 LLOS0
BIT 7 BIT 0
This register controls the full-scale range of the quick-trip monitoring for the differential inputs of MON3.
BIT 7 RESERVED (Default = 0)
BITS 6:4
HLOS[2:0]: HLOS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for high LOS
found on MON3. Default is 000b and creates an FS of 1.25V.
HLOS[2:0] % OF 1.25V FS VOLTAGE (V)
000b 100.00 1.250
001b 80.00 1.000
010b 66.67 0.833
011b 50.00 0.625
100b 40.00 0.500
101b 33.33 0.417
110b 28.57 0.357
111b 25.00 0.313
BIT 3 RESERVED (Default = 0)
BITS 2:0
LLOS[2:0]: LLOS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for low LOS
found on MON3. Default is 000b and creates an FS of 1.25V.
LLOS[2:0] % OF 1.25V FS VOLTAGE (V)
000b 100.00 1.250
001b 80.00 1.000
010b 66.67 0.833
011b 50.00 0.625
100b 40.00 0.500
101b 33.33 0.417
110b 28.57 0.357
111b 25.00 0.313
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Table 02h, Register B9h: COMP RANGING
FACTORY DEFAULT 00h
READ ACCESS PW2
WRITE ACCESS PW2
MEMORY TYPE Nonvolatile (SEE)
B9h RESERVED BIAS2 BIAS1 BIAS0 RESERVED APC2 APC1 APC0
BIT 7 BIT 0
The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS. The lower nibble of
this byte controls the full-scale range for the quick-trip monitoring of the APC reference as well as the closed-loop
monitoring of APC.
BIT 7 RESERVED (Default = 0)
BITS 6:4
BIAS[2:0]: BIAS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for BIAS found
on MON1. Default is 000b and creates an FS of 1.25V.
BIAS[2:0] % OF 1.25V FS VOLTAGE (V)
000b 100.00 1.250
001b 80.00 1.000
010b 66.67 0.833
011b 50.00 0.625
100b 40.00 0.500
101b 33.33 0.417
110b 28.57 0.357
111b 25.00 0.313
BIT 3 RESERVED (Default = 0)
BITS 2:0
APC[2:0]: APC Full-Scale Ranging. 3-bit value to select the FS comparison voltage for MON2 with
the APC. Default is 000b and creates an FS of 2.5V.
APC[2:0] % OF 2.50V FS VOLTAGE (V)
000b 100.00 2.500
001b 80.00 2.000
010b 66.67 1.667
011b 50.00 1.250
100b 40.00 1.000
101b 33.33 0.833
110b 28.57 0.714
111b 25.00 0.625
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Table 02h, Register BAh: ISTEPH
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
BAh 28 2
7 2
6 2
5 2
4 2
3 2
2 2
1
BIT 7 BIT 0
ISTEP is the initial step value used at power-on or after a TXD pulse to control the BIAS register. The particular
ISTEP used depends on the value of TINDEX and ISTEPTI (Table 02h, Register C5h). When TINDEX > ISTEPTI,
ISTEPH is used. When TINDEX < ISTEPTI, ISTEPL is used. At startup, this value plus 20 = 1 is continuously added
to the BIAS register value until the APC feedback (MON2) is greater than its threshold. At that time, a binary
search is used to complete the startup of the APC closed loop. If the resulting math operation is greater than
IBIASMAX (Table 02h, Register EEh), the result is not loaded into the BIAS register, but the binary search is
begun to complete the initial search for APC. During startup, the BIAS register steps causing a higher bias value
than IBIASMAX do not create the BIAS MAX alarm. The BIAS MAX alarm detection is enabled at the end of the
binary search.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
BBh 28 2
7 2
6 2
5 2
4 2
3 2
2 2
1
BIT 7 BIT 0
See the ISTEPH register description.
Table 02h, Register BBh: ISTEPL
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FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatile (SEE)
BCh 27 2
6 2
5 2
4 2
3 2
2 2
1 2
0
BIT 7 BIT 0
Fast-comparison DAC threshold adjust for high TXP. This value is added to the APC DAC value recalled from
Table 06h. If the sum is greater than 0xFF, 0xFF is used. Comparisons greater than VHTXP, compared against
VMON2, create a TXP HI alarm. The same ranging applied to the APC DAC should be used here.
V
HTXP
=Full Scale
255
HTXP +APC DAC
()
Table 02h, Register BCh: HTXP
Table 02h, Register BDh: LTXP
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
WRITE ACCESS PW2 or (PW1 and RWTBL246)
MEMORY TYPE Nonvolatil