IRFR6215PbF, IRFU6215PbF Datasheet by Infineon Technologies

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(ifineon D- Pak IRFRGZTSPbF G
IRFR6215PbF
IRFU6215PbF
VDSS -150V
RDS(on) 0.295
ID -13A
1 2016-5-31
Absolute Maximum Ratings
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -13
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -9.0 A
IDM Pulsed Drain Current  -44
PD @TC = 25°C Maximum Power Dissipation 110 W
Linear Derating Factor 0.71 W/°C
VGS Gate-to-Source Voltage ± 20 V
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
EAS Single Pulse Avalanche Energy  310 mJ
IAR Avalanche Current  -6.6 A
EAR Repetitive Avalanche Energy  11 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
D- Pak
IRFR6215PbF
G D S
Gate Drain Source
P-Channel
175°C Operating Temperature
Surface Mount (IRFR6215)
Straight Lead (IRFU6215)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Lead-Free
G
I- Pak
IRFU6215PbF
HEXFET® Power MOSFET
Base part number Package Type
Standard Pack
Form Quantity
IRFU6215PbF I-Pak Tube 75 IRFU6215PbF
IRFR6215PbF D-Pak
Tube 75 IRFR6215PbF
Tape and Reel Left 3000 IRFR6215TRLPbF
Orderable Part Number
S
G
D D
S
D
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per
silicon area. This benefit, combined with the fast switching speed
and ruggedized device design that HEXFET Power MOSFETs are
well known for, provides the designer with an extremely efficient device
for use in a wide variety of applications.
The D-PAK is designed for surface mounting using vapor phase,
infrared, or wave soldering techniques. The straight lead version
(IRFU series) is for through-hole mounting applications. Power
dissipation levels up to 1.5 watts are possible in typical surface
mount applications.
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 1.4
°C/W
RJA Junction-to-Ambient ( PCB Mount) ––– 50
RJA Junction-to-Ambient ––– 110
V an AV an 55 ATJ -120V,V55
IRFR/U6215PbF
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Notes:
Repetitive rating; pulse width limited by max. junction temperature. (See Fig.11)
starting TJ = 25°C, L = 14mH, RG = 25, IAS = -6.6A.(See Fig.12)
I
SD -6.6A, di/dt -620A/µs, VDD V(BR)DSS, TJ 175°C
Pulse width 300µs; duty cycle 2%.
This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact.
Uses IRF6215 data and test conditions.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994.
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -150 ––– ––– V VGS = 0V, ID = -250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– -0.20 ––– V/°C Reference to 25°C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.295  VGS = -10V, ID = -6.6A
––– ––– 0.58 VGS = -10V, ID = -6.6A TJ =150°C
VGS(th) Gate Threshold Voltage -2.0 ––– -4.0 V VDS = VGS, ID = -250µA
gfs Forward Trans conductance 3.6 ––– ––– S VDS = -50V, ID = -6.6A
IDSS Drain-to-Source Leakage Current ––– ––– -25 µA VDS = -150V, VGS = 0V
––– ––– -250 VDS = -120V,VGS = 0V,TJ =150°C
IGSS Gate-to-Source Forward Leakage ––– ––– -100 nA VGS = -20V
Gate-to-Source Reverse Leakage ––– 100 VGS = 20V
Qg Total Gate Charge ––– ––– 66
nC
ID = -6.6A
Qgs Gate-to-Source Charge ––– ––– 8.1 VDS = -120V
Qgd Gate-to-Drain Charge ––– ––– 35 VGS = -10V, See Fig. 6 and 13 
td(on) Turn-On Delay Time ––– 14 –––
ns
VDD = -75V
tr Rise Time ––– 36 ––– ID = -6.6A
td(off) Turn-Off Delay Time ––– 53 ––– RG = 6.8
tf Fall Time ––– 37 ––– RD = 12See Fig. 10 
LD Internal Drain Inductance ––– 4.5 –––
nH
Between lead
,6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package
and center of die contact
Ciss Input Capacitance ––– 860 ––– VGS = 0V
Coss Output Capacitance ––– 220 ––– pF VDS = -25V
Crss Reverse Transfer Capacitance ––– 130 ––– ƒ = 1.0MHz,See Fig. 5
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– -13
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– -44 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– -1.6 V TJ = 25°C,IS = -6.6A,VGS = 0V
trr Reverse Recovery Time ––– 160 240 ns TJ = 25°C ,IF = -6.6A
Qrr Reverse Recovery Charge ––– 1.2 1.7 C di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
(Imneon, an
IRFR/U6215PbF
3 2016-5-31
Fig. 2 Typical Output Characteristics
Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance
vs. Temperature
Fig. 1 Typical Output Characteristics
1
10
100
110100
D
DS
20µs PULSE WIDTH
T = 25°C
c
A
-I , Drain-to-Source Current (A)
-V , Drain-to-Source Voltage (V)
VGS
TOP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
-4.5V
1
10
100
110100
D
DS
A
-I , Drain-to-Source Current (A)
-V , Drain-to-Source Voltage (V)
VGS
TOP - 15V
- 10V
- 8.0V
- 7.0V
- 6.0V
- 5.5V
- 5.0V
BOTTOM - 4.5V
-4.5V
20µs PULSE WIDTH
T = 175°C
C
1
10
100
45678910
T = 25°C
J
GS
D
A
-I , Drain-to-Source Current (A)
-V , Gate-to-Source Voltage (V)
T = 175°C
J
V = -50V
20µs PULSE WIDTH
DS
0.0
0.5
1.0
1.5
2.0
2.5
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Temperature (°C)
R , Drain-to-Source On Resistance
DS(on)
(Normalized)
A
V = -10V
GS
I = -11A
D
(Imneon, V V ,7 \\ v \ \‘ \ //1 \\ \ /A/ \ \ “~ // (\ZV \\ A w A / C ‘\ \ \ \\\ \
IRFR/U6215PbF
4 2016-5-31
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
0
400
800
1200
1600
2000
110100
C, Capacitance (pF)
A
DS
-V , Drain-to-Source Voltage (V)
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0
4
8
12
16
20
020406080
G
GS
A
-V , Gate-to-Source Voltage (V)
Q , Total Gate Charge (nC)
FOR TEST CIRCUIT
SEE FIGURE 13
I = -6.6A V = -120V
V = -75V
V = -30V
DDS
DS
DS
0.1
1
10
100
0.2 0.6 1.0 1.4 1.8
T = 25°C
J
V = 0V
GS
SD
SD
A
-I , Reverse Drain Current (A)
-V , Source-to-Drain Voltage (V)
T = 175°C
J
1
10
100
1 10 100 1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
10ms
-I , Drain Current (A)
-V , Drain-to-Source Voltage (V)
DS
D
10µs
100µs
1ms
T = 25°C
T = 175°C
Single Pulse
C
J
RD V“ > « “va V33 />; DUT “Ii :VDD A' ‘-10\/ =u‘se w‘dm , 1 .15 mm Factur : u 1 a
IRFR/U6215PbF
5 2016-5-31
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature
25 50 75 100 125 150 175
0
2
4
6
8
10
12
14
T , Case Temperature ( C)
-I , Drain Current (A)
°
C
D
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
t , Rectangular Pulse Duration (sec)
1
thJC
D = 0.50
0.01
0.02
0.05
0.10
0.20
SINGLE PULSE
(THERMAL RESPONSE)
A
Thermal Response (Z )
P
t
2
1
t
DM
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
12
J
DM
thJC
C
(Imneon, :NDD DRWER 15v V(BR)DSS Charge 4» // /// / Current Regu‘alor Curvem Samphng Resmors
IRFR/U6215PbF
6 2016-5-31
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 13b. Gate Charge Test Circuit
Fig 13a. Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
0
200
400
600
800
25 50 75 100 125 150 175
J
E , Single Pulse Avalanche Energy (mJ)
AS
Starting T , Junction Temperature (°C)
I
TOP -2.7A
-4.7A
BOTTOM -6.6A
D
Peak Diode Recovery dvldt Test Circuit M‘ Ctrcutt Layout Considerations 0 Low Stray Inductance 0 Ground P‘ane 0 Low Leakage Inductance Current Transformer dv/dt controHed by Re Dnver same type as D U T ‘50 control‘ed by Duty Factor "D" D.U T. - Device Under Test “ Reverse Polanty of D.U.T for P-Channel Reverse Recovery Current Re-Applred , Voltage ® Dnver Gate Dnve Pertod 4" P.W. PW Pernod ® D U.T, ISD Waveform 48L—H v D urr. vD5 Waveform Diode Recovery / dv/ot Body Diode Forward 0 v rrentd (3) @ Inductor Curent /\\§“K7‘, Rrpple s 5% \// / \/ Body Drooe “)’Forv/ard Drop k v65=1ov * VGS = 5V for Logtc Levei Devtces
IRFR/U6215PbF
7 2016-5-31
Fig 14. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
(Ianneon mm [ [II VI in Iwuwm] I THEII [I I[LIINV H n 7E7 M Ir IEI rmwzmm rwmt m: ]7 mm“ [ HIKIM Inuwuu mum 4E7 [am I T[T[[ mum ,Uzw 4m II IKUK mg I MN r v u “up ‘ I“ I mm: A: w [ I I , I PART NUMBER INTERNATIONAL RECTIFIER DATE CODE VEAR1= 2001 WEEK1S ASSEMBLV ”NE A LOT CODE IRFR’IZD IQRF‘IEA P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) www. mfmeoncom [
IRFR/U6215PbF
8 2016-5-31
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
INTERNATIONAL
ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"
OR
Note: "P" in assembly line position
EXAMPLE:
LOT CODE 1234
THIS IS AN IRFR120
WITH ASSEMBLY
indicates "Lead-Free"
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
PART NUMBER
WEEK 16
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
ASSEMBLY
3412
IRFR120
116A
LINE A
34
RECTIFIER
LOGO
IRFR120
12
ASSEMBLY
LOT CODE
YEAR 1 = 2001
DATE CODE
PART NUMBER
WEEK 16
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level
P = DESIGNATES LEAD-FREE
PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
m ‘ r\[\\7Vl[r [7L7 7‘“ 7E“ \\N[[HH[VE] iwzw E ”Ltlrbu HHHHLVHE [1E mwzuz‘ 7E[7 [4m V my“ rwtpv m ;7 V v \VN\\[\\\L[ ,mm‘ vmw 77‘“ m «m 7 ml: 7 w H mm7 77‘ 7 Vm m‘ w: \[\ ‘ ““‘ ‘ \m n: ‘ u: w 1 .H L ‘ ‘ ‘ dam-t ‘ ‘ ‘ ‘ ‘ ‘ ‘ ‘ H‘ ‘ ‘ ‘ 7 7 ‘ r ‘ 7 , ‘ LE7 7‘ [w x L ‘ um i ‘ 7 7v: x 7 7‘ 7 z ‘7 7‘ m 7 , www.infmeon.com
IRFR/U6215PbF
9 2016-5-31
I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
78
LINE A
LOGO
INTERNATIONAL
RECTIFIER
OR
PRODUCT (OPTIONAL)
P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
IRFU120
PART NUMBER
WEEK 19
DATE CODE
YEAR 1 = 2001
RECTIFIER
INTERNATIONAL
LOGO
ASSEMBLY
LOT CODE
IRFU120
56
DATE CODE
PART NUMBER
LOT CODE
ASSEMBLY
56 78
YEAR 1 = 2001
WEEK 19
119A
indicates Lead-Free"
ASSEMBLED ON WW 19, 2001
IN THE ASSEMBLY LINE "A"
Note: "P" in assembly line position
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFU120
LOT CODE 5678
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
(Imneon,
IRFR/U6215PbF
10 2016-5-31
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches)
(ifineon, Qualification lnformalion' www.mfineon.com
IRFR/U6215PbF
11 2016-5-31
Revision History
Date Comments
5/31/2016  Updated datasheet with corporate template.
 Added disclaimer on last page.
Qualification Information
Qualification Level Industrial
(per JEDEC JESD47F) ††
D-Pak MSL1
I-Pak (per JEDEC J-STD-020D) ††
RoHS Compliant Yes
Moisture Sensitivity Level
Qualification standards can be found at Infineon’swebsitewww.infineon.com
†† Applicable version of JEDEC standard at the time of product release.
TrademarksofInfineonTechnologiesAG
µHVIC™,µIPM™,µPFC™,AUConvertIR™,AURIX™,C166™,CanPAK™,CIPOS™,CIPURSE™,CoolDP™,CoolGaN™,COOLiR™,CoolMOS™,CoolSET™,CoolSiC™,
DAVE™,DIPOL™,DirectFET™,DrBlade™,EasyPIM™,EconoBRIDGE™,EconoDUAL™,EconoPACK™,EconoPIM™,EiceDRIVER™,eupec™,FCOS™,GaNpowIR™,
HEXFET™,HITFET™,HybridPACK™,iMOTION™,IRAM™,ISOFACE™,IsoPACK™,LEDrivIR™,LITIX™,MIPAQ™,ModSTACK™,myd™,NovalithIC™,OPTIGA™,
OpMOS™,ORIGA™,PowIRaudio™,PowIRStage™,PrimePACK™,PrimeSTACK™,PROFET™,PROSIL™,RASIC™,REAL3™,SmartLEWIS™,SOLIDFLASH™,
SPOC™,StrongIRFET™,SupIRBuck™,TEMPFET™,TRENCHSTOP™,TriCore™,UHVIC™,XHP™,XMC™
TrademarksupdatedNovember2015
OtherTrademarks
Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespecveowners.
Edion20160419
Publishedby
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81726Munich,Germany
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