NCV8405A,B Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
June, 2019 Rev. 8
1Publication Order Number:
NCV8405/D
NCV8405A, NCV8405B
Self-Protected Low Side
Driver with Temperature
and Current Limit
NCV8405A/B is a three terminal protected LowSide Smart
Discrete device. The protection features include overcurrent,
overtemperature, ESD and integrated DraintoGate clamping for
overvoltage protection. This device is suitable for harsh automotive
environments.
Features
ShortCircuit Protection
Thermal Shutdown with Automatic Restart
Overvoltage Protection
Integrated Clamp for Inductive Switching
ESD Protection
dV/dt Robustness
Analog Drive Capability (Logic Level Input)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ101
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
Switch a Variety of Resistive, Inductive and Capacitive Loads
Can Replace Electromechanical Relays and Discrete Circuits
Automotive / Industrial
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*Max current limit value is dependent on input
condition.
SOT223
CASE 318E
STYLE 3
MARKING
DIAGRAM
V(BR)DSS
(Clamped) RDS(ON) TYP ID MAX
42 V 90 mW @ 10 V 6.0 A*
A = Assembly Location
Y = Year
W, WW = Work Week
xxxxx = 8405A or 8405B
G or G= PbFree Package
1
(Note: Microdot may be in either location)
1
AYW
xxxxx G
G
23
4
GATE
DRAIN
SOURCE
DRAIN
23
4
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
Drain
Source
Temperature
Limit
Gate
Input
Current
Limit
Current
Sense
Overvoltage
Protection
ESD Protection
12
3
4
DPAK
CASE 369C
YWW
xxxxxG
NCV8405A, NCV8405B
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2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
DraintoSource Voltage Internally Clamped VDSS 42 V
DraintoGate Voltage Internally Clamped (RG = 1.0 MW)VDGR 42 V
GatetoSource Voltage VGS "14 V
Continuous Drain Current IDInternally Limited
Power Dissipation SOT223 Version
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
@ TS = 25°C
Power Dissipation DPAK Version
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
@ TS = 25°C
PD1.0
1.7
11.4
2.0
2.5
40
W
Thermal Resistance SOT223 Version
JunctiontoAmbient Steady State (Note 1)
JunctiontoAmbient Steady State (Note 2)
JunctiontoSoldering Point Steady State
Thermal Resistance DPAK Version
JunctiontoAmbient Steady State (Note 1)
JunctiontoAmbient Steady State (Note 2)
JunctiontoSoldering Point Steady State
RqJA
RqJA
RqJS
RqJA
RqJA
RqJS
130
72
11
60
50
3.0
°C/W
Single Pulse DraintoSource Avalanche Energy
(VDD = 40 V, VG = 5.0 V, IPK = 2.8 A, L = 80 mH, RG(ext) = 25 W, TJ = 25°C)
EAS 275 mJ
Load Dump Voltage VLD = VA + VS (VGS = 0 and 10 V, RI = 2.0 W, RL = 6.0 W, td = 400 ms) VLD 53 V
Operating Junction Temperature TJ40 to 150 °C
Storage Temperature Tstg 55 to 150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Surfacemounted onto min pad FR4 PCB, (2 oz. Cu, 0.06 thick).
2. Surfacemounted onto 2 sq. FR4 board (1 sq., 1 oz. Cu, 0.06 thick).
DRAIN
SOURCE
GATE VDS
VGS
ID
IG
+
+
Figure 1. Voltage and Current Convention
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NCV8405A, NCV8405B
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3
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter Test Condition Symbol Min Typ Max Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(Note 3)
VGS = 0 V, ID = 10 mA, TJ = 25°CV(BR)DSS 42 46 51 V
VGS = 0 V, ID = 10 mA, TJ = 150°C
(Note 5)
42 45 51
Zero Gate Voltage Drain Current VGS = 0 V, VDS = 32 V, TJ = 25°CIDSS 0.5 2.0 mA
VGS = 0 V, VDS = 32 V, TJ = 150°C
(Note 5)
2.0 10
Gate Input Current VDS = 0 V, VGS = 5.0 V IGSSF 50 100 mA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS = VDS, ID = 150 mAVGS(th) 1.0 1.6 2.0 V
Gate Threshold Temperature Coefficient VGS(th)/TJ4.0 mV/°C
Static DraintoSource OnResistance VGS = 10 V, ID = 1.4 A, TJ = 25°CRDS(on) 90 100 mW
VGS = 10 V, ID = 1.4 A, TJ = 150°C
(Note 5)
165 190
VGS = 5.0 V, ID = 1.4 A, TJ = 25°C105 120
VGS = 5.0 V, ID = 1.4 A, TJ = 150°C
(Note 5)
185 210
VGS = 5.0 V, ID = 0.5 A, TJ = 25°C105 120
VGS = 5.0 V, ID = 0.5 A, TJ = 150°C
(Note 5)
185 210
SourceDrain Forward On Voltage VGS = 0 V, IS = 7.0 A VSD 1.05 V
SWITCHING CHARACTERISTICS (Note 5)
TurnON Time (10% VIN to 90% ID)VGS = 10 V, VDD = 12 V
ID = 2.5 A, RL = 4.7 W
tON 20 ms
TurnOFF Time (90% VIN to 10% ID) tOFF 110
SlewRate ON (70% VDS to 50% VDS)VGS = 10 V, VDD = 12 V,
RL = 4.7 W
dVDS/dtON 1.0 V/ms
SlewRate OFF (50% VDS to 70% VDS) dVDS/dtOFF 0.4
SELF PROTECTION CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 4)
Current Limit VDS = 10 V, VGS = 5.0 V, TJ = 25°CILIM 6.0 9.0 11 A
VDS = 10 V, VGS = 5.0 V, TJ = 150°C
(Note 5)
3.0 5.0 8.0
VDS = 10 V, VGS = 10 V, TJ = 25°C7.0 10.5 13
VDS = 10 V, VGS = 10 V, TJ = 150°C
(Note 5)
4.0 7.5 10
Temperature Limit (Turnoff) VGS = 5.0 V (Note 5) TLIM(off) 150 180 200 °C
Thermal Hysteresis VGS = 5.0 V DTLIM(on) 15
Temperature Limit (Turnoff) VGS = 10 V (Note 5) TLIM(off) 150 165 185
Thermal Hysteresis VGS = 10 V DTLIM(on) 15
GATE INPUT CHARACTERISTICS (Note 5)
Device ON Gate Input Current VGS = 5 V ID = 1.0 A IGON 50 mA
VGS = 10 V ID = 1.0 A 400
Current Limit Gate Input Current VGS = 5 V, VDS = 10 V IGCL 0.05 mA
VGS = 10 V, VDS = 10 V 0.4
Thermal Limit Fault Gate Input Current VGS = 5 V, VDS = 10 V IGTL 0.22 mA
VGS = 10 V, VDS = 10 V 1.0
ESD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5)
ElectroStatic Discharge Capability Human Body Model (HBM) ESD 4000 V
Machine Model (MM) 400
3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.
4. Fault conditions are viewed as beyond the normal operating range of the part.
5. Not subject to production testing.
TJs‘an : 25‘0 Us.“ : 150 -40:C M 00°C H
NCV8405A, NCV8405B
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4
TYPICAL PERFORMANCE CURVES
8 V
1
10
10 100
Figure 2. Single Pulse Maximum Switchoff
Current vs. Load Inductance
L (mH)
IL(max) (A)
TJstart = 25°C
TJstart = 150°C
10
100
1000
10 10
0
Figure 3. Single Pulse Maximum Switching
Energy vs. Load Inductance
L (mH)
Emax (mJ)
TJstart = 25°C
TJstart = 150°C
1
10
100
110
Figure 4. Single Pulse Maximum Inductive
Switchoff Current vs. Time in Clamp
TIME IN CLAMP (ms)
IL(max) (A)
TJstart = 25°C
TJstart = 150°C
10
100
1000
110
Figure 5. Single Pulse Maximum Inductive
Switching Energy vs. Time in Clamp
TIME IN CLAMP (ms)
Emax (mJ)
TJstart = 25°C
TJstart = 150°C
Figure 6. Output Characteristics
VDS = 10 V
25°C
100°C
150°C
40°C
ID (A)
VGS (V)
Figure 7. Transfer Characteristics
VDS (V)
ID (A)
VGS = 2.5 V
3 V
4 V
5 V
6 V
10 V
TA = 25°C
0
2
4
6
8
10
12
14
012345
7 V
9 V
0
2
4
6
8
10
12
12345
0°C‘ VGs 150‘0‘ Ves: 10v 100°C,V :sv 100°C,V55:10V 100°C‘ID:1_4 _ _ _ ___ _ _ _ _ 25°C‘sz:5v I 0°C,I :0,5A _ 25_°cv _0V 40‘C»\0:14 -40§C| :05A 3 4 5 s 7 a 9 1 V55:5V /// // 150°C / \ // \ / \ 0°C 25%:
NCV8405A, NCV8405B
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5
TYPICAL PERFORMANCE CURVES
Figure 8. RDS(on) vs. GateSource Voltage
VGS (V)
RDS(on) (mW)
150°C, ID = 0.5 A
150°C, ID = 1.4 A
100°C, ID = 0.5 A
100°C, ID = 1.4 A
25°C, ID = 0.5 A
25°C, ID = 1.4 A
40°C, ID = 0.5 A
40°C, ID = 1.4 A
Figure 9. RDS(on) vs. Drain Current
ID (A)
RDS(on) (mW)
VGS = 5 V
VGS = 10 V
ID = 1.4 A
Figure 10. Normalized RDS(on) vs. Temperature
T (°C)
RDS(on) (VGS = 5 V, TJ = 25°C)(NORMALIZED)
25°C
100°C
150°C
40°C
Figure 11. Current Limit vs. GateSource
Voltage
VGS (V)
ILIM (A)
VDS = 10 V
Figure 12. Current Limit vs. Junction
Temperature
TJ (°C)
ILIM (A)
VDS = 10 V
VGS = 5 V
VGS = 10 V
Figure 13. DraintoSource Leakage Current
VDS (V)
IDSS (mA)
VGS = 0 V
25°C
100°C
150°C
40°C
50
100
150
200
250
300
345678910
50
70
90
110
130
150
170
190
210
40°C, VGS = 5 V
40°C, VGS = 10 V
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
25°C, VGS = 5 V
25°C, VGS = 10 V
100°C, VGS = 5 V
100°C, VGS = 10 V
150°C, VGS = 10 V
150°C, VGS = 10 V
0.5
0.75
1.0
1.25
1.5
1.75
2.0
40 20 0 20 40 60 80 100 120 140
3
5
7
9
11
13
15
567891
0
4
6
8
10
12
14
40 20 0 20 40 60 80 100 120 140 160
0.001
0.01
0.1
1
10
10 15 20 25 30 35 40
7 : /// \\ /;00/ 25%: /// \ ///100°C ‘//// \ : / / 150°C S/d((un
NCV8405A, NCV8405B
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6
TYPICAL PERFORMANCE CURVES
DRAINSOURCE VOLTAGE SLOPE (V/ms)
0.6
0.7
0.8
0.9
1
1.1
1.2
40 20 0 20 40 60 80 100 120 140
Figure 14. Normalized Threshold Voltage vs.
Temperature
T (°C)
NORMALIZED VGS(th) (V)
ID = 150 mA
VGS = VDS
Figure 15. BodyDiode Forward
Characteristics
IS (A)
VSD (V)
25°C
100°C
150°C
40°C
VGS = 0 V
td(off)
td(on)
tf
tr
Figure 16. Resistive Load Switching Time vs.
GateSource Voltage
VGS (V)
TIME (ms)
ID = 2.5 A
VDD = 12 V
RG = 0 W
Figure 17. Resistive Load Switching
DrainSource Voltage Slope vs. GateSource
Voltage
VGS (V)
DRAINSOURCE VOLTAGE SLOPE (V/ms)
ID = 2.5 A
VDD = 12 V
RG = 0 W
dVDS/dt(on)
dVDS/dt(off)
TIME (ms)
Figure 18. Resistive Load Switching Time vs.
Gate Resistance
RG (W)
tf, (VGS = 10 V)
tf, (VGS = 5 V)
td(off), (VGS = 10 V)
tr, (VGS = 5 V)
td(off), (VGS = 5 V)
tr, (VGS = 10 V) td(on), (VGS = 5 V)
td(on), (VGS = 10 V)
ID = 2.5 A
VDD = 12 V
dVDS/dt(off), VGS = 5 V
dVDS/dt(on), VGS = 10 V
dVDS/dt(on), VGS = 5 V
dVDS/dt(off), VGS = 10 V
Figure 19. DrainSource Voltage Slope during
Turn On and Turn Off vs. Gate Resistance
RG (W)
ID = 2.5 A
VDD = 12 V
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1234567891
0
0
50
100
150
200
345678910
0.000
0.500
1.000
1.500
345678910
0
25
50
75
100
125
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
0 500 1000 1500 20
0
NCV8405A, NCV8405B
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7
TYPICAL PERFORMANCE CURVES
0.01
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Single Pulse
50% Duty Cycle
20%
10%
5%
2%
1%
PULSE WIDTH (sec)
RqJA 1” SQ 1 Oz COPPER
Figure 20. Transient Thermal Resistance
0
20
40
60
80
100
120
140
0 100 200 300 400 500 600 700
COPPER HEAT SPREADER AREA (mm2)
qJA (°C/W)
Figure 21. qJA vs. Copper
qJA Curve with PCB cu thk 1.0 oz
qJA Curve with PCB cu thk 2.0 oz
TA 25°C
RL VIN Figure 22. Resistive Load Switching Test Circuit VIN IDS Figure 23. Resistive Load Switching Waveforms www.cnsemi.com a
NCV8405A, NCV8405B
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8
TEST CIRCUITS AND WAVEFORMS
DUT
G
D
S
RL
VDD
IDS
VIN
Figure 22. Resistive Load Switching Test Circuit
RG
+
Figure 23. Resistive Load Switching Waveforms
tON
VIN
IDS
tOFF
10%
10%
90%
90%
G DUT VDD E —o IDS Figure 24. Inductive Load Switching Tesl Circuit www.cnsemi.com s
NCV8405A, NCV8405B
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9
TEST CIRCUITS AND WAVEFORMS
VDD
IDS
VIN
L
VDS
tp
Figure 24. Inductive Load Switching Test Circuit
DUT
G
D
S
RG +
0 V
5 V
Tav
VIN
IDS
VDS
Tp
VDS(on)
Ipk
0
VDD
V(BR)DSS
Figure 25. Inductive Load Switching Waveforms
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NCV8405A, NCV8405B
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10
ORDERING INFORMATION
Device Package Shipping
NCV8405ASTT1G SOT223
(PbFree)
1000 / Tape & Reel
NCV8405ASTT3G SOT223
(PbFree)
4000 / Tape & Reel
NCV8405ADTRKG DPAK
(PbFree)
2500 / Tape & Reel
NCV8405BDTRKG DPAK
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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SOT223 (TO261)
CASE 318E04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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DOCUMENT NUMBER:
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PAGE 1 OF 2
SOT223 (TO261)
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
L||_||_| ON Semxcunduclm and are hademavks av Semxcanduclur Campunenls lnduslnes. uc dha ON Samanaucxar ar us suhsxdxanes m xna Umled sxaxas andJm mhev cmm‘nes ON Semxcunduclar vesewes me “gm to make changes wuhum mnna. mouse to any pruduns necem ON Semanduc‘m makes nu wanamy. represenlalmn m guarantee regardmg ma sumahmly at W; manual: can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy snsmg mm xna aapncauan m use M any pmduclnv mum and specmcsl‘y dwsc‘axms any and an Mammy mc‘udmg wxlham hmma‘mn spema‘ cansequemm m \nmdeula‘ damages ON Semxmnduclar dues nn| away any hcense under Ms pa|EM nghls Ivar xna ngms av n|hers
SOT223 (TO261)
CASE 318E04
ISSUE R
DATE 02 OCT 2018
STYLE 4:
PIN 1. SOURCE
2. DRAIN
3. GATE
4. DRAIN
STYLE 6:
PIN 1. RETURN
2. INPUT
3. OUTPUT
4. INPUT
STYLE 8:
CANCELLED
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 7:
PIN 1. ANODE 1
2. CATHODE
3. ANODE 2
4. CATHODE
STYLE 3:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 2:
PIN 1. ANODE
2. CATHODE
3. NC
4. CATHODE
STYLE 9:
PIN 1. INPUT
2. GROUND
3. LOGIC
4. GROUND
STYLE 5:
PIN 1. DRAIN
2. GATE
3. SOURCE
4. GATE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
1
A = Assembly Location
Y = Year
W = Work Week
XXXXX = Specific Device Code
G= PbFree Package
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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DOCUMENT NUMBER:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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SOT223 (TO261)
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DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F DATE 21 JUL 2015
SCALE 1:1
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
123
4
STYLE 8:
PIN 1. N/C
2. CATHODE
3. ANODE
4. CATHODE
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. RESISTOR ADJUST
4. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. ANODE
b
D
E
b3
L3
L4b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 0.040 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 3.93
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
XXXXXX = Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
AYWW
XXX
XXXXXG
XXXXXXG
ALYWW
DiscreteIC
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
eBOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON10527D
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
DPAK SINGLE GAUGE SURFACE MOUNT
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
0N Semlconduclol“ m Semicnnduclor and J
DOCUMENT NUMBER:
98AON10527D
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION. REQ. BY L. GAN 24 SEP 2001
AADDED STYLE 8. REQ. BY S. ALLEN. 06 AUG 2008
BADDED STYLE 9. REQ. BY D. WARNER. 16 JAN 2009
CADDED STYLE 10. REQ. BY S. ALLEN. 09 JUN 2009
DRELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE. 29 JUN 2010
EADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-
BALIZA.
06 FEB 2014
FADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA. 21 JUL 2015
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. F Case Outline Number
:
369C
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