SST25VF016B Datasheet by Microchip Technology

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6‘ ‘MICROCHIP SST25VF01 6 B
2015 Microchip Technology Inc. DS20005044C-page 1
Features
Single Voltage Read and Write Operations
- 2.7-3.6V
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
High Speed Clock Frequency
- Up to 50 MHz
Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
Low Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5 µA (typical)
Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
Fast Erase and Byte-Program:
- Chip-Erase Time: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7 µs (typical)
Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
End-of-Write Detection
- Software polling the BUSY bit in Status Register
- Busy Status readout on SO pin in AAI Mode
Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
Software Write Protection
- Write protection through Block-Protection bits in
status register
Temperature Range
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
Packages Available
- 8-lead SOIC (200 mils)
- 8-contact WSON (6mm x 5mm)
All devices are RoHS compliant
Product Description
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25VF016B
devices are enhanced with improved operating fre-
quency and even lower power consumption than the
original SST25VFxxxA devices. SST25VF016B SPI
serial flash memories are manufactured with propri-
etary, high-performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
SST25VF016B devices significantly improve perfor-
mance and reliability, while lowering power consump-
tion. The devices write (Program or Erase) with a single
power supply of 2.7-3.6V for SST25VF016B. The total
energy consumed is a function of the applied voltage,
current, and time of application. Since for any given
voltage range, the SuperFlash technology uses less
current to program and has a shorter erase time, the
total energy consumed during any Erase or Program
operation is less than alternative flash memory technol-
ogies.
The SST25VF016B device is offered in both 8-lead
SOIC (200 mils) and 8-contact WSON (6mm x 5mm)
packages. See Figure 2-1 for pin assignments.
SST25VF016B
16 Mbit SPI Serial Flash
SST25VF016B
DS20005044C-page 2 2015 Microchip Technology Inc.
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2015 Microchip Technology Inc. DS20005044C-page 3
SST25VF016B
1.0 BLOCK DIAGRAM
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
1271 B1.0
I/O Buffers
and
Data Latches
SuperFlash
Memory
X - Decoder
Control Logic
Address
Buffers
and
Latches
CE#
Y - Decoder
SCK SI SO WP# HOLD#
Serial Interface
jjjj CECE
SST25VF016B
DS20005044C-page 4 2015 Microchip Technology Inc.
2.0 PIN DESCRIPTION
FIGURE 2-1: PIN ASSIGNMENTS
TABLE 2-1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See “Hardware End-of-Write Detection” on page 11 for details.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the
device.
VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF016B
VSS Ground
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1271 08-soic S2A P1.0
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
Top View
VDD
HOLD#
SCK
SI
1271 08-wson QA P2.0
8-Lead SOIC 8-Contact WSON
XX X XX) XXX XXXXX)— —<:x:x:x:x:><:x:x:>—
2015 Microchip Technology Inc. DS20005044C-page 5
SST25VF016B
3.0 MEMORY ORGANIZATION
The SST25VF016B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with
32 KByte overlay blocks and 64 KByte overlay eras-
able blocks.
4.0 DEVICE OPERATION
The SST25VF016B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25VF016B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
FIGURE 4-1: SPI PROTOCOL
4.1 Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be
driven active low. See Figure 5-3 for Hold timing.
FIGURE 4-2: HOLD CONDITION WAVEFORM
4.2 Write Protection
SST25VF016B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP3, BP2, BP1, BP0, and BPL) in the status
register provide Write protection to the memory array
and the status register. See Table 4-3 for the Block-Pro-
tection description.
1271 SPIprot.0
MODE 3
SCK
SI
SO
CE#
MODE 3
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MODE 0MODE 0
HIGH IMPEDANCE
MSB
MSB
Active Hold Active Hold Active
1271 HoldCond.0
SCK
HOLD#
SST25VF016B
DS20005044C-page 6 2015 Microchip Technology Inc.
4.2.1 WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
4.3 Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
4.3.1 BUSY
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
4.3.2 WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch (WEL) bit indicates the status
of the internal memory Write Enable Latch. If the Write-
Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:
•Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instructions
4.3.3 AUTO ADDRESS INCREMENT (AAI)
The Auto Address Increment Programming-Status bit
provides status on whether the device is in Auto
Address Increment (AAI) programming mode or Byte-
Program mode. The default at power up is Byte-Pro-
gram mode.
TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP# BPL Execute WRSR Instruction
L1Not Allowed
L0Allowed
HXAllowed
TABLE 4-2: SOFTWARE STATUS REGISTER
Bit Name Function
Default at
Power-up Read/Write
0BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0R
1WEL 1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0R
2BP0 Indicate current level of block write protection (See Table 4-3)1R/W
3BP1 Indicate current level of block write protection (See Table 4-3)1R/W
4BP2 Indicate current level of block write protection (See Table 4-3)1R/W
5BP3 Indicate current level of block write protection (See Table 4-3)0R/W
6AAI Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0R
7BPL 1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable
0R/W
2015 Microchip Technology Inc. DS20005044C-page 7
SST25VF016B
4.3.4 BLOCK PROTECTION (BP3,BP2,
BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define
the size of the memory area, as defined in Table 4-3, to
be software protected against any memory Write (Pro-
gram or Erase) operation. The Write-Status-Register
(WRSR) instruction is used to program the BP3, BP2,
BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-
up, BP3, BP2, BP1 and BP0 are set to 1.
4.3.5 BLOCK PROTECTION LOCK-DOWN
(BPL)
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents
any further alteration of the BPL, BP3, BP2, BP1, and
BP0 bits. When the WP# pin is driven high (VIH), the
BPL bit has no effect and its value is “Don’t Care”. After
power-up, the BPL bit is reset to 0.
TABLE 4-3: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF016B1
1. X = Don’t Care (RESERVED) default is “0
Protection Level
Status Register Bit2
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
Protected Memory Address
BP3 BP2 BP1 BP0 16 Mbit
None X 0 0 0 None
Upper 1/32 X 0 0 1 1F0000H-1FFFFFH
Upper 1/16 X 0 1 0 1E0000H-1FFFFFH
Upper 1/8X 0 1 1 1C0000H-1FFFFFH
Upper 1/4 X 1 0 0 180000H-1FFFFFH
Upper 1/2 X 1 0 1 100000H-1FFFFFH
All Blocks X 1 1 0 000000H-1FFFFFH
All Blocks X 1 1 1 000000H-1FFFFFH
SST25VF016B
DS20005044C-page 8 2015 Microchip Technology Inc.
4.4 Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25VF016B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-4. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-4: DEVICE OPERATION INSTRUCTIONS
Instruction Description Op Code Cycle1
1. One bus cycle is eight clock periods.
Address
Cycle(s)2
2. Address bits above the most significant bit of each density can be VIL or VIH.
Dummy
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
Read Read Memory at 25 MHz 0000 0011b (03H) 301 to 25 MHz
High-Speed
Read Read Memory at 50 MHz 0000 1011b (0BH) 311 to 50 MHz
4 KByte Sector-
Erase3
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 4 KByte of
memory array 0010 0000b (20H) 30050 MHz
32 KByte Block-
Erase4
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 32 KByte block
of memory array 0101 0010b (52H) 30050 MHz
64 KByte Block-
Erase5
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
Erase 64 KByte block
of memory array 1101 1000b (D8H) 30050 MHz
Chip-Erase Erase Full Memory Array 0110 0000b (60H) or
1100 0111b (C7H)
00050 MHz
Byte-Program To Program One Data Byte 0000 0010b (02H) 30150 MHz
AAI-Word-Pro-
gram6
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be pro-
grammed into the initial address [A23-A1] with A0=1.
Auto Address Increment
Programming 1010 1101b (ADH) 302 to 50 MHz
RDSR7
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
Read-Status-Register 0000 0101b (05H) 001 to 50 MHz
EWSR Enable-Write-Status-Register 0101b 0000b (50H) 00050 MHz
WRSR Write-Status-Register 0000 0001b (01H) 00150 MHz
WREN Write-Enable 0000 0110b (06H) 00050 MHz
WRDI Write-Disable 0000 0100b (04H) 00050 MHz
RDID8
8.Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
Read-ID 1001 0000b (90H) or
1010 1011b (ABH)
301 to 50 MHz
JEDEC-ID JEDEC ID read 1001 1111b (9FH) 003 to 50 MHz
EBSY Enable SO to output RY/BY#
status during AAI program-
ming
0111 0000b (70H) 00050 MHz
DBSY Disable SO as RY/BY#
status during AAI program-
ming
1000 0000b (80H) 00050 MHz
,flflWfl H,Ih H,Ih HWJUW XX XXX XXX XX XXXXX mmwwfinfl mmflfifl XXXX X X X X XXXX XX XXX XX XXXX H‘GH \MPEDANCE
2015 Microchip Technology Inc. DS20005044C-page 9
SST25VF016B
4.4.1 READ (25 MHZ)
The Read instruction, 03H, supports up to 25 MHz
Read. The device outputs the data starting from the
specified address location. The data output stream is
continuous through all addresses until terminated by a
low to high transition on CE#. The internal address
pointer will automatically increment until the highest
memory address is reached. Once the highest memory
address is reached, the address pointer will automati-
cally increment to the beginning (wrap-around) of the
address space. Once the data from address location
1FFFFFH has been read, the next output will be from
address location 000000H.
The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A23-A0]. CE#
must remain active low for the duration of the Read
cycle. See Figure 4-3 for the Read sequence.
FIGURE 4-3: READ SEQUENCE
4.4.2 HIGH-SPEED-READ (50 MHZ)
The High-Speed-Read instruction supporting up to 50
MHz Read is initiated by executing an 8-bit command,
0BH, followed by address bits [A23-A0] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 4-4 for the High-
Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location 1FFFFFH
has been read, the next output will be from address
location 000000H.
FIGURE 4-4: HIGH-SPEED-READ SEQUENCE
1271 ReadSeq.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.
03
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 7047 48 55 56 63 64
N+2 N+3 N+4N N+1
DOUT
MSB MSB
MSB
MODE 0
MODE 3
DOUT DOUT DOUT DOUT
1271 HSRdSeq.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD.0B
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 4855 56 63 64
N+2 N+3 N+4
NN+1
X
MSB
MSB
MSB
MODE 0
MODE 3
DOUT DOUT DOUT DOUT
80
71 72
DOUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V
IL
or V
IH
)
X XXXXX
SST25VF016B
DS20005044C-page 10 2015 Microchip Technology Inc.
4.4.3 BYTE-PROGRAM
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Pro-
gram operation. A Byte-Program instruction applied to a
protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.
The Byte-Program instruction is initiated by executing
an 8-bit command, 02H, followed by address bits [A23-
A0]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait
TBP for the completion of the internal self-timed Byte-
Program operation. See Figure 4-5 for the Byte-Pro-
gram sequence.
FIGURE 4-5: BYTE-PROGRAM SEQUENCE
4.4.4 AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM
The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word pro-
gram instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Program-
ming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the com-
pletion of each AAI Word program cycle: hardware
detection by reading the Serial Output, software detec-
tion by polling the BUSY bit in the software status reg-
ister, or wait TBP. Refer to“End-of-Write Detection” for
details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data are input sequentially,
each one from MSB (Bit 7) to LSB (Bit 0). The first byte
of data (D0) is programmed into the initial address [A23-
A1] with A0=0, the second byte of Data (D1) is pro-
grammed into the initial address [A23-A1] with A0=1.
CE# must be driven high before executing the AAI
Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, fol-
lowed by the next two, and so on.
When programming the last desired word, or the high-
est unprotected memory address, check the busy sta-
tus using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Dis-
able (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figures 4-8 and 4-9
for the AAI Word programming sequence.
4.4.5 END-OF-WRITE DETECTION
There are three methods to determine completion of a
program cycle during AAI Word programming: hard-
ware detection by reading the Serial Output, software
detection by polling the BUSY bit in the Software Status
Register, or wait TBP. The Hardware End-of-Write
detection method is described in the section below.
1271 ByteProg.0
CE#
SO
SI
SCK
ADD.
012345678
ADD. ADD. DIN
02
HIGH IMPEDANCE
15 16 23 24 31 32 39
MODE 0
MODE 3
MSBMSB
MSB LSB
2015 Microchip Technology Inc. DS20005044C-page 11
SST25VF016B
4.4.6 HARDWARE END-OF-WRITE
DETECTION
The Hardware End-of-Write detection method elimi-
nates the overhead of polling the Busy bit in the Soft-
ware Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see Figure 4-6) The 8-
bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first exe-
cute WRDI instruction, 04H, to reset the Write-Enable-
Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
FIGURE 4-6: ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
FIGURE 4-7: DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
SO
SI
SCK
01234567
70
HIGH IMPEDANCE
MODE 0
MODE 3
1271 EnableSO.0
MSB
CE#
SO
SI
SCK
01234567
80
HIGH IMPEDANCE
MODE 0
MODE 3
1271 DisableSO.0
MSB
!_I !_I I'Lfl FLIS WWXXWWDCXWS LII LILS \ / Sl—l'LfL.._I_\_I_\_ S_fl_J'|_|'l_J'|_|'LJ'L___J'l__J'L___fl__J'L___fl__J'|_|'l_J'L SDQDW— sfixfl—D ,, /i\ , F ‘I F ‘I T‘LWL 5 JMMMMMRHMMHHMMRHHHMR XXXXXWWW
SST25VF016B
DS20005044C-page 12 2015 Microchip Technology Inc.
FIGURE 4-8: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
FIGURE 4-9: AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
SOFTWARE END-OF-WRITE DETECTION
CE#
SI
SCK
SO
1271 AAI.HW.3
Check for Flash Busy Status to load next valid
1
command
Load AAI command, Address, 2 bytes data
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
0
AAA
AD D0 AD
MODE 3
MODE 0
D1 D2 D3
7
WREN
EBSY
07078 32 4715 16 23 24 31 04039 7 8 15 16 23
D
OUT
WRDI followed by DBSY
to exit AAI Mode
WRDI RDSR
7015780
DBSY
70
CE# cont.
SI cont.
SCK cont.
SO cont.
Last 2
Data Bytes
AD
D
n-1 Dn
7 8 15 16 230
Check for Flash Busy Status to load next valid
1
command
07832 4715 16 23 24 31 04039 7 815 16 23 7 815 16 23 70 157800
CE#
SI
SCK
SO DOUT
MODE 3
MODE 0
1271 AAI.SW.1
Note: 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command
Wait TBP or poll Software Status
register to load next valid1 command
Last 2
Data Bytes
WRDI to exit
AAI Mode
Load AAI command, Address, 2 bytes data
AAAAD D0 ADD1 D2 D3 AD Dn-1 Dn
WRDI
RDSR
2015 Microchip Technology Inc. DS20005044C-page 13
SST25VF016B
4.4.7 4-KBYTE SECTOR-ERASE
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address
bits [A23-A0]. Address bits [AMS-A12] (AMS =Most Sig-
nificant address) are used to determine the sector
address (SAX), remaining address bits can be VIL or VIH.
CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software
status register or wait TSE for the completion of the
internal self-timed Sector-Erase cycle. See Figure 4-10
for the Sector-Erase sequence.
FIGURE 4-10: SECTOR-ERASE SEQUENCE
4.4.8 32-KBYTE AND 64-KBYTE BLOCK-
ERASE
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain
active low for the duration of any command sequence.
The 32-Kbyte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Sig-
nificant Address) are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE#
must be driven high before the instruction is executed. The
64-Kbyte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A23-A0].
Address bits [AMS-A15] are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
FIGURE 4-11: 32-KBYTE BLOCK-ERASE SEQUENCE
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
52
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1271 32KBklEr.0
MSB MSB
SST25VF016B
DS20005044C-page 14 2015 Microchip Technology Inc.
FIGURE 4-12: 64-KBYTE BLOCK-ERASE SEQUENCE
4.4.9 CHIP-ERASE
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction will be ignored if any
of the memory area is protected. Prior to any Write oper-
ation, the Write-Enable (WREN) instruction must be exe-
cuted. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase
instruction is initiated by executing an 8-bit command,
60H or C7H. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait TCE for the completion of the
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.
FIGURE 4-13: CHIP-ERASE SEQUENCE
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16 23 24 31
MODE 0
MODE 3
1271 63KBlkEr.0
MSB MSB
CE#
SO
SI
SCK
01234567
60 or C7
HIGH IMPEDANCE
MODE 0
MODE 3
1271 ChEr.0
MSB
XX XXXX X XXXX X X XXX
2015 Microchip Technology Inc. DS20005044C-page 15
SST25VF016B
4.4.10 READ-STATUS-REGISTER (RDSR)
The Read-Status-Register (RDSR) instruction allows
reading of the status register. The status register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog-
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is termi-
nated by a low to high transition of the CE#. See Figure
4-14 for the RDSR instruction sequence.
FIGURE 4-14: READ-STATUS-REGISTER (RDSR) SEQUENCE
4.4.11 WRITE-ENABLE (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed prior to any Write (Program/Erase) opera-
tion. The WREN instruction may also be used to allow
execution of the Write-Status-Register (WRSR) instruc-
tion; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.
FIGURE 4-15: WRITE ENABLE (WREN) SEQUENCE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
1271 RDSRseq.0
MODE 3
SCK
SI
SO
CE#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05
MODE 0
HIGH IMPEDANCE
Status
Register Out
MSB
MSB
CE#
SO
SI
SCK
01234567
06
HIGH IMPEDANCE
MODE 0
MODE 3
1271 WREN.0
MSB
XXXXX XXXXXXXXXXXX )OOOOOOOO—
SST25VF016B
DS20005044C-page 16 2015 Microchip Technology Inc.
4.4.12 WRITE-DISABLE (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. The WRDI instruction will not
terminate any programming operation in progress. Any
program operation in progress may continue up to TBP
after executing the WRDI instruction. CE# must be driven
high before the WRDI instruction is executed.
FIGURE 4-16: WRITE DISABLE (WRDI) SEQUENCE
4.4.13 ENABLE-WRITE-STATUS-
REGISTER (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction
and opens the status register for alteration. The Write-
Status-Register instruction must be executed immedi-
ately after the execution of the Enable-Write-Status-
Register instruction. This two-step instruction
sequence of the EWSR instruction followed by the
WRSR instruction works like SDP (software data pro-
tection) command structure which prevents any acci-
dental alteration of the status register values. CE# must
be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction
is executed.
4.4.14 WRITE-STATUS-REGISTER (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP3, BP2, BP1, BP0, and BPL bits of the sta-
tus register. CE# must be driven low before the
command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. See Figure 4-17 for EWSR or WREN and
WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is low, the BPL bit can only be set from
“0” to “1” to lock-down the status register, but cannot be
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
and BP1 and BP2 bits in the status register can all be
changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to “1” to lock down the status register as
well as altering the BP0, BP1, and BP2 bits at the same
time. See Table 4-1 for a summary description of WP#
and BPL functions.
FIGURE 4-17: ENABLE-WRITE-STATUS-REGISTER (EWSR) OR
WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
CE#
SO
SI
SCK
01234567
04
HIGH IMPEDANCE
MODE 0
MODE 3
1271 WRDI.0
MSB
1271 EWSR.0
MODE 3
HIGH IMPEDANCE
MODE 0
STATUS
REGISTER IN
76543210
MSBMSBMSB
01
MODE 3
SCK
SI
SO
CE#
MODE 0
50 or 06
01234567 0123456789 101112131415
QLLLflflflflflflflflflflflflflflflflflflflflflflflflflflflflflflflflflflfl XXXXX XXXXXXXX XXXXXXXX XXXXXXX XXXX 44444444444%::::::::X:::::::}::::::::%447
2015 Microchip Technology Inc. DS20005044C-page 17
SST25VF016B
4.4.15 JEDEC READ-ID
The JEDEC Read-ID instruction identifies the device as
SST25VF016B and the manufacturer as Microchip.
The device information can be read from executing the
8-bit command, 9FH. Following the JEDEC Read-ID
instruction, the 8-bit manufacturer’s ID, BFH, is output
from the device. After that, a 16-bit device ID is shifted
out on the SO pin. Byte 1, BFH, identifies the manufac-
turer as Microchip. Byte 2, 25H, identifies the memory
type as SPI Serial Flash. Byte 3, 41H, identifies the
device as SST25VF016B. The instruction sequence is
shown in Figure 4-18. The JEDEC Read ID instruction
is terminated by a low to high transition on CE# at any
time during data output. If no other command is issued
after executing the JEDEC Read-ID instruction, issue a
00H (NOP) command before going into Standby Mode
(CE#=VIH).
FIGURE 4-18: JEDEC READ-ID SEQUENCE
TABLE 4-5: JEDEC READ-ID DATA
Manufacturer’s ID
Device ID
Memory Type Memory Capacity
Byte1 Byte 2 Byte 3
BFH 25H 41H
25 41
1271 JEDECID.1
CE#
SO
SI
SCK
012345678
HIGH IMPEDANCE
15 1614 28 29 30 31
BF
MODE 3
MODE 0
MSBMSB
9 10111213 1718 32 34
9F
19 20 21 22 23 3324 25 26 27
fl,fl fl,fl fl, XXX XXX XXXXXXXXX
SST25VF016B
DS20005044C-page 18 2015 Microchip Technology Inc.
4.4.16 READ-ID (RDID)
The Read-ID instruction (RDID) identifies the devices
as SST25VF016B and manufacturer as Microchip. This
command is backward compatible to all SST25xFxxxA
devices and should be used as default device identifi-
cation when multiple versions of SPI Serial Flash
devices are used in a design. The device information
can be read from executing an 8-bit command, 90H or
ABH, followed by address bits [A23-A0]. Following the
Read-ID instruction, the manufacturer’s ID is located in
address 00000H and the device ID is located in
address 00001H. Once the device is in Read-ID mode,
the manufacturer’s and device ID output data toggles
between address 00000H and 00001H until terminated
by a low to high transition on CE#.
Refer to Tables 4-5 and 4-6 for device identification
data.
FIGURE 4-19: READ-ID SEQUENCE
TABLE 4-6: PRODUCT IDENTIFICATION
Address Data
Manufacturer’s ID 00000H BFH
Device ID
SST25VF016B 00001H 41H
1271 RdID.0
CE#
SO
SI
SCK
00
012345678
00 ADD1
90 or AB
HIGH IMPEDANCE
15 16 23 24 31 32 39 40 47 48 55 56 63
BF Device ID BF Device ID
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
Device ID = 41H for SST25VF016B
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
HIGH
IMPEDANCE
MODE 3
MODE 0
MSB MSB
MSB
2015 Microchip Technology Inc. DS20005044C-page 19
SST25VF016B
5.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Te m p e r a ture Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Tem pe ra ture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
TABLE 5-1: OPERATING RANGE
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
TABLE 5-2: AC CONDITIONS OF TEST1
1. See Figures 5-5 and 5-6
Input Rise/Fall Time Output Load
5ns CL = 30 pF
TABLE 5-3: DC OPERATING CHARACTERISTICS
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDDR Read Current 10 mA CE#=0.1 VDD/0.9 VDD@25 MHz, SO=open
IDDR2 Read Current 15 mA CE#=0.1 VDD/0.9 VDD@50 MHz, SO=open
IDDR3 Read Current 20 mA CE#=0.1 VDD/0.9 VDD@50 MHz, SO=open
IDDW Program and Erase Current 30 mA CE#=VDD
ISB Standby Current 20 µA CE#=VDD, VIN=VDD or VSS
ILI Input Leakage Current AVIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current AVOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8VVDD=VDD Min
VIH Input High Voltage 0.7 VDD VVDD=VDD Max
VOL Output Low Voltage 0.2 VIOL=100 µA, VDD=VDD Min
VOL2 Output Low Voltage 0.4 VIOL=1.6 mA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 VIOH=-100 µA, VDD=VDD Min
SST25VF016B
DS20005044C-page 20 2015 Microchip Technology Inc.
TABLE 5-4: CAPACITANCE (TA = 25°C, F=1 MHz, OTHER PINS OPEN)
Parameter Description Test Condition Maximum
COUT1Output Pin Capacitance VOUT = 0V12 pF
CIN1Input Capacitance VIN = 0V6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 5-5: RELIABILITY CHARACTERISTICS
Symbol Parameter Minimum Specification Units Test Method
NEND1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
TABLE 5-6: AC OPERATING CHARACTERISTICS
Symbol Parameter
25 MHz 50 MHz
Min Max Min Max Units
FCLK1
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
Serial Clock Frequency 25 50 MHz
TSCKH Serial Clock High Time 189ns
TSCKL Serial Clock Low Time 189ns
TSCKR2
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns
TSCKF Serial Clock Fall Time (Slew Rate) 0.1 0.1 V/ns
TCES3
3. Relative to SCK.
CE# Active Setup Time 10 5 ns
TCEH3CE# Active Hold Time 10 5 ns
TCHS3CE# Not Active Setup Time 10 5 ns
TCHH3CE# Not Active Hold Time 10 5 ns
TCPH CE# High Time 100 50 ns
TCHZ CE# High to High-Z Output 15 8ns
TCLZ SCK Low to Low-Z Output 00ns
TDS Data In Setup Time 52ns
TDH Data In Hold Time 55ns
THLS HOLD# Low Setup Time 10 5 ns
THHS HOLD# High Setup Time 10 5 ns
THLH HOLD# Low Hold Time 10 5 ns
THHH HOLD# High Hold Time 10 5 ns
THZ HOLD# Low to High-Z Output 20 8ns
TLZ HOLD# High to Low-Z Output 15 8ns
TOH Output Hold from SCK Change 00ns
TVOutput Valid from SCK 15 8ns
TSE Sector-Erase 25 25 ms
TBE Block-Erase 25 25 ms
TSCE Chip-Erase 50 50 ms
TBP Byte-Program 10 10 µs
2015 Microchip Technology Inc. DS20005044C-page 21
SST25VF016B
FIGURE 5-1: SERIAL INPUT TIMING DIAGRAM
FIGURE 5-2: SERIAL OUTPUT TIMING DIAGRAM
FIGURE 5-3: HOLD TIMING DIAGRAM
HIGH-Z HIGH-Z
CE#
SO
SI
SCK
MSB LSB
TDS TDH
TCHH TCES TCEH TCHS
TSCKR
TSCKF
TCPH
1271 SerIn.0
1271 SerOut.0
CE#
SI
SO
SCK
MSB
TCLZ
TV
TSCKH
TCHZ
TOH
TSCKL
LSB
THZ TLZ
THHH THLS
THLH
THHS
1271 Hold.0
HOLD#
CE#
SCK
SO
SI
SST25VF016B
DS20005044C-page 22 2015 Microchip Technology Inc.
5.1 Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0v
- 3.0V in less than 300 ms). See Table 5-7 and Figure
5-4 for more information.
FIGURE 5-4: POWER-UP TIMING DIAGRAM
TABLE 5-7: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VDD Min to Read Operation 100 µs
TPU-WRITE1VDD Min to Write Operation 100 µs
Time
VDD Min
VDD Max
VDD
Device fully accessible
TPU-READ
TPU-WRITE
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
1271 PwrUp.0
2015 Microchip Technology Inc. DS20005044C-page 23
SST25VF016B
FIGURE 5-5: AC INPUT/OUTPUT REFERENCE WAVEFORMS
FIGURE 5-6: A TEST LOAD EXAMPLE
1271 IORef.0
REFERENCE POINTS OUTPUTINPUT
VHT
VLT
VHT
VLT
VIHT
VILT
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement
reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10%
90%) are <5 ns.
Note: VHT - VHIGH Tes t
VLT - VLOW Tes t
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Te st
1271 TstLd.0
TO TESTER
TO DUT
CL
Pmn Idznllfier \ 540 SIS I:E |:E I:E I:I: TOP VIEW :1 j: j: :I:I 540 515 4’ fl m SIDE VIEW + +% ENDVIEW <_. lie="" i="" 75="" *="" &i="" _a'="" ois7="" \="" '="" i="" —=""> I<— 3="" d80="" as="" m="" m="" 3="" tao="" |_|="">
SST25VF016B
DS20005044C-page 24 2015 Microchip Technology Inc.
6.0 PACKAGING DIAGRAMS
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-14005A Sheet 1 of 1
8-Lead Small Outline Integrated Circuit (S2AE/F) - .208 Inch Body [SOIC]
Note:
1. All linear dimensions are in millimeters (max/min).
2. Coplanarity: 0.1 mm
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
TOPVIEW SIDEV‘EW BOTTOM VDEW PM W \ / Pm SH — Comer D — 1 L17 sit U snn+nm UU <— auuzum="" ——="" cross="" section="" %="" e="" —="" w="" t="" 5="" mm="" 515="" an="" an="" 0.90="" 0="" 7n="">
2015 Microchip Technology Inc. DS20005044C-page 25
SST25VF016B
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing C04-14008A Sheet 1 of 1
8-Lead Very, Very Thin Small Outline No-Leads (QAE/F) - 5x6 mm Body [WSON]
Note:
1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.
3. The external paddle is electrically connected to the
die back-side and possibly to certain VSS leads.
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the VSS of the unit.
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
HT LT
SST25VF016B
DS20005044C-page 26 2015 Microchip Technology Inc.
TABLE 6-1: REVISION HISTORY
Revision Description Date
00 Initial release of data sheet Apr 2005
01 Corrected “JEDEC Read-ID” on page 17 including timing diagram
Corrected VHT and VLT values in Figure 5-5 on page 23
Sep 2005
02 Migrated document to a Data Sheet
Updated Surface Mount Solder Reflow Tem p e ra t ure information
Jan 2006
03 Edited Clock Frequency speed from 50 MHz to 80 MHz in Features, page 1
Revised Table 5 for 80 MHz
Edited High Speed Read for 80 MHz, page 10
Edited Table 8, page 21
Added 80 MHz columns to Table 12, page 22
Updated Product Ordering Information and Valid Combination, page 26
Sep 2008
04 Updated “Auto Address Increment (AAI) Word-Program”, “End-of-Write
Detection”, and “Hardware End-of-Write Detection” on page 11.
Revised Figures 4-8 and 4-9 on page page 12.
Updated document to new format.
Jan 2011
AAdded “Power-Up Specifications” on page 22
Updated Table 5-7 on page 22
Released document under letter revision system
Updated Spec number from S71271 to DS25044
Aug 2011
BUpdated document to new corporate format
EOL of all 75 MHz parts. Replacement parts are the 50 MHz parts found in
this data sheet.
Jan 2015
CFixed an error in “Product Identification System” on page 28Jul 2015
assxslance cuslom ed \r
2015 Microchip Technology Inc. DS20005044C-page 27
SST25VF016B
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following informa-
tion:
Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
General Technical SupportFrequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registration
instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
PART NO. XX T XX Min Tern ax
SST25VF016B
DS20005044C-page 28 2015 Microchip Technology Inc.
7.0 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XX
XX
Operating
Device
Device: SST25VF016B = 16 Mbit, 2.7-3.6V, SPI Flash Memory
Operating
Frequency:
50 = 50 MHz
Minimum
Endurance
4 = 10,000 cycles
Temperature: I = -40°C to +85°C
C = 0°C to +70°C
Package: QAF/QAE1= WSON (6mm x 5mm Body), 8-lead
S2AF/S2AE1= SOIC (200 mil Body), 8-lead
1. Suffix E = Matte Tin finish
Suffix F = Nickel plating with Gold top (outer) layer finish
Tape and
Reel Flag:
T = Tape and Reel
Valid Combinations:
SST25VF016B-50-4C-S2AF
SST25VF016B-50-4C-S2AF-T
SST25VF016B-50-4I-S2AF
SST25VF016B-50-4I-S2AF-T
SST25VF016B-50-4I-S2AE
SST25VF016B-50-4I-S2AE-T
SST25VF016B-50-4C-QAF
SST25VF016B-50-4C-QAF-T
SST25VF016B-50-4I-QAF
SST25VF016B-50-4I-QAF-T
SST25VF016B-50-4I-QAE
SST25VF016B-50-4I-QAE-T
X
Tape/Reel
Indicator
Frequency
XX
Package
Temp
Range
Minimum
Endurance
YSTEM
2015 Microchip Technology Inc. DS20005044C-page 29
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A.,3 All Rights Reserved.
ISBN: 978-1-6277-622-8
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
6‘ ‘MICROCHIP
2015 Microchip Technology Inc. DS20005044C-page 30
Worldwide Sales and Service
AMERICAS
Corporate Office
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Tel: 480-792-7200
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Technical Support:
http://www.microchip.com/
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Web Address:
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Fax: 972-818-2924
Detroit
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Tel: 281-894-5983
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Tel: 86-532-8502-7355
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Fax: 82-2-558-5932 or
82-2-558-5934
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Fax: 33-1-69-30-90-79
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Tel: 49-2129-3766400
Germany - Karlsruhe
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Fax: 44-118-921-5820
07/14/15

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