LTC2654 Datasheet by Analog Devices Inc.

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LTLII‘IEAQ mm TECHNOLOGY
LTC2654
1
2654f
BLOCK DIAGRAM
DESCRIPTION
Quad 16-/12-Bit Rail-to-Rail
DACs with 10ppm/°C
Max Reference
The LTC
®
2654 is a family of quad 16-/12-bit rail-to-rail
DACs with integrated 10ppm/°C maximum reference . The
DACs have built-in high performance, rail-to-rail, output
buffers and are guaranteed monotonic. The LTC2654-L
has a full-scale output of 2.5V with the integrated refer-
ence and operates from a single 2.7V to 5.5V supply.
The LTC2654-H has a full-scale output of 4.096V with
the integrated reference and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to 2 times the
external reference voltage.
These DACs communicate via a SPI/MICROWIRE compat-
ible 4-wire serial interface which operates at clock rates
up to 50MHz. The LTC2654 incorporates a power-on reset
circuit that is controlled by the PORSEL pin. If PORSEL
is tied to GND the DACs reset to zero-scale. If PORSEL is
tied to VCC, the DACs reset to mid-scale.
FEATURES
APPLICATIONS
n Precision Reference 10ppm/°C Max
n Maximum INL Error: ±4LSB at 16-Bits
n Low ±2mV (Max) Offset Error
n Guaranteed Monotonic Over Temperature
n Selectable Internal or External Reference
n 2.7V to 5.5V Supply Range (LTC2654-L)
n Integrated Reference Buffers
n Ultralow Crosstalk Between DACs (<3nVs)
n Power-on-Reset to Zero-Scale/Mid-Scale
n Asynchronous DAC Update Pin
n Tiny 20-Lead 4mm × 4mm QFN and 16-Lead Narrow
SSOP Packages
n Mobile Communications
n Process Control and Industrial Automation
n Instrumentation
n Automatic Test Equipment
n Automotive
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245, 6891433 and patent pending.
INL Curve
CODE
128
INL (LSB)
4
2
3
1
0
–2
–1
–3
–4 16384 49152
2654 TA01b
6553532768
VCC = 5V
2654 TA01a
GND
VOUTA
VOUTB
SCK
CS/LD
LDAC
REFLO
REFIN/OUT
REFCOMP
VCC
VOUTD
VOUTC
PORSEL
SDO
SDI
CLR
INTERNAL REFERENCE
DAC A
CONTROL LOGIC DECODE
POWER-ON
RESET
DAC B
DAC D
DAC C
REGISTER
32-BIT SHIFT REGISTER
REGISTER
REGISTERREGISTER
REGISTERREGISTER
REGISTERREGISTER
LTC2654 flflflflflflflfl UUUUUUUU L7LJCUEN2
LTC2654
2
2654f
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ................................... 0.3V to 6V
CS/LD, SCK, SDI, LDAC, CLR, REFLO .......... 0.3V to 6V
VOUTA-D ............................0.3V to Min (VCC + 0.3V, 6V)
REFIN/OUT, REFCOMP .....0.3V to Min (VCC + 0.3V, 6V)
PORSEL, SDO ..................0.3V to Min (VCC + 0.3V, 6V)
Operating Temperature Range
LTC2654C ................................................ 0°C to 70°C
LTC2654I..............................................40°C to 85°C
(Notes 1, 2)
GN PACKAGE
16-LEAD PLASTIC SSOP NARROW
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
REFLO
VOUTA
REFCOMP
VOUTB
REFIN/OUT
LDAC
CS/LD
SCK
GND
VCC
VOUTD
VOUTC
PORSEL
CLR
SDO
SDI
TJMAX = 150°C, θJA = 110°C/W
20 19 18 17 16
6 7 8
TOP VIEW
21
GND
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
9 10
5
4
3
2
1
11
12
13
14
15
VOUTA
REFCOMP
VOUTB
REFIN/OUT
LDAC
DNC
VOUTD
VOUTC
PORSEL
CLR
REFLO
GND
VCC
DNC
DNC
CS/LD
SCK
DNC
SDI
SDO
TJMAX = 150°C, θJA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
Maximum Junction Temperature........................... 150°C
Storage Temperature Range ...................65°C to 150°C
Lead Temperature
(Soldering GN-Package, 10 sec) ....................... 300°C
LTC2654 J L7 LJUW
LTC2654
3
2654f
PRODUCT SELECTOR GUIDE
LTC2654 BC UF –L 16 #TR PBF
LEAD FREE DESIGNATOR
TAPE AND REEL
TR = Tape and Reel
RESOLUTION
16 = 16-Bit
12 = 12-Bit
FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE
L = 2.5V
H = 4.096V
PACKAGE TYPE
UF = 20-Lead (4mm × 4mm) Plastic QFN
GN = 16-Lead Narrow SSOP
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
ELECTRICAL GRADE (OPTIONAL)
B = ±4LSB INL (MAX)
PRODUCT PART NUMBER
Consult LTC Marketing for information on non-standard lead based fi nish parts. Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC2654
LTC2654
4
2654f
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION
TEMPERATURE
RANGE
MAXIMUM
INL
LTC2654BCGN-L16#PBF LTC2654BCGN-L16#TRPBF 654L16 16-Lead Narrow SSOP 0°C to 70°C ±4
LTC2654BIGN-L16#PBF LTC2654BIGN-L16#TRPBF 654L16 16-Lead Narrow SSOP –40°C to 85°C ±4
LTC2654BCUF-L16#PBF LTC2654BCUF-L16#TRPBF 54L16 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±4
LTC2654BIUF-L16#PBF LTC2654BIUF-L16#TRPBF 54L16 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±4
LTC2654BCGN-H16#PBF LTC2654BCGN-H16#TRPBF 654H16 16-Lead Narrow SSOP 0°C to 70°C ±4
LTC2654BIGN-H16#PBF LTC2654BIGN-H16#TRPBF 654H16 16-Lead Narrow SSOP –40°C to 85°C ±4
LTC2654BCUF-H16#PBF LTC2654BCUF-H16#TRPBF 54H16 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±4
LTC2654BIUF-H16#PBF LTC2654BIUF-H16#TRPBF 54H16 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±4
LTC2654CGN-L12#PBF LTC2654CGN-L12#TRPBF 654L12 16-Lead Narrow SSOP 0°C to 70°C ±1
LTC2654IGN-L12#PBF LTC2654IGN-L12#TRPBF 654L12 16-Lead Narrow SSOP –40°C to 85°C ±1
LTC2654CUF-L12#PBF LTC2654CUF-L12#TRPBF 54L12 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±1
LTC2654IUF-L12#PBF LTC2654IUF-L12#TRPBF 54L12 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±1
LTC2654CGN-H12#PBF LTC2654CGN-H12#TRPBF 654H12 16-Lead Narrow SSOP 0°C to 70°C ±1
LTC2654IGN-H12#PBF LTC2654IGN-H12#TRPBF 654H12 16-Lead Narrow SSOP –40°C to 85°C ±1
LTC2654CUF-H12#PBF LTC2654CUF-H12#TRPBF 54H12 20-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C ±1
LTC2654IUF-H12#PBF LTC2654IUF-H12#TRPBF 54H12 20-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C ±1
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC2654B-L16/LTC2654-L12 (Internal Reference = 1.25V)
SYMBOL PARAMETER CONDITIONS
LTC2654-12 LTC2654B-16
UNITSMIN TYP MAX MIN TYP MAX
DC Performance
Resolution l12 16 Bits
Monotonicity (Note 3) l12 16 Bits
DNL Differential Nonlinearity (Note 3) l±0.1 ±0.5 ±0.3 ±1 LSB
INL Integral Nonlinearity VCC = 5.5V, VREF = 2.5V (Note 3) l±0.5 ±1 ±2 ±4 LSB
Load Regulation VCC = 5V ±10%, Integral Reference,
Mid-Scale, –15mA ≤ IOUT ≤ 15mA
l0.04 0.125 0.6 2 LSB/mA
VCC = 3V ±10%, Integral Reference,
Mid-Scale, –7.5mA ≤ IOUT ≤ 7.5mA
l0.06 0.25 1 4 LSB/mA
ZSE Zero-Scale Error l13 13 mV
VOS Offset Error (Note 4) l±1 ±2 ±1 ±2 mV
VOS Temperature Coeffi cient 5 5 µV/°C
GE Gain Error (Note 13) l±0.02 ±0.1 ±0.02 ±0.1 %FSR
Gain Temperature Coeffi cient 1 1 ppm/°C
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2654 L7 LJUW
LTC2654
5
2654f
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifi ed.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT DAC Output Span Internal Reference
External Reference = VEXTREF
0 to 2.5
0 to 2VEXTREF
V
V
PSR Power Supply Rejection VCC ±10% –80 dB
ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference,
Mid-Scale, –15mA ≤ IOUT ≤ 15mA
VCC = 3V ±10%, Internal Reference,
Mid-Scale, –7.5mA ≤ IOUT ≤ 7.5mA
l
l
0.04
0.04
0.15
0.15
DC Crosstalk Due to Full-Scale Output Change (Note 5)
Due to Load Current Change (Note 5)
Due to Powering Down (per Channel) (Note 5)
±1.5
±2
±1
µV
µV/mA
µV
ISC Short-Circuit Output Current VCC = 5.5V VEXTREF = 2.8V (Note 6)
Code: Zero-Scale; Forcing Output to VCC (Note 6)
Code: Full-Scale; Forcing Output to GND (Note 6)
l
l
20
20
65
65
mA
mA
VCC = 2.7V VEXTREF = 1.4V
Code: Zero-Scale; Forcing Output to VCC
Code: Full-Scale; Forcing Output to GND
l
l
10
10
45
45
mA
mA
LTC2654B-L16/ LTC2654-L12 (Internal Reference = 1.25V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference
Reference Output Voltage 1.248 1.25 1.252 V
Reference Temperature Coeffi cient (Note 7) ±2 ±10 ppm/°C
Reference Line Regulation VCC ±10% –80 dB
Reference Short-Circuit Current VCC = 5.5V, Forcing Output to GND l35 mA
Refcomp Pin Short-Circuit Current VCC = 5.5V, Forcing Output to GND l60 200 µA
Reference Load Regulation VCC = 3V ±10% or 5V ±10%, IOUT = 100µA Sourcing 40 mV/mA
Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1µF, at f = 1kHz 30 nV/√Hz
Reference Input Range External Reference Mode (Note 13) l0.5 VCC/2 V
Reference Input Current l0.001 1 µA
Reference Input Capacitance (Note 9) l20 pF
Power Supply
VCC Positive Supply Voltage For Specifi ed Performance l2.7 5.5 V
ICC Supply Current VCC = 5V, Internal Reference On (Note 8)
VCC = 5V, Internal Reference Off (Note 8)
VCC = 3V, Internal Reference On (Note 8)
VCC = 3V, Internal Reference Off (Note 8)
l
l
l
l
1.7
1.3
1.6
1.2
2.5
2
2.2
1.7
mA
mA
mA
mA
ISD Supply Current in Shutdown Mode VCC = 5V (Note 8) lA
Digital I/O
VIH Digital Input High Voltage VCC = 3.6V to 5.5V
VCC = 2.7V to 3.6V
l
l
2.4
2.0
V
V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
l
l
0.8
0.6
V
V
VOH Digital Output High Voltage Load Current = –100µA lVCC – 0.4 V
VOL Digital Output Low Voltage Load Current = 100µA l0.4 V
LTC2654
LTC2654
6
2654f
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specifi ed.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOUT DAC Output Span Internal Reference
External Reference = VEXTREF
0 to 4.096
0 to 2VEXTREF
V
V
PSR Power Supply Rejection VCC ±10% –80 dB
ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-Scale,
–15mA ≤ IOUT ≤ 15mA
l0.04 0.15
LTC2654B-H16/LTC2654-H12 (Internal Reference = 2.048V)
SYMBOL PARAMETER CONDITIONS
LTC2654-12 LTC2654B-16
UNITSMIN TYP MAX MIN TYP MAX
DC Performance
Resolution l12 16 Bits
Monotonicity (Note 3) l12 16 Bits
DNL Differential Nonlinearity (Note 3) l±0.1 ±0.5 ±0.3 ±1 LSB
INL Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V l±0.5 ±1 ±2 ±4 LSB
Load Regulation VCC = 5V ±10%, Integral Reference,
Mid-Scale, –15mA ≤ IOUT ≤ 15mA
l0.04 0.125 0.6 2 LSB/mA
ZSE Zero-Scale Error l13 13 mV
VOS Offset Error (Note 4) l±1 ±2 ±1 ±2 mV
VOS Temperature Coeffi cient 5 5 µV/°C
GE Gain Error (Note 13) l±0.02 ±0.1 ±0.02 ±0.1 %FSR
Gain Temperature Coeffi cient 1 1 ppm/°C
LTC2654B-L16/ LTC2654-L12 (Internal Reference = 1.25V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ILK Digital Input Leakage VIN = GND to VCC l±1 µA
CIN Digital Input Capacitance (Note 9) l8pF
AC Performance
tSSettling Time ±0.024% (±1LSB at 12 Bits) (Note 10)
±0.0015% (±1LSB at 16 Bits) (Note 10)
4.2
8.9
µs
µs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)
±0.0015% (±1LSB at 16 Bits)
2.2
4.9
µs
µs
Voltage Output Slew Rate 1.8 V/µs
Capacitive Load Driving 1000 pF
Glitch Impulse At Mid-Scale Transition (Note 11) 3 nVs
DAC-to-DAC Crosstalk Due to Full-Scale Output Change (Note 12) 3 nVs
Multiplying Bandwidth 150 kHz
enOutput Voltage Noise Density At f = 1kHz
At f = 10kHz
85
80
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Internal Reference
8
400
µVP-P
µVP-P
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.
LTC2654 L7 LJUW
LTC2654
7
2654f
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Crosstalk Due to Full-Scale Output Change (Note 5)
Due to Load Current Change (Note 5)
Due to Powering Down (per Channel) (Note 5)
±1.5
±2
±1
µV
µV/mA
µV
ISC Short-Circuit Output Current VCC = 5.5V VEXTREF = 2.8V (Note 6)
Code: Zero-Scale; Forcing Output to VCC (Note 6)
Code: Full-Scale; Forcing Output to GND (Note 6)
l
l
20
20
65
65
mA
mA
LTC2654B-H16/ LTC2654-H12 (Internal Reference = 2.048V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference
Reference Output Voltage 2.044 2.048 2.052 V
Reference Temperature Coeffi cient (Note 7) ±2 ±10 ppm/°C
Reference Line Regulation VCC ±10% –80 dB
Reference Short-Circuit Current VCC = 5.5V, Forcing Output to GND l35 mA
Refcomp Pin Short-Circuit Current VCC = 5.5V, Forcing Output to GND l60 200 µA
Reference Load Regulation VCC = 5V ±10%, IOUT = 100µA Sourcing 40 mV/mA
Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1µF, at f = 1kHz 35 nV/√Hz
Reference Input Range External Reference Mode (Note 13) l0.5 VCC/2 V
Reference Input Current l0.001 1 µA
Reference Input Capacitance (Note 9) l20 pF
Power Supply
VCC Positive Supply Voltage For Specifi ed Performance l4.5 5.5 V
ICC Supply Current VCC = 5V, Internal Reference On (Note 8)
VCC = 5V, Internal Reference Off (Note 8)
l
l
1.9
1.5
2.5
2
mA
mA
ISD Supply Current in Shutdown Mode VCC = 5V (Note 8) lA
Digital I/O
VIH Digital Input High Voltage VCC = 4.5V to 5.6V l2.4 V
VIL Digital Input Low Voltage VCC = 4.5V to 5.5V l0.8 V
VOH Digital Output High Voltage Load Current = –100µA lVCC – 0.4 V
VOL Digital Output Low Voltage Load Current = 100µA l0.4 V
ILK Digital Input Leakage VIN = GND to VCC l±1 µA
CIN Digital Input Capacitance (Note 9) l8pF
AC Performance
tSSettling Time ±0.024% (±1LSB at 12 Bits) (Note 10)
±0.0015% (±1LSB at 16 Bits) (Note 10)
4.6
7.9
µs
µs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)
±0.0015% (±1LSB at 16 Bits)
2.0
3.8
µs
µs
Voltage Output Slew Rate 1.8 V/µs
Capacitive Load Driving 1000 pF
Glitch Impulse At Mid-Scale Transition (Note 11) 6 nVs
DAC-to-DAC Crosstalk Due to Full-Scale Output Change (Note 12) 3 nVs
Multiplying Bandwidth 150 kHz
LTC2654
LTC2654
8
2654f
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specifi ed.
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C.
LTC2654B-L16/LTC2654-L12/LTC2654B-H16/LTC2654-H12
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
t1SDI Valid to SCK Setup l4ns
t2SDI Valid to SCK Hold l4ns
t3SCK High Time l9ns
t4SCK Low Time l9ns
t5CS/LD Pulse Width l10 ns
t6LSB SCK High to CS/LD High l7ns
t7CS/LD Low to SCK High l7ns
t8SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF
VCC = 4.5V to 5.5V
VCC = 2.7V to 4.5V
l
l
20
45
ns
ns
t9CLR Pulse Width l20 ns
t10 CS/LD High to SCK Positive Edge l7ns
t12 LDAC Pulse Width l15 ns
t13 CS/LD High to LDAC High or Low Transition l200 ns
SCK Frequency 50% Duty Cycle l50 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltages with respect to GND.
Note 3: Linearity and monotonicity are defi ned from code kL to code 2N–1,
where N is the resolution and kL is the lower end code for which no output
limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and linearity is
defi ned from code 128 to code 65535. For VREF = 2.5V and N = 12, kL = 8
and linearity is defi ned from code 8 to code 4,095.
Note 4: Inferred from measurement at code 128 (LTC2654-16), or code 8
(LTC2654-12).
Note 5: DC Crosstalk is measured with VCC = 5V and using internal
reference, with the measured DAC at mid-scale.
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specifi ed maximum operating junction temperature may impair
device reliability.
Note 7: Temperature coeffi cient is calculated by dividing the maximum
change in output voltage by the specifi ed temperature range. Maximum
temperature coeffi cient is guaranteed for C-grade only.
Note 8: Digital inputs at 0V or VCC.
Note 9: Guaranteed by design and not production tested.
Note 10: Internal Reference mode. DAC is stepped ¼ scale to ¾ scale and
¾ scale to ¼ scale. Load is 2k in parallel with 200pF to GND.
Note 11: VCC = 5V, Internal Reference mode. DAC is stepped ±1 LSB
between half-scale and half-scale - 1. Load is 2k in parallel with 200pF
to GND.
Note 12: DAC to DAC Crosstalk is the glitch that appears at the output
of one DAC due to a full-scale change at the output of another DAC. It is
measured with VCC = 5V and using internal reference, with the measured
DAC at mid-scale. CREFIN/OUT = No Load.
Note 13: Gain error specifi cation may be degraded for reference input
voltages less than 1V. See Gain Error vs Reference Input Voltage curve in
the Typical Performance Characteristics section.
LTC2654B-H16/ LTC2654-H12 (Internal Reference = 2.048V)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
enOutput Voltage Noise Density At f = 1kHz
At f = 10kHz
85
80
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz, Internal Reference
0.1Hz to 200kHz, Internal Reference
12
450
µVP-P
µVP-P
LTC2654 L7 LJDW
LTC2654
9
2654f
TYPICAL PERFORMANCE CHARACTERISTICS
DNL vs Temperature
Reference Output Voltage
vs Temperature
Sampling to ±1LSB Rising Sampling to ±1LSB Falling
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
LTC2654-L16
CODE
128
INL (LSB)
4
3
1
–1
2
0
–2
–3
–4 16384 49152
2654 G01
6553532768
VCC = 3V
CODE
128
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 16384 49152
2654 G02
6553532768
VCC = 3V
TEMPERATURE (°C)
–50
INL (LSB)
4
2
3
1
0
–2
–3
–1
–4 –30 11090
2654 G03
130–10 10 30 50 70
VCC = 3V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 –30 11090
2654 G04
130–10 10 30 50 70
VCC = 3V
DNL (POS)
DNL (NEG)
TEMPERATURE (°C)
–50
VREF (V)
1.253
1.251
1.252
1.250
1.249
1.248
1.247 –30 11090
2654 G05
130–10 10 30 50 70
VCC = 3V
CS/LD
3V/DIV
VOUT
200µV/DIV
2654 G06
2µs/DIV
8µs
1/4 SCALE TO 3/4 SCALE STEP
VCC = 3V, VFS = 2.50V
RL = 2k, CL = 200pF
CS/LD
3V/DIV
VOUT
200µV/DIV
2654 G07
2µs/DIV
8.1µs
3/4 SCALE TO 1/4 SCALE STEP
VCC = 3V, VFS = 2.50V
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
LTC2654 L7Hߤߤ
LTC2654
10
2654f
TYPICAL PERFORMANCE CHARACTERISTICS
DNL vs Temperature
Reference Output Voltage
vs Temperature
Settling to ±1LSB Rising Settling to ±1LSB Falling
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
LTC2654-H16
CODE
128
INL (LSB)
4
2
3
1
0
–2
–1
–3
–4 16384 49152
2654 G08
6553532768
VCC = 5V
CODE
128
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 16384 49152
2654 G09
6553532768
VCC = 5V
TEMPERATURE (°C)
–50
INL (LSB)
4
2
3
1
0
–2
–3
–1
–4 –30 11090
2654 G10
130–10 10 30 50 70
VCC = 5V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 –30 11090
2654 G11
130–10 10 30 50 70
VCC = 5V
DNL (POS)
DNL (NEG)
TEMPERATURE (°C)
–50
VREF (V)
2.054
2.052
2.050
2.048
2.046
2.044
2.042 –30 11090
2654 G12
130–10 10 30 50 70
VCC = 5V
CS/LD
5V/DIV
VOUT
250µV/DIV
2654 G13
2µs/DIV
7.9µs
1/4 SCALE TO 3/4 SCALE STEP
VCC = 5V, VFS = 4.096V
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
CS/LD
5V/DIV
VOUT
250µV/DIV
2654 G14
2µs/DIV
6.8µs
3/4 SCALE TO 1/4 SCALE STEP
VCC = 5V, VFS = 4.096V
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
LTC2654 L7 LJDW
LTC2654
11
2654f
TYPICAL PERFORMANCE CHARACTERISTICS
Load Regulation Current Limiting
Headroom at Rails
vs Output Current
Offset Error vs Temperature Zero-Scale Error vs Temperature Gain Error vs Temperature
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB (12-Bit) Rising
LTC2654-12
LTC2654-16
CODE
0
INL (LSB)
1.0
0.5
0
–0.5
–1.0 1024 3072
2654 G15
40952048
VCC = 5V
VREF = 2.048V
CODE
0
DNL (LSB)
1.0
0.5
0
–0.5
–1.0 1024 3072
2654 G16
40952048
VCC = 3V
VREF = 1.25V CS/LD
5V/DIV
VOUT
1mV/DIV
2654 G17
2µs/DIV
4.6µs
1/4 SCALE TO 3/4 SCALE STEP
VCC = 5V, VFS = 4.095V, RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
IOUT (mA)
INTERNAL REF
CODE = MID-SCALE
–50
$VOUT (V)
10
4
6
8
2
0
–4
–2
–6
–8
–10 –30–40 4030
2654 G18
50–20 –10 0 10 20
VCC = 5V (LTC2654-H)
VCC = 3V (LTC2654-L)
IOUT (mA)
INTERNAL REF
CODE = MID-SCALE
–50
$VOUT (V)
0.20
0.05
0.10
0.15
0
–0.05
–0.10
–0.15
–0.20 –30–40 4030
2654 G19
50–20 –10 0 10 20
VCC = 5V (LTC2654-H)
VCC = 3V (LTC2654-L)
IOUT (mA)
0
VOUT (V)
5.0
3.5
4.0
4.5
3.0
2.5
2.0
1.0
0.5
1.5
02198
2654 G20
1034567
5V (LTC2654-H) SOURCING
3V (LTC2654-L) SOURCING
5V (LTC2654-H) SINKING
3V (LTC2654-H) SINKING
TEMPERATURE (°C)
–50
OFFSET ERROR (mV)
3
1
2
0
–1
–2
–3 –10–30 110
2654 G21
13010 30 50 70 90
TEMPERATURE (°C)
–50
ZERO-SCALE ERROR (mV)
3.0
2.0
2.5
1.5
1.0
0.5
0–10–30 110
2654 G22
13010 30 50 70 90
TEMPERATURE (°C)
–50
GAIN ERROR (LSB)
64
32
16
48
0
–32
–16
–48
–64 –10–30 110
2654 G23
13010 30 50 70 90
LTC2654 L7Hߤߤ
LTC2654
12
2654f
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Logic Voltage Hardware CLR to Mid-Scale Hardware CLR
Multiplying Bandwidth Large-Signal Response Mid-Scale Glitch Impulse
Offset Error vs Reference Input Gain Error vs Reference Input ICC Shutdown vs VCC
LTC2654-16
REFERENCE VOLTAGE (V)
0.5
OFFSET ERROR (mV)
2.0
1.0
0.5
1.5
0
–1.0
–0.5
–1.5
–2.0 1
2654 G24
2.51.5 2
VCC = 5.5V
OFFSET ERROR OF 4 CHANNELS
REFERENCE VOLTAGE (V)
0.5
GAIN ERROR (LSB)
64
32
16
48
0
–32
–16
–48
–64 1
2654 G25
2.51.5 2
VCC = 5.5V
OFFSET ERROR OF 4 CHANNELS
VCC (V)
2.5
ICC (nA)
450
300
350
250
400
200
100
150
50
03 3.5 4
2654 G26
5.54.5 5
LOGIC VOLTAGE (V)
0
ICC (nA)
3.5
2.3
2.7
1.9
3.1
1.5 12
2654 G27
534
SWEEP SCK, SDI, CS/LD
BETWEEN 0V AND VCC
VCC = 5V (LTC2654-H)
VCC = 3V (LTC2654-L)
CLR
3V/DIV
VOUT
1V/DIV
2654 G28
1µs/DIV
VCC = 3V, VREF = 1.25V
CODE = FULL-SCALE
CLR
3V/DIV
VOUT
1V/DIV
2654 G29
1µs/DIV
VCC = 3V, VREF = 1.25V
CODE = FULL-SCALE
FREQUENCY (Hz)
1k
BANDWIDTH (dB)
8
2
4
0
6
–2
–6
–4
–8
–10
–12 10k
2654 G30
1M100k
VCC = 5V
VREF(DC) = 2V
VREF(AC) = 0.2VP-P
CODE = FULL-SCALE
VOUT
1V/DIV
2654 G31
2.5µs/DIV
LTC2654-H16
VCC = 5V, VFS = 4.095V
ZERO-SCALE TO FULL-SCALE
VOUT
5mV/DIV
VOUT
5mV/DIV
CS/LD
5mV/DIV
2654 G32
2µs/DIV
MSMS-1
LTC2654-H16
VCC = 5V, 5nV-s TYP
LTC2654-L16
VCC = 3V, 3nV-s TYP
L7 LJDW LTC2654
LTC2654
13
2654f
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2654-16
Power-On Reset to Mid-Scale Noise Voltage vs Frequency
DAC Output 0.1Hz to 10Hz
Voltage Noise
Reference 0.1Hz to 10Hz
Voltage Noise
DAC to DAC Crosstalk (Dynamic) Power-On Reset Glitch
VOUT
2mV/DIV
VOUT
2mV/DIV
ONE DAC
SWITCH 0-FS
2V/DIV
2654 G33
2µs/DIV
LTC2654-L16, VCC = 5V, 4nV TYP
CREFCOMP = 1000pF
CREFOUT = NO LOAD
LTC2654-L16, VCC = 5V
CREFCOMP = CREFOUT
= 0.22µF
VCC
2V/DIV
VOUT
10mV/DIV
2654 G34
200µs/DIV
ZERO-SCALE
VCC
2V/DIV
VOUT
1V/DIV
2654 G35
1ms/DIV
LTC2654-L
FREQUENCY (Hz)
10
NOISE VOLTAGE (nV/√Hz)
400
100
200
300
010k1k100
2654 G36
1M100k
VCC = 5V
CODE = MID-SCALE
INTERNAL REF
CREFCOMP = CREFOUT = 0.1µF
LTC2654-H
LTC2654-L
5µV/DIV
2654 G37
1s/DIV
VCC = 5V, LTC2654-H
CODE = MID-SCALE
INTERNAL REF
CREFCOMP = CREFOUT = 0.1µF
2µV/DIV
2654 G38
1s/DIV
VREFOUT = 2.048V
CREFCOMP = CREFOUT = 0.1µF
LTC2654 L7LJCUEN2
LTC2654
14
2654f
PIN FUNCTIONS
VOUTA to VOUTD (Pins 1, 3, 13, 14/Pins 2,4,13,14): DAC
Analog Voltage Outputs. The output range is 0V to 2 times
the voltage at the REFIN/OUT pin.
REFCOMP (Pin 2/Pin 3): Internal Reference Compensa-
tion pin. For low noise and reference stability, tie a 0.1µF
capacitor to GND. Connecting this pin to GND allows the
use of external reference at start-up.
REFIN/OUT (Pin 4/Pin 5): Reference Input/Output. This
pin acts as the internal reference output in internal refer-
ence mode and acts as the reference input pin in external
reference mode. When acting as an output the nominal
voltage at this pin is 1.25V for -L options and 2.048V
for -H options. For low noise and reference stability tie
a capacitor to GND. Capacitor value must be ≤CREFCOMP.
In external reference mode, the allowable reference input
voltage range is 0.5V to VCC/2.
LDAC (Pin 5/Pin 6): Asynchronous DAC Update Pin. If
CS/LD is high, a falling edge on LDAC immediately updates
the DAC register with the contents of the input register
(similar to a software update). If CS/LD is low when LDAC
goes low, the DAC register is updated after CS/LD returns
high. A low on the LDAC pin powers up the DAC outputs.
All the software power-down commands are ignored if
LDAC is low when CS/LD goes high.
CS/LD (Pin 6/Pin 7): Serial Interface Chip Select/Load
Input. When CS/LD is low, SCK is enabled for shifting
data on SDI into the register. When CS/LD is taken high,
SCK is disabled and the specifi ed command (see Table 1)
is executed.
SCK (Pin 7/Pin 8): Serial Interface Clock Input. CMOS
and TTL compatible.
DNC (Pins 8, 15, 16, 17/NA): Do not connect these pins.
SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is ap-
plied to SDI for transfer to the device at the rising edge of
SCK (Pin 10). The LTC2654 accepts input word lengths of
either 24 or 32 bits. See Figures 2a and 2b.
SDO (Pin 10/Pin 10): Serial Interface Data Output. This pin
is used for daisy-chain operation. The serial output of the
shift register appears at the SDO pin. The data transferred
to the device via the SDI pin is delayed 32 SCK rising edges
before being output at the next falling edge. This pin is
continuously driven and does not go high impedance when
CS/LD is taken active high.
CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic
low at this level-triggered input clears all registers and
causes the DAC voltage outputs to drop to 0V if PORSEL
pin is tied to GND. If the PORSEL pin is tied to VCC, a logic
low at CLR sets all registers to mid-scale code and causes
the DAC voltage outputs to go to mid-scale.
PORSEL (Pin 12/Pin 12): Power-On-Reset Select Pin. If
tied to GND, the DACs reset to zero-scale. If tied to VCC,
the DACs reset to mid-scale.
VCC (Pin 18/Pin 15): Supply Voltage Input. For -L op-
tions, 2.7V ≤ VCC ≤ 5.5V, and for -H options, 4.5V ≤ VCC
≤ 5.5V. Should be bypassed by a 0.1µF low ESR ceramic
capacitor to GND.
GND (Pin 19, Exposed Pad Pin 21/Pin 16): Ground.
Exposed pad must be soldered to PCB Ground.
REFLO (Pin 20/Pin 1): Reference Low Pin. The voltage at
this pin sets the zero-scale voltage of all DACs. This pin
should be tied to GND.
(QFN/SSOP)
LTC2654 \Tflfi F”? \ / \ }”\ / L7 LJUW
LTC2654
15
2654f
BLOCK DIAGRAM
TIMING DIAGRAMS
Figure 1a
Figure 1b
SDI
SDO
CS/LD
SCK
2654 F01a
t2
t10
t5t7
t6
t1
LDAC
t3t4
1232324
t13 t12
t8
CS/LD
2654 F01b
t13
LDAC
2636 BD
GND
VOUTA
VOUTB
SCK
CS/LD
LDAC
REFLO
REFIN/OUT
REFCOMP
VCC
VOUTD
VOUTC
PORSEL
SDO
SDI
CLR
INTERNAL REFERENCE
DAC A
CONTROL LOGIC DECODE
POWER-ON
RESET
DAC B
DAC D
DAC C
REGISTER
32-BIT SHIFT REGISTER
REGISTER
REGISTERREGISTER
REGISTERREGISTER
REGISTERREGISTER
LTC2654 L7LJCUEN2
LTC2654
16
2654f
OPERATION
The LTC2654 is a family of quad voltage output DACs in
20-lead 4mm × 4mm QFN and in 16-lead narrow SSOP
packages. Each DAC can operate rail-to-rail in external
reference mode, or with its full-scale voltage set by an
integrated reference. Four combinations of accuracy (16-
bit and 12-bit), and full-scale voltage (2.5V or 4.096V)
are available. The LTC2654 is controlled using a 4-wire
SPI/MICROWIRE compatible interface.
Power-On Reset
The LTC2654-L/LTC2654-H clear the output to zero-scale
if PORSEL pin is tied to GND, when power is fi rst applied,
making system initialization consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2654 con-
tains circuitry to reduce the power-on glitch. The analog
outputs typically rise less than 10mV above zero-scale
during power-on if the power supply is ramped to 5V in
1ms or more. In general, the glitch amplitude decreases
as the power supply ramp time is increased. See Power-
On-Reset Glitch in the Typical Performance Characteristics
section.
Alternatively, if PORSEL pin is tied to VCC (Pin 18/Pin 15),
The LTC2654-L/LTC2654-H set the output to mid-scale
when power is fi rst applied.
Power Supply Sequencing and Start-Up
For LTC2654 family of parts, the internal reference is
powered-up at start-up by default. If an external reference
is to be used, the REFCOMP pin (Pin 2/Pin 3) must be
hardwired to GND. Having REFCOMP hardwired to GND
at power up, will cause the REFIN/OUT pin to become
high-impedance and will allow for the use of an external
reference at start-up. However in this confi guration, internal
reference will still be ON, even though it is disconnected
from the REFIN/OUT pin and it will draw supply current. In
order to use external reference after power-up, the com-
mand Select External Reference (0111b) should be used
to turn the internal reference off (See Table 1).
The voltage at REFIN/OUT (Pin 4/Pin 5) should be kept
within the range –0.3V ≤ REFIN/OUT ≤ VCC + 0.3V (see
Absolute Maximum Ratings). Particular care should be
taken to observe these limits during power supply turn-on
and turn-off sequences, when the voltage at VCC (Pin 18/
Pin 15) is in transition.
Transfer Function
The digital-to-analog transfer function is
VOUT(IDEAL) =k
2N
•2• V
REF VREFLO
+VREFLO
where k is the decimal equivalent of the binary DAC input
code, N is the resolution of the DAC, and VREF is the volt-
age at the REFIN/OUT Pin. The resulting DAC output span
is 0V to 2VREF, as it is necessary to tie REFLO to GND.
VREF is nominally 1.25V for LTC2654-L and 2.048V for
LTC2654-H, in Internal Reference Mode.
Table 1. Command and Address Codes
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
n
0 0 0 1 Update (Power-Up) DAC Register
n
0 0 1 0 Write to Input Register
n
, Update (Power-Up) All
0 0 1 1 Write to and Update (Power-Up)
n
0 1 0 0 Power-Down
n
0 1 0 1 Power-Down Chip (All DAC’s and Reference)
0 1 1 0 Select Internal Reference (Power-Up Reference)
0 1 1 1 Select External Reference (Power-Down Reference)
1 1 1 1 No Operation
ADDRESS (
n
)*
A3 A2 A1 A0
0 0 0 0 DAC A
0 0 0 1 DAC B
0 0 1 0 DAC C
0 0 1 1 DAC D
1 1 1 1 All DACs
*Command and address codes not shown are reserved and should not
be used.
LTC2654 L7 LJUW
LTC2654
17
2654f
OPERATION
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded fi rst; followed by
the 4-bit DAC address, A3-A0; and fi nally the 16-bit data
word. For the LTC2654-16 the data word comprises the
16-bit input code, ordered MSB-to-LSB. For the LTC2654-
12 the data word comprises the 12-bit input code, ordered
MSB-to-LSB followed by four don’t-care bits. Data can
only be transferred to the LTC2654 when the CS/LD signal
is low. The rising edge of CS/LD ends the data transfer
and causes the device to carry out the action specifi ed in
the 24-bit input word. The complete sequence is shown
in Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The fi rst four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC,
n
. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16- or 12-bit input code,
and is converted to an analog voltage at the DAC output.
The update operation also powers up the selected DAC
if it had been in power-down mode. The data path and
registers are shown in the block diagram.
While the minimum input word is 24 bits, it may option-
ally be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits are transferred to the device fi rst, followed
by the 24-bit word as just described. Figure 2b shows the
32-bit sequence. The 32-bit word is required for daisy
chain operation, and is also available to accommodate
microprocessors that have a minimum word width of
16 bits (2 bytes). The 16-bit data word is ignored for all
commands that do not include a write operation.
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge. The SDO pin is continuously driven
and does not go high impedance when CS/LD is taken
active high.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a daisy-chain series is confi gured
by connecting SDO of each up-stream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire chain.
Because of this, the devices can be addressed and con-
trolled individually by simply concatenating their input
words; the fi rst instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is fi rst taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
rst device as the data input. When the data transfer is
complete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111b) for the other devices in the chain.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four DAC outputs are needed. When in power-down,
the buffer amplifi ers, bias circuits and integrated reference
circuits are disabled, and draw essentially zero current.
The DAC outputs are put into a high-impedance state, and
the output pins are passively pulled to ground through
individual 80k resistors. Input- and DAC-register contents
are not disturbed during power-down.
LTC2654 Ix} L7Hߤߤ
LTC2654
18
2654f
OPERATION
Figure 2a. LTC2654-16 24-Bit Load Sequence (Minimum Input Word)
LTC2654-12 SDI Data Word: 12-Bit Input Code + 4 Don’t Care Bits
Figure 2b. LTC2654-16 32-Bit Load Sequence.
LTC2654-12 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t Care Bits
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
CS/LD
SCK
SDI
COMMAND WORD ADDRESS DATA WORD
24-BIT INPUT WORD
2654 F02a
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX
CS/LD
SCK
SDI
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX
SDO
COMMAND WORD DATA WORD
DON’T CARE ADDRESS WORD
2654 F02b
PREVIOUS 32-BIT INPUT WORD CURRENT
32-BIT
INPUT WORD
t2
t1
t3t4
t8
PREVIOUS D15 PREVIOUS D14
D15
1817
SDI
SDO
SCK
D14
LTC2654 L7 LJUW
LTC2654
19
2654f
OPERATION
Any channel or combination of DAC channels can be put
into power-down mode by using command 0100b in
combination with the appropriate DAC address, (
n
). The
integrated reference is automatically powered down when
external reference is selected using command 0111b. In
addition, all the DAC channels and the integrated refer-
ence together can be put into power-down mode using
Power-Down Chip command 0101b. For all power-down
commands the 16-bit data word is ignored, but still needs
to be clocked in.
Normal operation resumes by executing any command
which includes a DAC update, in software as shown in
Table 1 or by taking the asynchronous LDAC pin low.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state is
powered up and updated, normal settling is delayed. If less
than four DACs are in a powered-down state prior to the
update command, the power-up delay time is 12s. If on
the other hand, all four DACs and the integrated reference
are powered down, then the main bias generation circuit
block has been automatically shut down in addition to the
individual DAC amplifi ers and integrated reference. In this
case, the power up delay time is 14s. The power-up of
integrated reference depends on the command that pow-
ered it down. If the reference is powered down using the
Select External Reference Command (0111b) then it can
only be powered back-up using Select Internal Reference
Command (0110b). However if the reference was powered
down using Power-Down Chip Command (0101b) then in
addition to Select Internal Reference Command (0110b),
any command that powers up the DACs will also power-up
the integrated reference.
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 1, the
LDAC pin asynchronously updates all the DAC registers
with the contents of the input registers.
If CS/LD is high, a low on the LDAC pin causes all the
DAC registers to be updated with the contents of the in-
put registers.
If CS/LD is low, a low going pulse on the LDAC pin before
the rising edge of CS/LD powers up all the DAC outputs but
does not cause the output to be updated. If LDAC remains
low after the rising edge of CS/LD, then LDAC is recognized,
the command specifi ed in the 24-bit word just transferred
is executed and the DAC outputs are updated.
The DAC outputs are powered up when LDAC is taken
low, independent of the state of CS/LD. The integrated
reference is also powered up if it was powered down us-
ing Power-Down Chip (0101b) command. The integrated
reference will not power up when LDAC is taken low, if
it was powered down using Select External Reference
(0111b) Command.
If LDAC is low at the time CS/LD goes high, it inhibits any
software power-down command (Power-Down
n
, Power-
Down Chip, Select External Reference) that was specifi ed
in the input word.
Reference Modes
For applications where an accurate external reference is
not available, the LTC2654 has a user-selectable, inte-
grated reference. The LTC2654-L has a 1.25V reference
that provides a full-scale output of 2.5V. The LTC2654-H
has a 2.048V reference that provides a full-scale output
of 4.096V. Both references exhibit a typical temperature
drift of 2ppm/°C. Internal reference mode can be selected
by using command 0110b, and is the power-on default.
A buffer is needed if the internal reference is required to
drive external circuitry. For reference stability and low
noise, connect a 0.1µF capacitor between REFCOMP and
GND. In this confi guration, the internal reference can drive
up to 0.1µF capacitive load without any stability problems.
In order to ensure stable operation, the capacitive load on
REFIN/OUT pin should not exceed the capacitive load on
the REFCOMP pin.
The DAC can also operate in external reference mode using
command 0111b. In this mode, REFIN/OUT pin acts as an
input that sets the DAC’s reference voltage. The input is
high impedance and does not load the external reference
source. The acceptable voltage range at this pin is 0.5V ≤
REFIN/OUT ≤ VCC/2. The resulting full-scale output voltage
is 2VREFIN/OUT. For using External Reference at start-up,
see the Power Supply Sequencing and Start-Up Section.
LTC2654 L7LJCUEN2
LTC2654
20
2654f
OPERATION
Integrated Reference Buffers
Each of the four DACs in the LTC2654 has its own inte-
grated high performance reference buffer. The buffers have
very high input impedance and do not load the reference
voltage source. These buffers shield the reference voltage
from glitches caused by DAC switching and thus minimize
DAC-to-DAC Dynamic Crosstalk. Typically DAC-to-DAC
crosstalk is less than 3nVs. By tying 0.22µF capacitors
between REFCOMP and GND, and also between REFIN/
OUT and GND, this number can be reduced to less than
1nVs. See the curve DAC-to-DAC Dynamic Crosstalk in
the Typical Performance Characteristics section.
Voltage Outputs
Each of the LTC2654’s four rail-to-rail output amplifi ers con-
tained in these parts has guaranteed load regulation when
sourcing or sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifi ers ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifi ers’ DC output
impedance is 0.04 when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30 typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30 • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifi ers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping signal and
power grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. The REFLO pin should be connected to system
star ground. Resistance from the REFLO pin to system
star ground should be as low as possible.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur in external refer-
ence mode near full-scale when the REFIN/OUT pin is at
VCC/2. If VREFIN/OUT = VCC/2 and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits
at VCC as shown in Figure 3c. No full-scale limiting can
occur if VREFIN/OUT ≤ (VCC – FSE)/2.
Offset and linearity are defi ned and tested over the region
of the DAC transfer function where no output limiting can
occur.
LTC2654 L7 LJUW
LTC2654
21
2654f
OPERATION
Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of
Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
2654 F04
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
0V 32,7680 4,095
INPUT CODE
OUTPUT
VOLTAGE
(a)
VREF = VCC
VREF = VCC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
[IC2654 IDDDDDDDDT’ ‘DDDDDDQQL T7 {:H«4447 f fifififififififi QEQEQQQQ L7LJCUEN2
LTC2654
22
2654f
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC2654 SED PAD / ft L7 LJUW
LTC2654
23
2654f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710)
4.00 ± 0.10
4.00 ± 0.10
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2019
1
2
BOTTOM VIEW—EXPOSED PAD
2.00 REF
2.45 ± 0.10
0.75 ± 0.05 R = 0.115
TYP
R = 0.05
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF20) QFN 01-07 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.00 REF 2.45 ± 0.05
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
2.45 ± 0.10
2.45 ± 0.05
LTC2654 L7LJCUEN2
LTC2654
24
2654f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 0310 • PRINTED IN USA
TYPICAL APPLICATION
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LTC1664 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821 Single 16-Bit VOUT DAC with ±1LSB INL, DNL Parallel Interface, Precision 16-Bit Settling in 2s for 10V Step
LTC2656 Octal 16-/12-Bit VOUT DACs 325A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
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LTC2601/LTC2611/
LTC2621
Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2602/LTC2612/
LTC2622
Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2604/LTC2614/
LTC2624
Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250A per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2605/LTC2615/
LTC2625
Octal 16-/14-/12-Bit VOUT DACs with I2C Interface 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output
LTC2606/LTC2616/
LTC2626
Single 16-/14-/12-Bit VOUT DACs with I2C Interface 270A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output
LTC2609/LTC2619/
LTC2629
Quad 16-/14-/12-Bit VOUT DACs with I2C Interface 250A per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with
Separate VREF Pins for Each DAC
LTC2634 Quad 12-/10-/8-Bit VOUT DACs with 10ppm/°C (Typical)
Reference
125µA per DAC, 2.7V to 5.5V Supply Range,
Internal 1.25V or 2.048V Reference, Rail-to-Rail Output, SPI Interface
LTC2636 Octal 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference 125A per DAC, 2.7V to 5.5V Supply Range,
Internal 1.25V or 2.048V Reference, Rail-to-Rail Output, SPI Interface
LTC2641/LTC2642 Single 16-/14-/12-Bit VOUT DACs with ±1LSB INL, DNL ±1LSB (Max) INL, DNL, 3mm × 3mm DFN and MSOP Packages,
120A Supply Current, SPI Interface
LTC2704 Quad 16-/14-/12-Bit VOUT DACs with ±2LSB INL,
±1LSB DNL
Software Programmable Output Ranges Up to ±10V, SPI Interface
LTC2754 Quad 16-/14-/12-Bit SPI IOUT DACs with ±1LSB INL,
±1LSB DNL
Software Programmable Output Ranges Up to ±10V SPI Interface
LTC2755 Quad 16-/14-/12-Bit IOUT DACs with ±1LSB INL,
±1LSB DNL
Software Programmable Output Ranges Up to ±10V, Parallel Interface
True Rail-to-Rail Output DAC
2654 TA02
LTC2654
VCC REFCOMP REFIN/OUT LDAC PORSEL CLR
GND GND DNC
C1
0.1µF
DNC DNC DNCREFLO
CS/LD
SCK
SDI
SDO
VOUTA
VOUTB
VOUTC
VOUTD
C2
0.1µF
C3
0.1µF
D1
BAS70
18
19 21 8 17 16 1520
PIN NUMBERS
SHOWN ARE FOR
THE QFN PACKAGE.
PINS 5, 6, 7, 9, 11
TIE TO DIGITAL
CONTROL LINES
2451211
R2
10k
–5V
5V
1
3
13
14
6
7
9
10

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