CAT24C128 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2013
May, 2018 Rev. 16
1Publication Order Number:
CAT24C128/D
CAT24C128
EEPROM Serial 128-Kb I2C
Description
The CAT24C128 is a EEPROM Serial 128Kb I2C internally
organized as 16,384 words of 8 bits each.
It features a 64byte page write buffer and supports both the
Standard (100 kHz), Fast (400 kHz) and FastPlus (1 MHz) I2C
protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
OnChip ECC (Error Correction Code) makes the device suitable
for high reliability applications.*
Features
Supports Standard, Fast and FastPlus I2C Protocol
1.8 V to 5.5 V Supply Voltage Range
64Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
This Device is PbFree, Halogen Free/BFR Free and RoHS
Compliant**
Figure 1. Functional Symbol
SDA
SCL
WP
CAT24C128
VCC
VSS
A2, A1, A0
** For additional information on our PbFree strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
www.onsemi.com
PIN CONFIGURATION
SDA
WP
VCC
VSS
A2
A1
A0
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SOIC8
W SUFFIX
CASE 751BD
SCL
SOIC (W), TSSOP (Y), UDFN (HU4)
TSSOP8
Y SUFFIX
CASE 948AL
Device Address InputsA0, A1, A2
Serial Data Input/OutputSDA
Serial Clock InputSCL
Write Protect InputWP
Power SupplyVCC
GroundVSS
FunctionPin Name
PIN FUNCTION
For the location of Pin 1, please consult the
corresponding package drawing.
UDFN8
HU4 SUFFIX
CASE 517AZ
The exposed pad for the TDFN/UDFN packages can
be left floating or connected to Ground.
SOIC8 WIDE
X SUFFIX
CASE 751BE
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Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Units
Storage Temperature 65 to +150 °C
Voltage on Any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than 0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than 1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
NEND (Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles
TDR Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C
4. The new product revision (C) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when
a single byte has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes in order
to benefit from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS Mature Product (Rev B)
(VCC = 1.8 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 1 mA
ICCW Write Current Write, fSCL = 400 kHz 3 mA
ISB Standby Current All I/O Pins at GND or VCC TA = 40°C to +85°C 1 mA
TA = 40°C to +125°C 2
ILI/O Pin Leakage Pin at GND or VCC TA = 40°C to +85°C 1 mA
TA = 40°C to +125°C 2
VIL Input Low Voltage 0.5 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage VCC 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V
Table 4. PIN IMPEDANCE CHARACTERISTICS Mature Product (Rev B)
(VCC = 1.8 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 5) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN (Note 5) Input Capacitance (other pins) VIN = 0 V 6 pF
IWP (Note 6) WP Input Current VIN < VIH 200 mA
VIN > VIH 1mA
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pulldown is relatively strong;
therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pulldown reverts to a weak current source.
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Table 5. D.C. OPERATING CHARACTERISTICS New Product (Rev C) (Note 7)
(VCC = 1.8 V to 5.5 V, TA = 40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specified.)
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz/1 MHz 1 mA
ICCW Write Current 3 mA
ISB Standby Current All I/O Pins at GND or VCC TA = 40°C to +85°C 2 mA
TA = 40°C to +125°C 5
ILI/O Pin Leakage Pin at GND or VCC TA = 40°C to +85°C 1 mA
TA = 40°C to +125°C 2
VIL1 Input Low Voltage 2.5 V VCC 5.5 V 0.5 0.3 VCC V
VIL2 Input Low Voltage 1.8 V VCC < 2.5 V 0.5 0.25 VCC V
VIH1 Input High Voltage 2.5 V VCC 5.5 V 0.7 VCC VCC + 0.5 V
VIH2 Input High Voltage 1.8 V VCC < 2.5 V 0.75 VCC VCC + 0.5 V
VOL1 Output Low Voltage VCC 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V
Table 6. PIN IMPEDANCE CHARACTERISTICS New Product (Rev C) (Note 7)
(VCC = 1.8 V to 5.5 V, TA = 40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = 40°C to +125°C, unless otherwise specified.)
Symbol Parameter Conditions Max Units
CIN (Note 8) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN (Note 8) Input Capacitance (other pins) VIN = 0 V 6 pF
IWP
, IA (Note 9) WP Input Current, Address Input
Current (A0, A1, A2)
VIN < VIH, VCC = 5.5 V 75 mA
VIN < VIH, VCC = 3.3 V 50
VIN < VIH, VCC = 1.8 V 25
VIN > VIH 2
7. The product Rev C is identified by letter “C” or dedicated marking code on top of the package.
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
9. When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally. For improved noise immunity, the internal pulldown is relatively
strong; therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pulldown reverts to a weak current source.
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Table 7. A.C. CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = 40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = 40°C to +125°C) (Note 10)
Symbol Parameter
Standard
VCC = 1.8 V 5.5 V
Fast
VCC = 1.8 V 5.5 V
FastPlus (Note 13)
VCC = 2.5 V 5.5 V
TA = 405C to +855C
Units
Min Max Min Max Min Max
FSCL Clock Frequency 100 400 1,000 kHz
tHD:STA START Condition Hold Time 4 0.6 0.25 ms
tLOW Low Period of SCL Clock 4.7 1.3 0.45 ms
tHIGH High Period of SCL Clock 4 0.6 0.40 ms
tSU:STA START Condition Setup Time 4.7 0.6 0.25 ms
tHD:DAT Data In Hold Time 000ms
tSU:DAT Data In Setup Time 250 100 50 ns
tR (Note 11) SDA and SCL Rise Time 1,000 300 100 ns
tF (Note 11) SDA and SCL Fall Time 300 300 100 ns
tSU:STO STOP Condition Setup Time 4 0.6 0.25 ms
tBUF Bus Free Time Between
STOP and START
4.7 1.3 0.5 ms
tAA SCL Low to Data Out Valid 3.5 0.9 0.40 ms
tDH Data Out Hold Time 100 100 50 ns
Ti (Note 11) Noise Pulse Filtered at SCL
and SDA Inputs
100 100 50 ns
tSU:WP WP Setup Time 000ms
tHD:WP WP Hold Time 2.5 2.5 1 ms
tWR Write Cycle Time 5 5 5 ms
tPU
(Notes 11, 12)
Power-up to Ready Mode 1 1 0.1 1 ms
10.Test conditions according to “A.C. Test Conditions” table.
11. Tested initially and after a design or process change that affects this parameter.
12.tPU is the delay between the time VCC is stable and the device is ready to accept commands.
13.FastPlus (1 MHz) speed class available for new product revision “C”. The die revision “C” is identified by letter “C” or a dedicated marking
code on top of the package.
Table 8. A.C. TEST CONDITIONS
Input Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times v 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
The last bit, R/W
CAT24C128
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PowerOn Reset (POR)
The CAT24C128 incorporates PowerOn Reset (POR)
circuitry which protects the device against powering up in
the wrong state.
The CAT24C128 will power up into Standby mode after
VCC exceeds the POR trigger level and will power down into
Reset mode when VCC drops below the POR trigger level.
This bidirectional POR feature protects the device against
‘brownout’ failure following a temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
When not driven, these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAT24C128 supports the InterIntegrated Circuit
(I2C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24C128 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A0, A1,
and A2.
I2C Bus Protocol
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pullup
resistors. Master and Slave devices connect to the 2wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wakeup’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A2, A1 and A0, select one of 8 possible Slave
devices and must match the state of the external address pins.
The last bit, R/W, specifies whether a Read (1) or Write (0)
operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge all address bytes and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 2. START/STOP Conditions
1010
DEVICE ADDRESS
Figure 3. Slave Address Bits
A2A1A0R/W
189
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
ACK SETUP ( tSU:DAT)
BUS RELEASE DELAY (RECEIVER
)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 4. Acknowledge Timing
ACK DELAY ( tAA)
SCL
SDA IN
SDA OUT
Figure 5. Bus Timing
tSU:STA
tHD:STA
tHD:DAT
tF
tLOW
tAA
tHIGH
tLOW
tR
tDH tBUF
tSU:DAT tSU:STO
n receiving 2: Slave address wim mo R/W E? % www.cnsemi.com
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Write Operations
Byte Write
Upon receiving a Slave address with the R/W bit set to ‘0’,
the CAT24C128 will interpret the next two bytes as address
bytes. These bytes are used to initialize the internal address
counter; the 2 most significant bits are ‘don’t care’, the next
8 point to one of 256 available pages and the last 6 point to
a location within a 64 byte page. A byte following the
address bytes will be interpreted as data. The data will be
loaded into the Page Write Buffer and will eventually be
written to memory at the address specified by the 14 active
address bits provided earlier. The CAT24C128 will
acknowledge the Slave address, address bytes and data byte.
The Master then starts the internal Write cycle by issuing a
STOP condition (Figure 6). During the internal Write cycle
(tWR), the SDA output will be tristated and additional Read
or Write requests will be ignored (Figure 7).
Page Write
By continuing to load data into the Page Write Buffer after
the 1st data byte and before issuing the STOP condition, up
to 64 bytes can be written simultaneously during one
internal Write cycle (Figure 8). If more data bytes are loaded
than locations available to the end of page, then loading will
continue from the beginning of page, i.e. the page address is
latched and the address count automatically increments to
and then wrapsaround at the page boundary. Previously
loaded data can thus be overwritten by new data. What is
eventually written to memory reflects the latest Page Write
Buffer contents. Only data loaded within the most recent
Page Write sequence will be written to memory.
Acknowledge Polling
The ready/busy status of the CAT24C128 can be
ascertained by sending Read or Write requests immediately
following the STOP condition that initiated the internal
Write cycle. As long as internal Write is in progress, the
CAT24C128 will not acknowledge the Slave address.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C128. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C128 will not acknowledge the data byte
and the Write request will be rejected.
Delivery State
The CAT24C128 is shipped erased, i.e., all bytes are FFh.
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
O
P
P
BUS ACTIVITY:
MASTER
SLAVE
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
BYTE DATA
BYTE
A
C
K
* = Don’t Care Bit
Figure 6. Byte Write Sequence
**
a13a8a7a0
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8th Bit
Byte n
SCL
SDA
Figure 7. Write Cycle Timing
tWR
[Ill—HUI“IllllllllllIllllllllIllllllllllllllM‘lllllllH—F n Icociving 2| Slave address wim ms R/W www.cnsemi.com
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8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SLAVE
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
BYTE
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+P
A
C
K
S
T
O
P
A
C
K
A
C
K
P
A
C
K
* = Don’t Care Bit
P v 63 Figure 8. Page Write Sequence
**
a13a8a7a0
1891 8
ADDRESS
BYTE
DATA
BYTE
SCL
SDA
WP
Figure 9. WP Timing
d0
d7
a7a0
tHD:WP
tSU:WP
Read Operations
Immediate Read
Upon receiving a Slave address with the R/W bit set to ‘1’,
the CAT24C128 will interpret this as a request for data
residing at the current byte address in memory. The
CAT24C128 will acknowledge the Slave address, will
immediately shift out the data residing at the current address,
and will then wait for the Master to respond. If the Master
does not acknowledge the data (NoACK) and then follows
up with a STOP condition (Figure 10), the CAT24C128
returns to Standby mode.
Selective Read
To read data residing at a specific location, the internal
address counter must first be initialized as described under
Byte Write. If rather than following up the two address bytes
with data, the Master instead follows up with an Immediate
Read sequence, then the CAT24C128 will use the 14 active
address bits to initialize the internal address counter and will
shift out data residing at the corresponding location. If the
Master does not acknowledge the data (NoACK) and then
follows up with a STOP condition (Figure 11), the
CAT24C128 returns to Standby mode.
Sequential Read
If during a Read session the Master acknowledges the 1st
data byte, then the CAT24C128 will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure 12).
In contrast to Page Write, during Sequential Read the
address count will automatically increment to and then
wraparound at end of memory (rather than end of page).
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9
SCL
SDA 8th Bit
STOP
NO ACKDATA OUT
8
SLAVE
ADDRESS
S
A
C
K
DATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
Figure 10. Immediate Read Sequence and Timing
9
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SLAVE
S
T
A
R
T
ADDRESS
BYTE
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
S
A
C
K
P
* = Don’t Care Bit
Figure 11. Selective Read Sequence
**
S
T
A
R
T
S
T
O
P
A
C
K
N
O
a13a8a7a0
BUS ACTIVITY:
MASTER
SLAVE DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
A
C
K
A
C
K
A
C
K
S
T
O
P
N
O
A
C
K
A
C
K
P
SLAVE
ADDRESS
Figure 12. Sequential Read Sequence
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ORDERING INFORMATION (Notes 14 thru 17)
Device Order Number
Specific
Device
Marking*
Package
Type Temperature Range Lead Finish Shipping
CAT24C128WIGT3 24128C SOIC8,
JEDEC
I = Industrial
(40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT24C128YIGT3 C28C TSSOP8I = Industrial
(40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
CAT24C128XIT2 TBD SOIC8I = Industrial
(40°C to +85°C)
MatteTin Tape & Reel,
2,000 Units / Reel
CAT24C128HU4IGT3 C7U UDFN8I = Industrial
(40°C to +85°C)
NiPdAu Tape & Reel,
3,000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
14.All packages are RoHScompliant (Leadfree, Halogenfree).
15.The standard lead finish is NiPdAu.
16.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
17.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol.
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UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A DATE 23 MAR 201
5
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
REFERENCE
TOP VIEW
SIDE VIEW
BOTTOM VIEW
L
D2
E2
C
C0.10
C0.08 A1 SEATING
PLANE
NOTE 3
b
8X
0.10 C
0.05 C
AB
DIM MIN MAX
MILLIMETERS
A0.45 0.55
A1 0.00 0.05
b0.20 0.30
D2.00 BSC
D2 1.35 1.45
E3.00 BSC
E2 1.25 1.35
e0.50 BSC
L0.25 0.35
14
8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
PITCH
1.45 3.40
1
DIMENSIONS: MILLIMETERS
1
NOTE 4
0.30
8X
DETAIL A
A3 0.13 REF
A3
A
DETAIL B
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
L1 −−− 0.15
e
RECOMMENDED
5
1.56
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
XXXXX
AWLYWG
1
M
M
0.68
C0.10
8X
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0 Case Outline Number:
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DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON42552E
ON SEMICONDUCTOR STANDARD
UDFN8, 2X3 EXTENDED PAD
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
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REQ. BY B. BECKER. 23 MAR 2015
© Semiconductor Components Industries, LLC, 2015
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:
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
SOIC 8, 150 mils
CASE 751BD01
ISSUE O
DATE 19 DEC 2008
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34272E
ON SEMICONDUCTOR STANDARD
SOIC 8, 150 MILS
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
0N Snmlcondllclol“ 0N Semxcanduclm m J a m mamas havem some
DOCUMENT NUMBER:
98AON34272E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #SOIC800201 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
© Semiconductor Components Industries, LLC, 2008
December, 2008 Rev. 01O
Case Outline Number:
751BD
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
El 9‘5
TSSOP8, 4.4x3
CASE 948AL01
ISSUE O
DATE 19 DEC 2008
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
0º 8º
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34428E
ON SEMICONDUCTOR STANDARD
TSSOP8, 4.4X3
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
0N Snmlcondllclol“ 0N Semxcanduclm m J a m mamas havem some
DOCUMENT NUMBER:
98AON34428E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #TSSOP800401 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
© Semiconductor Components Industries, LLC, 2008
December, 2008 Rev. 01O
Case Outline Number:
948AL
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
SOIC8, 208 mils
CASE 751BE01
ISSUE O
DATE 19 DEC 2008
E1
eb
SIDE VIEW
TOP VIEW
E
D
PIN#1 IDENTIFICATION
END VIEW
A1
A
Lc
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
q
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
0º 8º
0.05
0.36
0.19
5.13
7.75
5.13
1.27 BSC
2.03
0.25
0.48
0.25
5.33
8.26
5.38
L0.51 0.76
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON34273E
ON SEMICONDUCTOR STANDARD
SOIC8, 208 MILS
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
0N Snmlcondllclol“ 0N Semxcanduclm m J a m mamas havem some
DOCUMENT NUMBER:
98AON34273E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION FROM POD #SOIK803101 TO ON
SEMICONDUCTOR. REQ. BY B. BERGMAN.
19 DEC 2008
© Semiconductor Components Industries, LLC, 2008
December, 2008 Rev. 01O
Case Outline Number:
751BE
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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