MCP6071,72,74 Datasheet by Microchip Technology

View All Related Products | Download PDF Datasheet
MCP6071I2I4 MICROCHIP aEEs MEEMEEE 1EE4 aEEs EEEEEEE ‘EE4
© 2010 Microchip Technology Inc. DS22142B-page 1
MCP6071/2/4
Features
Low Offset Voltage: ±150 µV (maximum)
Low Quiescent Current: 110 µA (typical)
Rail-to-Rail Input and Output
Wide Supply Voltage Range: 1.8V to 6.0V
Gain Bandwidth Product: 1.2 MHz (typical)
Unity Gain Stable
Extended Temperature Range: -40°C to +125°C
No Phase Reversal
Applications
• Automotive
Portable Instrumentation
Sensor Conditioning
Battery Powered Systems
Medical Instrumentation
Test Equipment
Analog Filters
Design Aids
SPICE Macro Models
•FilterLab
® Software
MAPS (Microchip Advanced Part Selector)
Analog Demonstration and Evaluation Boards
Application Notes
Typical Application
Description
The Microchip Technology Inc. MCP6071/2/4 family of
operational amplifiers (op amps) has low input offset
voltage (±150 µV, maximum) and rail-to-rail input and
output operation. This family is unity gain stable and
has a gain bandwidth product of 1.2 MHz (typical).
These devices operate with a single supply voltage as
low as 1.8V, while drawing low quiescent current per
amplifier (110 µA, typical). These features make the
family of op amps well suited for single-supply, high
precision, battery-powered applications.
The MCP6071/2/4 family is offered in single
(MCP6071), dual (MCP6072), and quad (MCP6074)
configurations.
The MCP6071/2/4 is designed with Microchip’s
advanced CMOS process. All devices are available in
the extended temperature range, with a power supply
range of 1.8V to 6.0V.
Package Types
RL
VOUT
Gyrator
ZIN
R
C
ZIN RLjωL+=
LR
LRC=
MCP6071
* Includes Exposed Thermal Pad (EP); see Table 3-1.
1
2
3
4
8
7
6
5
EP
9
VDD
VOUT
NC
NC
VIN+
VIN
VSS
NC 1
2
3
4
8
7
6
5
EP
9
VOUTB
VINB
VINB+
VDD
VINA+
VINA
VSS
VOUTA
VINA+
VINA
VDD
1
2
3
4
14
13
12
11
VOUTA VOUTD
VIND
VIND+
VSS
VINB+510 VINC+
VINB69
VOUTB 7 8 VOUTC
VINC
VINA+
VINA
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB
VINB+
VIN+
VIN
VSS
1
2
3
4
8
7
6
5
NC NC
VDD
VOUT
NC
MCP6071
SOIC
MCP6071
2x3 TDFN
MCP6072
2x3 TDFN
MCP6072
SOIC
MCP6074
SOIC, TSSOP
VIN+VIN
VSS
1
2
3
5
4
VDD
VOUT
MCP6071
SOT-23-5
110 µA, High Precision Op Amps
MCP6071/2/4
DS22142B-page 2 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS22142B-page 3
MCP6071/2/4
1.0 ELECTRICAL CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Input Pins .....................................................±2 mA
Analog Inputs (VIN+, VIN-)†† .......... VSS 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short-Circuit Current .................................continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other conditions
above those indicated in the operational listings of this
specification is not implied. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
†† See 4.1.2 “Input Voltage Limits”
1.2 Specifications
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25°C, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -150 +150 µV VDD = 3.0V,
VCM = VDD/3
Input Offset Drift with Temperature ΔVOS/ΔTA—±1.5µV/°CT
A= -40°C to +85°C,
VDD = 3.0V, VCM = VDD/3
ΔVOS/ΔTA—±4.0µV/°CT
A= +85°C to +125°C,
VDD = 3.0V, VCM = VDD/3
Power Supply Rejection Ratio PSRR 70 87 dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB ±1.0 100 pA
IB—60pAT
A = +85°C
IB 1100 5000 pA TA = +125°C
Input Offset Current IOS — ±1.0 pA
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||6 — Ω||pF
Common Mode
Common Mode Input Voltage Range VCMR VSS0.15 — VDD+0.15 V VDD = 1.8V (Note 1)
VCMR VSS0.3 — VDD+0.3 V VDD = 6.0V (Note 1)
Common Mode Rejection Ratio CMRR 72 89 dB VCM = -0.15V to 1.95V,
VDD = 1.8V
74 91 dB VCM = -0.3V to 6.3V,
VDD = 6.0V
72 87 dB VCM = 3.0V to 6.3V,
VDD = 6.0V
74 89 dB VCM = -0.3V to 3.0V,
VDD = 6.0V
Note 1: Figure 2-13 shows how VCMR changed across temperature.
MCP6071/2/4
DS22142B-page 4 © 2010 Microchip Technology Inc.
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
TABLE 1-3: TEMPERATURE SPECIFICATIONS
Open-Loop Gain
DC Open-Loop Gain
(Large Signal) AOL 95 115 dB 0.2V < VOUT <(VDD-0.2V)
VCM = VSS
Output
Maximum Output Voltage Swing VOL, VOH VSS+15 — VDD–15 mV 0.5V input overdrive
Output Short-Circuit Current ISC —±7mAV
DD = 1.8V
—±28mAV
DD = 6.0V
Power Supply
Supply Voltage VDD 1.8 6.0 V
Quiescent Current per Amplifier IQ50 110 170 µA IO = 0, VDD = 6.0V
VCM = 0.9VDD
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to +6.0V, VSS = GND, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP 1.2 MHz
Phase Margin PM 57 ° G = +1 V/V
Slew Rate SR 0.5 V/µs
Noise
Input Noise Voltage Eni 4.3 µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —19nV/Hz f = 10 kHz
Input Noise Current Density ini —0.6fA/Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 +125 °C Note 1
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 220.7 — °C/W
Thermal Resistance, 8L-2x3 TDFN θJA —52.5°C/W
Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W
Thermal Resistance, 14L-SOIC θJA 95.3 °C/W
Thermal Resistance, 14L-TSSOP θJA 100 °C/W
Note 1: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +6.0V, VSS= GND, TA= +25°C, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2 and RL = 10 kΩ to VL. (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
Note 1: Figure 2-13 shows how VCMR changed across temperature.
gfl—h‘ 4% i E H/w (H
© 2010 Microchip Technology Inc. DS22142B-page 5
MCP6071/2/4
1.3 Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-1. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s common mode voltage ((VP+V
M)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
EQUATION 1-1:
FIGURE 1-1: AC and DC Test Circuit for
Most Specifications.
GDM RFRG
=
VCM VPVDD 2+()2=
VOUT VDD 2()VPVM
()VOST 1GDM
+()++=
Where:
GDM = Differential Mode Gain (V/V)
VCM = Op Amp’s Common Mode
Input Voltage (V)
VOST = Op Amp’s Total Input Offset
Voltage (mV)
VOST VINVIN+
=
VDD
RGRF
VOUT
VM
CB2
CL
RL
VL
CB1
100 kΩ
100 kΩ
RGRF
VDD/2
VP
100 kΩ
100 kΩ
60 pF10 kΩ
F100 nF
VIN–
VIN+
CF
6.8 pF
CF
6.8 pF
MCP607X
MCP6071/2/4
DS22142B-page 6 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS22142B-page 7
MCP6071/2/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
FIGURE 2-1: Input Offset Voltage with
VDD = 3.0V.
FIGURE 2-2: Input Offset Voltage Drift
with VDD = 3.0V and TA
+85°C.
FIGURE 2-3: Input Offset Voltage Drift
with VDD = 3.0V and TA
+85°C.
FIGURE 2-4: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 6.0V.
FIGURE 2-5: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 3.0V.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 1.8V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
-150
-120
-90
-60
-30
0
30
60
90
120
150
Input Offset Voltage (µV)
Percentage of Occurences
1244 Samples
V
DD = 3.0V
V
CM = VDD /3
0%
3%
6%
9%
12%
15%
18%
21%
24%
27%
-20
-16
-12
-8
-4
0
4
8
12
16
20
Input Offset Drift with Temperature (µV/°C)
Percentage of Occurences
1244 Samples
VDD = 3.0V
VCM = VDD/3
TA = -40°C to +85°C
0%
3%
6%
9%
12%
15%
18%
21%
24%
27%
-20
-16
-12
-8
-4
0
4
8
12
16
20
Input Offset Drift with Temperature (µV/°C)
Percentage of Occurences
1244 Samples
VDD = 3.0V
VCM = VDD
/
3
TA = +85°C to +125°C
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
VDD = 6.0V Representative Part
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.5
-0.2
0.1
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
3.1
3.4
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
TA = -40°C
TA = +2C
TA = +8C
TA = +125°C
VDD = 3.0V Representative Part
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 1.8V Representative Part
TA = -40°C
TA = +2C
TA = +8C
TA = +125°C
Fvequency (ny Fvequency 1H1)
MCP6071/2/4
DS22142B-page 8 © 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
FIGURE 2-7: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-8: Input Offset Voltage vs.
Power Supply Voltage.
FIGURE 2-9: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-10: Input Noise Voltage Density
vs. Common Mode Input Voltage.
FIGURE 2-11: CMRR, PSRR vs.
Frequency.
FIGURE 2-12: CMRR, PSRR vs. Ambient
Temperature.
-350
-250
-150
-50
50
150
250
350
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 6.0V
VDD = 1.8V
VDD = 3.0V
Representative Part
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Input Offset Voltage (µV)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
Representative Part
10
100
1,000
1.E-1 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 1.E+5
Frequency (Hz)
Input Noise Voltage Density
(nV/Hz)
0.1 1 10 100 1k 10k 100k
0
5
10
15
20
25
30
35
40
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/Hz)
f = 10 kHz
VDD = 6.0V
20
30
40
50
60
70
80
90
100
110
10 100 1000 10000 100000 1000000
Frequency (Hz)
CMRR, PSRR (dB)
Representative Part
CMRR
PSRR+
PSRR-
10 100 1k 10k 100k 1M
60
65
70
75
80
85
90
95
100
105
110
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR (VDD = 1.8V to 6.0V, VCM = VSS)
CMRR (VDD = 6.0V, VCM = -0.3V to 6.3V)
-2o n.1 1 1n 1on 1k 1nk 100k 1M
© 2010 Microchip Technology Inc. DS22142B-page 9
MCP6071/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
FIGURE 2-13: Common Mode Input
Voltage Range Limit vs. Ambient Temperature.
FIGURE 2-14: Input Bias, Offset Currents
vs. Ambient Temperature.
FIGURE 2-15: Input Bias Current vs.
Common Mode Input Voltage.
FIGURE 2-16: Quiescent Current vs
Ambient Temperature with VCM = 0.9VDD.
FIGURE 2-17: Quiescent Current vs.
Power Supply Voltage with VCM = 0.9VDD.
FIGURE 2-18: Open-Loop Gain, Phase vs.
Frequency.
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
-50-25 0 255075100125
Ambient Temperature (°C)
Common Mode Input Voltage
Range Limit (V)
VCMR_L - VSS @ VDD = 1.8
V
VOL - VSS @ VDD = 3.0
V
VOL - VSS @ VDD = 6.0
V
VCMR_H - VDD @ VDD = 6.0V
@ VDD = 3.0V
@ VDD = 1.8V
1
10
100
1000
10000
25 45 65 85 105 125
Ambient Temperature (°C)
Input Bias and Offset
Currents (pA)
VDD = 6.0V
VCM = VDD
Input Bias Current
Input Offset Current
1
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Votlage (V)
Input Bias Current (pA)
VDD = 6.0V
TA = +125°C
TA = +85°C
60
70
80
90
100
110
120
130
140
150
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Quiescent Current
(µA/Amplifier)
VDD = 6.0V
VCM = 0.9VDD
VDD = 1.8V
VCM = 0.9VDD
0
20
40
60
80
100
120
140
160
180
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
Power Supply Voltage (V)
Quiescent Current
(µA/Amplifier)
VDD = 6.0V
VCM = 0.9VDD
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Open-Loop Gain
Open-Loop Phase
VDD = 6.0V
0.1 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
MCP6071/2/4
DS22142B-page 10 © 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
FIGURE 2-19: DC Open-Loop Gain vs.
Power Supply Voltage.
FIGURE 2-20: DC Open-Loop Gain vs.
Output Voltage Headroom.
FIGURE 2-21: Channel-to-Channel
Separation vs. Frequency ( MCP6072/4 only).
FIGURE 2-22: Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
FIGURE 2-23: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-24: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
100
105
110
115
120
125
130
135
140
145
150
1.52.02.53.03.54.04.55.05.56.0
Power Supply Voltage (V)
DC-Open-Loop Gain (dB)
RL = 10 k
VSS + 0.2V < VOUT < VDD - 0.2V
100
105
110
115
120
125
130
135
140
145
150
0.00 0.05 0.10 0.15 0.20 0.25
Output Voltage Headroom
VDD - VOH or VOL - VSS (V)
DC-Open-Loop Gain (dB)
VDD = 6.0V
VDD = 1.8V
Large Signal AOL
80
90
100
110
120
130
140
150
1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06
Frequency (Hz)
Channel to Channel
Separation (dB)
Input Referred
100 1k 10k 100k 1M
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Common Mode Input Voltage (V)
Gain Bandwidth Product
(MHz)
0
20
40
60
80
100
120
140
160
180
Phase Margin (°)
Phase Margin
Gain Bandwidth Product
VDD = 6.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
0
20
40
60
80
100
120
140
160
180
Phase Margin (°)
Gain Bandwidth Product
Phase MarginVDD = 6.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50-25 0 255075100125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
0
20
40
60
80
100
120
140
160
180
Phase Margin (°)
Gain Bandwidth Product
Phase Margin
VDD = 1.8V
© 2010 Microchip Technology Inc. DS22142B-page 11
MCP6071/2/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
FIGURE 2-25: Ouput Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-26: Output Voltage Swing vs.
Frequency.
FIGURE 2-27: Ratio of Output Voltage
Headroom to Output Current vs. Output Current.
FIGURE 2-28: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-29: Slew Rate vs. Ambient
Temperature.
FIGURE 2-30: Small Signal Non-Inverting
Pulse Response.
0
5
10
15
20
25
30
35
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Power Supply Voltage (V)
Output Short Circuit Current
(mA)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0.1
1
10
1000 10000 100000 1000000
Frequency (Hz)
Output Voltage Swing (VP-P)
VDD = 1.8V
VDD = 6.0V
1k 10k 100k 1M
0
5
10
15
20
25
30
35
40
45
50
55
60
0.1 1 10
Output Current (mA)
Ratio of Output Headroom to
Current (mV/mA)
(VOL - VSS)/(-IOUT)
(VDD - VOH)/IOUT VDD = 1.8V
(VDD - VOH)/IOUT
(VOL - VSS)/(-IOUT)
VDD = 6.0V
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
-50-25 0 255075100125
Ambient Temperature (°C)
Output Voltage Headroom
VDD - VOH or VOL - VSS (mV)
VDD - VOH
VOL - VSS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50-25 0 255075100125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling Edge, VDD = 6.0V
Falling Edge, VDD = 1.8V
Rising Edge, VDD = 6.0V
Rising Edge, VDD = 1.8V
Time (2 µs/div)
Output Voltage (50 mV/div)
VDD = 6.0V
G = +1 V/V
Fvequency (H1)
MCP6071/2/4
DS22142B-page 12 © 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +6.0V, VSS = GND, VCM = VDD/2, VOUT VDD/2,
VL = VDD/2, RL = 10 kΩ to VL and CL = 60 pF.
FIGURE 2-31: Small Signal Inverting Pulse
Response.
FIGURE 2-32: Large Signal Non-Inverting
Pulse Response.
FIGURE 2-33: Large Signal Inverting Pulse
Response.
FIGURE 2-34: The MCP6071/2/4 Shows
No Phase Reversal.
FIGURE 2-35: Closed Loop Output
Impedance vs. Frequency.
FIGURE 2-36: Measured Input Current vs.
Input Voltage (below VSS).
Time (2 µs/div)
Output Voltage (50 mV/div)
VDD = 6.0V
G = -1 V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Time (0.02 ms/div)
Output Voltage (V)
VDD = 6.0V
G = +1 V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Time (0.02 ms/div)
Output Voltage (V)
VDD = 6.0V
G = -1 V/V
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Time (0.1 ms/div)
Output Voltage (V)
VDD = 6.0V
G = +2 V/V
VOUT
VIN
1
10
100
1000
10 100 1000 10000 100000 1000000
Frequency (Hz)
Closed Loop Output
Impedance ()
GN:
101 V/V
11 V/V
1 V/V
10 100 1k 10k 100k 1M
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VIN (V)
-IIN (A)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
1m
100
µ
10
µ
1
µ
100n
10n
1n
100
10
p
1p
om Voum IN VINA \N VINA DD
© 2010 Microchip Technology Inc. DS22142B-page 13
MCP6071/2/4
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 Power Supply Pins
The positive power supply (VDD) is 1.8V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4 Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
MCP6071 MCP6072 MCP6074
Symbol Description
SOIC SOT-23-5 2x3 TDFN SOIC 2x3 TDFN SOIC,
TSSOP
61 611 1V
OUT, VOUTA Analog Output (op amp A)
24 222 2V
IN–, VINA Inverting Input (op amp A)
33 333 3V
IN+, VINA+ Non-inverting Input (op amp A)
75 788 4 V
DD Positive Power Supply
—— — 5 5 5 V
INB+ Non-inverting Input (op amp B)
—— — 6 6 6 VINBInverting Input (op amp B)
—— — 7 7 7 V
OUTB Analog Output (op amp B)
—— —— 8 V
OUTC Analog Output (op amp C)
—— —— 9 V
INC Inverting Input (op amp C)
—— ——— 10 V
INC+ Non-inverting Input (op amp C)
42 444 11 V
SS Negative Power Supply
—— ——— 12 V
IND+ Non-inverting Input (op amp D)
—— ——— 13 V
IND Inverting Input (op amp D)
—— —— 14 V
OUTD Analog Output (op amp D)
1, 5, 8 1, 5, 8 NC No Internal Connection
9 9 EP Exposed Thermal Pad (EP); must
be connected to VSS.
MCP6071/2/4
DS22142B-page 14 © 2010 Microchip Technology Inc.
NOTES:
© 2010 Microchip Technology Inc. DS22142B-page 15
MCP6071/2/4
4.0 APPLICATION INFORMATION
The MCP6071/2/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-power, high precision
applications.
4.1 Rail-to-Rail Input
4.1.1 PHASE REVERSAL
The MCP6071/2/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-34 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings †).
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize input bias
current (IB).
FIGURE 4-1: Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go well above VDD; their break-
down voltage is high enough to allow normal operation,
but not low enough to protect against slow over-voltage
(beyond VDD) events. Very fast ESD events (that meet
the spec) are limited so that damage does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs.
Figure 4-2 shows one approach to protecting these
inputs.
FIGURE 4-2: Protecting the Analog
Inputs.
A significant amount of current can flow out of the
inputs when the Common Mode voltage (VCM) is below
ground (VSS). See Figure 2-36.
4.1.3 INPUT CURRENT LIMITS
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings †).
Figure 4-3 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible cur-
rents in or out of the input pins (and the ESD diodes, D1
and D2). The diode currents will go through either VDD
or VSS.
FIGURE 4-3: Protecting the Analog
Inputs.
4.1.4 NORMAL OPERATION
The input stage of the MCP6071/2/4 op amps use two
differential input stages in parallel. One operates at a
low common mode input voltage (VCM), while the other
operates at a high VCM. With this topology, the device
operates with a VCM up to 300 mV above VDD and
300 mV below VSS. (See Figure 2-13). The input offset
voltage is measured at VCM = VSS –0.3V and
VDD + 0.3V to ensure proper operation.
The transition between the input stages occurs when
VCM is near VDD –1.1V (See Figures 2-4,2-5 and
Figure 2-6). For the best distortion performance and
gain linearity, with non-inverting gains, avoid this region
of operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN
V1
VDD
D1
V2
D2
MCP607X VOUT
U1
V1R1
VDD
D1
min(R1,R2)>VSS –min (V
1,V2)
2mA
min(R1,R2)>max(V1,V2)–V
DD
2mA
V2R2
D2
MCP607X
VOUT
U1
MCP6071/2/4
DS22142B-page 16 © 2010 Microchip Technology Inc.
4.2 Rail-to-Rail Output
The output voltage range of the MCP6071/2/4 op amps
is VSS + 15 mV (minimum) and VDD15 mV
(maximum) when RL=10kΩ is connected to VDD/2
and VDD = 6.0V. Refer to Figures 2-27 and 2-28 for
more information.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, all gains show the same
general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitance load.
FIGURE 4-4: Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5: Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and
simulations with the MCP6071/2/4 SPICE macro
model are very helpful.
4.4 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
4.5 Unused Op Amps
An unused op amp in a quad package (MCP6074)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuit A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-6: Unused Op Amps.
VIN
RISO
VOUT
MCP607X
CL
+
1
10
100
1000
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Normalized Load Capacitance; CL/GN (F)
Recommended R ISO ()
GN:
1 V/V
2 V/V
5 V/V
VDD = 6.0 V
RL = 10 k
10p 100p 1n 10n 0.1µ
VDD
VDD
¼ MCP6074 (A) ¼ MCP6074 (B)
R1
R2
VDD
VREF
VREF VDD
R2
R1R2
+
--------------------
×
=
3 MM,
© 2010 Microchip Technology Inc. DS22142B-page 17
MCP6071/2/4
4.6 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow; which is greater than the
MCP6071/2/4 family’s bias current at +25°C (±1.0 pA,
typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
FIGURE 4-7: Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity-Gain Buffer:
a.Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b.Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Transimpedance Gain
Amplifiers (convert current to voltage, such as
photo detectors):
a.Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b.Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
Guard Ring VIN–V
IN+ VSS
MCP6071/2/4
DS22142B-page 18 © 2010 Microchip Technology Inc.
4.7 Application Circuits
4.7.1 GYRATOR
The MCP6071/2/4 op amps can be used in gyrator
applications. The gyrator is an electric circuit which can
make a capacitive circuit behave inductively.
Figure 4-8 shows an example of a gyrator simulating
inductance, with an approximately equivalent circuit
below. The two ZIN have similar values in typical
applications. The primary application for a gyrator is to
reduce the size and cost of a system by removing the
need for bulky, heavy and expensive inductors. For
example, RLC bandpass filter characteristics can be
realized with capacitors, resistors and operational
amplifiers without using inductors. Moreover, gyrators
will typically have higher accuracy than real inductors,
due to the lower cost of precision capacitors than
inductors.
.
FIGURE 4-8: Gyrator.
4.7.2 INSTRUMENTATION AMPLIFIER
The MCP6071/2/4 op amps are well suited for
conditioning sensor signals in battery-powered
applications. Figure 4-9 shows a two op amp
instrumentation amplifier, using the MCP6072, that
works well for applications requiring rejection of
common mode noise at higher gains. The reference
voltage (VREF) is supplied by a low impedance source.
In single supply applications, VREF is typically VDD/2.
FIGURE 4-9: Two Op Amp
Instrumentation Amplifier.
To obtain the best CMRR possible, and not limit the
performance by the resistor tolerances, set a high gain
with the RG resistor.
4.7.3 PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s input offset performance. Figure 4-10 shows a
gain of 11 V/V placed before a comparator. The
reference voltage VREF can be any value between the
supply rails.
FIGURE 4-10: Precision, Non-inverting
Comparator.
MCP6071
RL
VOUT
Gyrator
ZIN
R
C
ZIN RLjωL+=
LR
LRC=
RL
L
ZIN
Equivalent Circuit
VOUT V1V2
()1R1
R2
------2R1
RG
---------++
⎝⎠
⎛⎞
VREF
+=
VREF R1R2R2R1VOUT
RG
V2
V1
½
MCP6072
½
MCP6072
VIN
1MΩVOUT
MCP6071
100 kΩMCP6541
VREF
© 2010 Microchip Technology Inc. DS22142B-page 19
MCP6071/2/4
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6071/2/4 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP6071/2/4
op amps is available on the Microchip web site at
www.microchip.com. The model was written and tested
in official Orcad (Cadence) owned PSPICE. For the
other simulators, it may require translation.
The model covers a wide aspect of the op amp's
electrical specifications. Not only does the model cover
voltage, current, and resistance of the op amp, but it
also covers the temperature and noise effects on the
behavior of the op amp. The model has not been
verified outside of the specification range listed in the
op amp data sheet. The model behaviors under these
conditions can not be guaranteed that it will match the
actual op amp performance.
Moreover, the model is intended to be an initial design
tool. Bench testing is a very important part of any
design and cannot be replaced with simulations. Also,
simulation results using this macro model need to be
validated by comparing them to the data sheet
specifications and characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data Sheets,
purchase, and sampling of Microchip parts.
5.4 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Some boards that are especially useful are:
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
5/6-Pin SOT-23 Evaluation Board, P/N VSUPEV2
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5.5 Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip. com/appnotes and are
recommended as supplemental reference resources.
ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
AN1332: “Current Sensing Circuit Concepts and
Fundamentals”, DS01332
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MCP6071/2/4
DS22142B-page 20 © 2010 Microchip Technology Inc.
NOTES:
HHHH UUUU NNN
© 2010 Microchip Technology Inc. DS22142B-page 21
MCP6071/2/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
8-Lead SOIC (150 mil) (MCP6071, MCP6072) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6071E
SN^^ 1044
256
3
e
Example:
AHE
044
25
8-Lead 2x3 TDFN (MCP6071, MCP6072)
XXX
YWW
NN
5-Lead SOT-23 (MCP6071)
XXNN
Example:
YH25
H H H H H H H H H H H H H H O 59 Ofi‘ H H H H H H H HHHHHHH Q? C‘ MUM H H H H H H H HHHHHHH 19 (D UUUUUUU
MCP6071/2/4
DS22142B-page 22 © 2010 Microchip Technology Inc.
Package Marking Information (Continuation)
14-Lead TSSOP (MCP6074)Example:
14-Lead SOIC (150 mil) (MCP6074)Example:
XXXXXXXXXXX
YYWWNNN
XXXXXXXX
YYWW
NNN
MCP6074E
1044
256
XXXXXXXXXXX MCP6074
1044256
E/SL
3
e
© 2010 Microchip Technology Inc. DS22142B-page 23
MCP6071/2/4


 
 
 
 

 
   
  
  
  
   
   
   
   
   
   
   
   
   
   
   
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
   
5-Lead Plastic Small Outline Transistor (OT) [SOT-23] SiLKg SCREEN <><—» gx="" e="" recommended="" land="" pattern="" units="" mlllimeters="" dimensmn="" limils="" mn="" |="" nom="" |="" max="" coniaci="" pitch="" e="" a="" 95="" asc="" conlacl="" pad="" spacing="" c="" 2="" so="" coniaci="" pad="" wmm="" (x5)="" x="" n="" so="" caniaci="" pad="" lenglh="" (x5)="" y="" 1="" m="" dislance="" eelween="" fads="" g="" 1="" 70="" dislance="" eelween="" pads="" gx="" u="" 35="" overall="" width="" z="" 3="" 90="" noies="" i.="" dimensionmg="" and="" lolerancmg="" per="" asme="" y14.5m="" bsc:="" basic="" dimension="" theoretically="" exact="" value="" shown="" wllhoul="" loleiances.="" mlcrcchlp="" technology="" drawing="" no="" c04r2091a="">
MCP6071/2/4
DS22142B-page 24 © 2010 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] EM- i—T—E SEATING PLANE A17 SIDEVIEW A‘— Lr A : \,L \/J Mlcmchlp Technology Drawlng Nu (204-0570 Sheet 1 of 2
© 2010 Microchip Technology Inc. DS22142B-page 25
MCP6071/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
B-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Unlls MILLlMETERS Dimenslan Limils MIN l NOM l MAX Number a! Plus N B Pitch 6! 1 27 BSC Overall Helghl A - - 1 75 Molded Package Thickness A2 1 25 - - Slandufl § A1 0 10 - 0 25 Overall Wldth E 6 00 BSC Molded Package Wldth El 3 90 BSC Overall Length D 4 90 BSC Chamler (Ophohal) h D 25 , 0 50 Foot Length L 0.40 , 1.27 Footprlnl L1 1 0A REF Foo! Angle v2 0“ , a“ Lead Thickness c on? , 0.25 Lead wldlh a 0.3l , 0.5l Mold mall Angle Top or 5“ , 15“ Mold mall Angle Bottom 5 5“ , 15“ Notes: 1.Plrl ‘l vlsual lndex lealure may vary, but must be located Wilhln the hatched area 2 §Slgnlficanl Characlansuc 3. Dlmensions D and E1 do not lnclude mold (lash or molmslorls. Mold (lash or prolruslans shall nol exceed 0 15mm per slde 4 Dlmenslanlng and Inleranclng per ASME v14 SM 380. Base Dimenslon Theorellcally exact value shown Wllhdul lolerances REF Relerence Dlmenslun, usually Wlthom tolerance for lnlormallon purposes unly Mlcrochlp Technology Drawing No co4ros7c Sheet 2 of 2
MCP6071/2/4
DS22142B-page 26 © 2010 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Dual Flat, No Lead Package (MN) 7 2x3x0.75mm Body [TDFN] ‘—lEl——>-l N l NOTEI <§$§§§ -__="" \w="" \\\\\\\\\$="" 2x="" q="" 015="" c="" \\\\\\\\}="" i="" l="" 2="" ‘="" 2x="" e-="" c="" top="" view="" 0.10="" c="" l="" a="" seatlng="" plane="" l="" exfosed="" v="" m:="" r="" i="" lfl="" 2="" 8xb—="">‘ 1 \ New AlBl 010® $ 005® BOTTOM VIEW MlCl’OChlP Technology Drawmg No 004-1290
© 2010 Microchip Technology Inc. DS22142B-page 27
MCP6071/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
8-Lead Plastic Dual Flat, No Lead Package (MN) — 2x3x0.75mm Body [TDFN] NOTEZ Unils MILLIMETERS Dlmenslon Limits MIN l NOM | MAX Number ol Pins N 8 Pitch e 0.50 BSC Overall Helght A 0.70 0.75 0.80 Slandoff A1 0.00 0.02 0.05 Contacl Thickness A3 0 20 REF Overall Length D 2.00 380 Overall Wldlh E 3.00 BSC Exposed Pad Length D2 1.20 - 1.50 Exposed Pad Widlh E2 1.20 , 1.60 Contacl Wldlh b 0 20 0 25 0 30 Conlacl Length L 0.25 0.30 0.45 ConlachlrExpased Pad K 0.20 , , Notes: 1. Pln 1 Visual index lealure may Vary, bul must be located wlthln lhe hatched area. 2. Package may have one or more exposed lie bars at ends 3. Package IS saw smgulaled 4. Dlmenslonlng and toleranclng per ASME Y‘l4.5M BSC: Baslc Dlmension Theoretlcally exact value shown wwlhout tolerances. REF: Reference Dimension, usually wllhoul mlerance, lor mformaliun purposes only. Microchlp Technology Drawing No. (204-1290 Sheet 2 ol 2
MCP6071/2/4
DS22142B-page 28 © 2010 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
W2 SILK SCREEN AIS? - fl UH ———:L0000H .04 h * RECOMMENDED LAND PATTERN Units MILLIMETERS Dimension Limits MiN \ NOM \ MAX Contact Pitch E 0.50 BSC Opiionai Cenler Pad Wiaih W2 1.46 Opiionai Cenler Pad Length T2 1.36 Contaci Pad Spacing Ci 3.00 Contact Pad Widm (x5) x1 0.30 Contact Pad Length (x3) Y1 0.75 Distance Between Pads G 0 20 Noies: 1. Dimensioning and toierencing per ASME Y14.5M BSC: Basic Dimension. Theoretioaiiy exaci vaiue shown without tolerances. Microchip Technuiogy Drawing No 004-21ng
© 2010 Microchip Technology Inc. DS22142B-page 29
MCP6071/2/4
 !"#$%&''()*+, !
 

7T HHHHHHH'
MCP6071/2/4
DS22142B-page 30 © 2010 Microchip Technology Inc.
-.&/")0(+,12

 
 
 
 
 
 
 

 
   
  
  
   
  
   
  
  
  
   
   
  
   
   
   
  
   
NOTE 1
N
D
E
E1
123
b
e
A
A1
A2
L
L1
c
h
hα
β
φ
   
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] A-l‘k Gx fimmui i ’/— SiLK .3] HUME: —»E<— —="">||<—x? t="" l_="" recommended="" land="" pattern="" units="" millimeters="" dimension="" limits="" min="" \="" nom="" \="" max="" contact="" pitcn="" e="" 1.27="" bsc="" contact="" pad="" spacing="" c="" 5.40="" contact="" pad="" width="" x="" 0.50="" contact="" pad="" lenglh="" v="" 1.50="" distance="" between="" pads="" gx="" 0.67="" dislance="" between="" pads="" g="" 3.90="" notes:="" t.="" dimensioning="" and="" tolerancing="" per="" asme="" v1a.5m="" bsc="" basic="" dimension="" theoveticaily="" exact="" value="" shown="" without="" toierances="" mlcmchip="" technology="" drawing="" na="" goa-2065a="">
© 2010 Microchip Technology Inc. DS22142B-page 31
MCP6071/2/4
 

14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] TOP VIEW ._D_.“ SEATING PLANE. """ SIDE VIEW Mmmcmp Technology Drawmg 004-0370 Shem 1 of 2
MCP6071/2/4
DS22142B-page 32 © 2010 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] Units MlLLlMETERs Dimension Limits MIN | NOM | MAX Numoer at Pins N 14 Piten e u 65 ESC Overall Heignt A - - 1 20 Molded Package Thlckness A2 a so 1 oo 1 05 Slandofi A1 a 05 - u 15 Overall wiutn E 5 Ac ESC Molded Package Widtli E1 4 30 4 Ac 4 so Molded Package Length D A 90 5 00 510 Foot Length L 0 45 0 60 0 75 Footprint (L1) 1.00 REF Foot Angle W 0° . 8° Lead Thickness c 0 09 . 0 20 Lead Width D 019 . 0 30 Notes 1. Pin 1 visual index leature may vary. but must be located Within tne hatched area. 2. Dimensions D and E1 do not include mold llasn or protrusions Mold tlasn or protrusions shall not exceed 015mm per Side. 3. Dimensioning and tolerancing per ASME v14.5M BSC Basic Dimension. Theoreticaily exact value snown Witnout tolerances. REF Reference Dimension, usually without tolerance. tor inlormation purposes only. Microchlp Technulugy Drawlng Nu (204-0870 Sheet 2 of 2
© 2010 Microchip Technology Inc. DS22142B-page 33
MCP6071/2/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] 0‘ C1 ‘ E E: LE E7 l:| Elie—l.— “TE g—i \ ,l a L SILK SCREEN RECOMMENDED LAND PATTERN Units MlLLIMETERS Dimension Limits MIN | NOM | MAX Contact Pitch E o 65 380 Contact Pad Spacing c1 5 90 Contact Pad Width (x14) x1 0 45 Contact Pad Length (x14) w 1 45 Distance Belween Pads 5 a 20 Notes: ‘l. Dimensioning and Iolerancmg per ASME Y14.5M ESC' Basic Dlmension Theoretically exact Value shown wilhoul tolerances Microchip Tachnulugy Drawing No CDA-ZOB7A
MCP6071/2/4
DS22142B-page 34 © 2010 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2010 Microchip Technology Inc. DS22142B-page 35
MCP6071/2/4
APPENDIX A: REVISION HISTORY
Revision B (December 2010)
The following is the list of modifications:
1. Added new SOT-23-5 package type for
MCP6071 device.
2. Corrected Figures 2-13,2-22,2-23,2-24,2-28,
2-29 and 2-34 in Section 2.0 “Typical
Performance Curves”.
3. Modified Table 3-1 to show the pin column for
MCP6071, SOT-23-5 package.
4. Updated Section 4.1.2 “Input Voltage Limits”.
5. Added Section 4.1.3 “Input Current Limits”.
6. Added new document item in Section 5.5
“Application Notes”.
7. Updated the Product Identification System
page.
Revision A (March 2009)
Original Release of this Document.
MCP6071/2/4
DS22142B-page 36 © 2010 Microchip Technology Inc.
NOTES:
PART NO. v
© 2010 Microchip Technology Inc. DS22142B-page 37
MCP6071/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6071: Single Op Amp
MCP6071T: Single Op Amp (Tape and Reel)
(SOIC, SOT-23 and 2x3 TDFN)
MCP6072: Dual Op Amp
MCP6072T: Dual Op Amp (Tape and Reel)
(SOIC and 2x3 TDFN)
MCP6074: Quad Op Amp
MCP6074T: Quad Op Amp (Tape and Reel)
(SOIC and TSSOP)
Temperature Range: E = -40°C to +125°C
Package: MNY * = Plastic Dual Flat, No Lead, (2x3 TDFN ) 8-leadd
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
ST = Plastic TSSOP (4.4mm Body), 14-lead
* Y = Nickel palladium gold manufacturing designator. Only
available on the TDFN package.
PART NO. -X /XX
PackageTemperature
Range
Device
Examples:
a) MCP6071T-E/OT: Tape and Reel,
5LD SOT-23 pkg
b) MCP6071-E/SN: 8LD SOIC pkg
c) MCP6071T-E/SN: Tape and Reel,
8LD SOIC pkg
d) MCP6071T-E/MNY: Tape and Reel,
8LD 2x3 TDFN pkg
a) MCP6072-E/SN: 8LD SOIC pkg
b) MCP6072T-E/SN: Tape and Reel,
8LD SOIC pkg
c) MCP6072T-E/MNY: Tape and Reel
8LD 2x3 TDFN pkg
a) MCP6074-E/SL: 14LD SOIC pkg
b) MCP6074T-E/SL: Tape and Reel,
14LD SOIC pkg
c) MCP6074-E/ST: 14LD TSSOP pkg
d) MCP6074T-E/ST: Tape and Reel,
14LD TSSOP pkg
MCP6071/2/4
DS22142B-page 38 © 2010 Microchip Technology Inc.
NOTES:
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV = ISO/TS 16949:2002 =
© 2010 Microchip Technology Inc. DS22142B-page 39
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-732-3
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
’3‘ MICRDCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS22142B-page 40 © 2010 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Worldwide Sales and Service
08/04/10

Products related to this Datasheet

IC OPAMP GP 1 CIRCUIT SOT23-5
IC OPAMP GP 2 CIRCUIT 8SOIC
IC OPAMP GP 4 CIRCUIT 14SOIC
IC OPAMP GP 2 CIRCUIT 8SOIC
IC OPAMP GP 4 CIRCUIT 14TSSOP
IC OPAMP GP 1 CIRCUIT 8SOIC
IC OPAMP GP 4 CIRCUIT 14TSSOP
IC OPAMP GP 4 CIRCUIT 14TSSOP
IC OPAMP GP 4 CIRCUIT 14SOIC
IC OPAMP GP 2 CIRCUIT 8SOIC
IC OPAMP GP 1 CIRCUIT SOT23-5
IC OPAMP GP 1 CIRCUIT SOT23-5
IC OPAMP GP 1 CIRCUIT 8SOIC
IC OPAMP GP 1 CIRCUIT 8TDFN
IC OPAMP GP 1 CIRCUIT 8TDFN
IC OPAMP GP 2 CIRCUIT 8TDFN
IC OPAMP GP 1 CIRCUIT 8TDFN
IC OPAMP GP 2 CIRCUIT 8TDFN
IC OPAMP GP 2 CIRCUIT 8TDFN
IC OPAMP GP 4 CIRCUIT 14SOIC
IC OPAMP GP 1 CIRCUIT 8SOIC
IC OPAMP GP 1 CIRCUIT SOT23-5
IC OPAMP GP 2 CIRCUIT 8SOIC
IC OPAMP GP 4 CIRCUIT 14SOIC
IC OPAMP GP 1 CIRCUIT 8SOIC
IC OPAMP GP 4 CIRCUIT 14TSSOP
IC OPAMP GP 2 CIRCUIT 8SOIC
IC OPAMP GP 1 CIRCUIT SOT23-5
IC OPAMP GP 1 CIRCUIT SOT23-5