MAX5134-37 Datasheet by Maxim Integrated

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General Description
The MAX5134–MAX5137 is a family of pin-compatible
and software-compatible 16-bit and 12-bit DACs. The
MAX5134/MAX5135 are low-power, quad 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5136/MAX5137 are low-power, dual 16-/12-bit,
buffered voltage-output, high-linearity DACs. They use
a precision internal reference or a precision external ref-
erence for rail-to-rail operation. The MAX5134–MAX5137
accept a wide +2.7V to +5.25V supply-voltage range to
accommodate most low-power and low-voltage applica-
tions. These devices accept a 3-wire SPI-/QSPITM-/
MICROWIRE®-/DSP-compatible serial interface to save
board space and reduce the complexity of optically iso-
lated and transformer-isolated applications. The digital
interface’s double-buffered hardware and software
LDAC provide simultaneous output updates. The serial
interface features a READY output for easy daisy-chain-
ing of several MAX5134–MAX5137 devices and/or other
compatible devices. The MAX5134–MAX5137 include a
hardware input to reset the DAC outputs to zero or mid-
scale upon power-up or reset, providing additional safety
for applications that drive valves or other transducers
that need to be off during power-up. The high linearity of
the DACs makes these devices ideal for precision con-
trol and instrumentation applications. The MAX5134–
MAX5137 are available in an ultra-small (4mm x 4mm),
24-pin TQFN package or a 16-pin TSSOP package. Both
packages are specified over the -40°C to +105°C
extended industrial temperature range.
Applications
Automatic Test Equipment
Automatic Tuning
Communication Systems
Data Acquisition
Gain and Offset Adjustment
Portable Instrumentation
Power-Amplifier Control
Process Control and Servo Loops
Programmable Voltage and Current Sources
Features
o16-/12-Bit Resolution Available in a 4mm x 4mm,
24-Pin TQFN Package or 16-Pin TSSOP
oHardware-Selectable to Zero/Midscale DAC
Output on Power-Up or Reset
oDouble-Buffered Input Registers
oLDAC Asynchronously Updates DAC Outputs
Simultaneously
oREADY Facilitates Daisy Chaining
oHigh-Performance 10ppm/°C Internal Reference
oGuaranteed Monotonic Over All Operating
Conditions
oWide +2.7V to +5.25V Supply Range
oRail-to-Rail Buffered Output Operation
oLow Gain Error (Less Than ±0.5%FS) and Offset
(Less Than ±10mV)
o30MHz 3-Wire SPI-/QSPI-/MICROWIRE-/
DSP-Compatible Serial Interface
oCMOS-Compatible Inputs with Hysteresis
oLow-Power Consumption (ISHDN = 2µA max)
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
MAX5134–MAX5137
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
EVALUATION KIT AVAILABLE
19-4209; Rev 4; 11/13
QSPI is a trademark of Motorola Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
Ordering Information
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Note: All devices are specified over the -40°C to +105°C oper-
ating temperature range.
PART PIN-
PACKAGE
RESOLUTION
(BITS)
INL
(LSB)
MAX5134AGTG+
24 TQFN-EP*
16 Quad ±8
MAX5134AGUE+
16 TSSOP 16 Quad ±8
MAX5135GTG+
24 TQFN-EP*
12 Quad ±1
MAX5135GUE+ 16 TSSOP 12 Quad ±1
MAX5136AGTG+
24 TQFN-EP*
16 Dual ±8
MAX5136AGUE+
16 TSSOP 16 Dual ±8
MAX5137GTG+
24 TQFN-EP*
12 Dual ±1
MAX5137GUE+ 16 TSSOP 12 Dual ±1
Functional Diagrams, Pin Configurations, and Typical
Operating Circuit appear at end of data sheet.
\ayer board For detafled \nformauow Ow package lherma‘ Cowswderauows reie' to www.maxi Integrahed.comlthermaI-lulorial
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
2 Maxim Integrated
MAX5134–MAX5137
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to GND...........................................................-0.3V to +6V
DVDD to GND...........................................................-0.3V to +6V
OUT0–OUT3 to GND ....................................-0.3V to the lower of
(AVDD + 0.3V) and +6V
REFI, REFO, M/Zto GND .............................-0.3V to the lower of
(AVDD + 0.3V) and +6V
SCLK, DIN, CS to GND ................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
LDAC, READY to GND .................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
Continuous Power Dissipation (TA= +70°C)
24-Pin TQFN (derate at 27.8mW/°C above +70°C)....2222.2mW
16-Pin TSSOP (derate at 11.1mW/°C above +70°C)....888.9mW
Maximum Current into Any Input or Output
with the Exception of M/ZPin .......................................±50mA
Maximum Current into M/ZPin ...........................................±5mA
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY (Notes 1, 2)
MAX5134/MAX5136 16
Resolution N
MAX5135/MAX5137 12
Bits
(Note 3) -8 ±2 +10
Integral Nonlinearity
(MAX5134/MAX5136) INL VREFI = 5V,
VAVDD = 5.25V TA = +25°C ±6 LSB
Integral Nonlinearity
(MAX5135/MAX5137) INL VREFI = 5V, VAVDD = 5.25V -1 +0.25 +1 LSB
Differential Nonlinearity DNL Guaranteed monotonic -1.0 +1.0 LSB
Offset Error OE (Note 4) -10 ±1 +10 mV
Offset-Error Drift ±4 μV/°C
Gain Error GE (Note 4) -0.5 ±0.2 +0.5 % of FS
Gain Temperature Coefficient ±2 ppm
FS/°C
REFERENCE INPUT
VAVDD = 3V to 5.25V 2 VAVDD
Reference-Input Voltage Range VREFI VAVDD = 2.7V to 3V 2 VAVDD
- 0.2
V
Reference-Input Impedance 113 k
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θJA) ............36°C/W
Junction-to-Case Thermal Resistance (θJC) ...................3°C/W
TSSOP
Junction-to-Ambient Thermal Resistance (θJA) ............90°C/W
Junction-to-Case Thermal Resistance (θJC) .................27°C/W
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Maxim Integrated 3
MAX5134–MAX5137
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL REFERENCE
Reference Voltage VREFO T
A = +25°C 2.437 2.440 2.443 V
Reference Temperature Coefficient (Note 5) 10 25 ppm/°C
Reference Output Impedance 1
Line Regulation 100 ppm/V
Maximum Capacitive Load CR 0.1 nF
DAC OUTPUT VOLTAGE (Note 2)
Output Voltage Range No load 0.02 VAVDD
- 0.02 V
DC Output Impedance 0.1
Series resistance = 0 0.2 nF
Maximum Capacitive Load
(Note 5) CLSeries resistance = 500 15 μF
Resistive Load RL 2 k
VAVDD = 5.25V ±35
Short-Circuit Current ISC VAVDD = 2.7V -40 ±20 +40 mA
Power-Up Time From power-down mode 25 μs
DIGITAL INPUTS (SCLK, DIN, CS,LDAC) (Note 6)
Input High Voltage VIH 0.7 x
VDVDD V
Input Low Voltage VIL 0.3 x
VDVDD V
Input Leakage Current IIN V
IN = 0 or VDVDD -1 ±0.1 +1 μA
Input Capacitance CIN 10 pF
DIGITAL OUTPUTS (READY)
Output High Voltage VOH I
SOURCE = 3mA VDVDD
- 0.5 V
Output Low Voltage VOL I
SINK = 2mA 0.4 V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate SR Positive and negative 1.25 V/μs
Voltage-Output Settling Time tS1/4 scale to 3/4 scale VREFI = VAVDD = 5V
settle to ±2 LSB (Note 5) 5 μs
Digital Feedthrough Code 0, all digital inputs from 0 to VDVDD 0.5 nV•s
Major Code Transition Analog
Glitch Impulse 25 nV•s
Output Noise 10kHz 120 nV/Hz
Integrated Output Noise 1Hz to 10kHz 18 μV
DAC-to-DAC Crosstalk 25 nV•s
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
4 Maxim Integrated
MAX5134–MAX5137
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 2.7V to 5.25V, VDVDD = 2.7V to 5.25V, VAVDD VDVDD, VGND = 0V, VREFI = VAVDD - 0.25V, COUT = 200pF, ROUT = 10kΩ,
TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER REQUIREMENTS (Note 7)
Analog Supply Voltage Range VAVDD 2.7 5.25 V
Digital Supply Voltage Range VDVDD 2.7 VAVDD V
IAVDD 2.5 3.6 mA
Supply Current
(MAX5134/MAX5135) IDVDD
No load, all digital inputs at 0 or DVDD 1 10 μA
IAVDD 1.5 2.3 mA
Supply Current
(MAX5136/MAX5137) IDVDD
No load, all digital inputs at 0 or DVDD 1 10 μA
IAVPD 0.2 2
Power-Down Supply Current IDVPD
No load, all digital inputs at 0 or DVDD 0.1 2 μA
TIMING CHARACTERISTICS (Note 8) (Figure 1)
Serial-Clock Frequency fSCLK 0 30 MHz
SCLK Pulse-Width High tCH 13 ns
SCLK Pulse-Width Low tCL 13 ns
CS Fall-to-SCLK Fall Setup Time tCSS 8 ns
SCLK Fall-to CS-Rise Hold Time tCSH 5 ns
DIN-to-SCLK Fall Setup Time tDS 10 ns
DIN-to-SCLK Fall Hold Time tDH 2 ns
SCLK Fall to READY Transition tSRL (Note 9) 30 ns
CS Pulse-Width High tCSW 33 ns
LDAC Pulse Width tLDACPWL 33 ns
Note 1: Static accuracy tested without load.
Note 2: Linearity is tested within 20mV of GND and AVDD, allowing for gain and offset error.
Note 3: Codes above 2047 are guaranteed to be within ±8 LSB.
Note 4: Gain and offset tested within 100mV of GND and AVDD.
Note 5: Guaranteed by design.
Note 6: Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < VDVDD - 0.6V
or VI > 0.5V. At VI = 2.2V with VDVDD = 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input level com-
patible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing.
Note 7: Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without
AVDD.
Note 8: All timing specifications are with respect to the digital input and output thresholds.
Note 9: Maximum daisy-chain clock frequency is limited to 25MHz.
C7 C6 C5 D2 D1 D0 X
COMMAND EXECUTED ON
24TH FALLING EDGE OF SCLK
CS
SCLK
DIN
X = DON'T CARE.
tCH
t
CL
t
CSS
tDH
t
CSH
tDS
tSRL
READY
X
tCSW
D3
Figure 1. Serial-Interface Timing Diagram
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. DIGITAL INPUT CODE
MAX5134-MAX5137 toc01
DIGITAL INPUT CODE (LSB)
INL (LSB)
0 16384 32768
6
3
0
-3
-6
-9
9
49152 65536
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc02
AVDD ( V )
INL (LSB)
2.7 3.7 4.73.2 4.2 5.2
-9
-7
-5
-3
-1
1
3
5
7
9
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. DIGITAL INPUT CODE
MAX5134-MAX5137 toc04
DIGITAL INPUT CODE (LSB)
DNL (LSB)
0
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
16384 32768 49152 65536
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc05
AVDD ( V )
DNL (LSB)
2.7
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
3.7 4.7
3.2 4.2 5.2
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. TEMPERATURE
MAX5134-MAX5137 toc06
TEMPERATURE (°C)
DNL (LSB)
-40
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-20 0 20 40 60 80 100
MAX5134/MAX5136 OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc07
AVDD ( V )
OFFSET ERROR (mV)
2.7 3.7 4.73.2 4.2 5.2
-10
-8
-6
-4
-2
0
2
4
6
8
10
MAX5135/MAX5137 DIFFERENTIAL
NONLINEARITY vs. DIGITAL INPUT CODE
MAX5134-MAX5137 toc08
DIGITAL INPUT CODE (LSB)
DNL (LSB)
0 30721024 2048 4096
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
MAX5135/MAX5137 INTEGRAL
NONLINEARITY vs. DIGITAL INPUT CODE
MAX5134-MAX5137 toc09
DIGITAL INPUT CODE (LSB)
INL (LSB)
0 30721024 2048 4096
-1.00
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Maxim Integrated 5
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
OFFSET ERROR vs. TEMPERATURE
MAX5134-MAX5137 toc10
TEMPERATURE (°C)
OFFSET ERROR (mV)
-40 20 80060-20 40 100
-0.6
-0.3
-0.5
-0.2
-0.4
-0.1
0
VAVDD = 2.7V
VREFI = 2.5V
VAVDD = 5.25V
VREFI = 5V
GAIN ERROR vs.
ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc11
AVDD ( V )
GAIN ERROR (%FS)
2.7 3.7 4.73.2 4.2 5.2
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
GAIN ERROR vs. TEMPERATURE
MAX5134-MAX5137 toc12
TEMPERATURE (°C)
GAIN ERROR (%FS)
-40 20 80060-20 40 100
0.070
0.080
0.076
0.082
0.078
0.072
0.074
0.084
0.086
VAVDD = 2.7V
VAVDD = 5.25V
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX5134-MAX5137 toc13
SUPPLY VOLTAGE (V)
4.74.23.73.2
1100
1300
1500
1700
1900
2100
2300
2500
900
2.7 5.2
SUPPLY CURRENT (μA)
VOUT_ = 0
(MAX5136/MAX5137)
VOUT_ = VREFO
(MAX5136/MAX5137)
VOUT_ = 0 (MAX5134/MAX5135)
VOUT_ = VREFO (MAX5134/MAX5135)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5134-MAX5137 toc14
TEMPERATURE (°C)
20 806040-40 -20
500
1000
1500
2000
2500
3000
0
0 100
SUPPLY CURRENT (μA)
IDVDD
IAVDD (MAX5136/MAX5137)
IAVDD (MAX5134/MAX5135)
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
(POWER-DOWN MODE)
MAX5134-MAX5137 toc15
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
4.74.23.73.2
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0
2.7 5.2
TA = +25°C
TA = -40°C
TA = +105°C
EXITING/ENTERING
POWER-DOWN MODE
MAX5134-MAX5137 toc16
4μs/div
CH1
CH0
500mV/div
500mV/div
MAJOR CODE TRANSITION
MAX5134-MAX5137 toc17
1μs/div
10mV/div
SETTLING TIME UP
MAX5134-MAX5137 toc18
400ns/div
500mV/div
6 Maxim Integrated
MAX5134–MAX5137
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
L 222 mm J7m2; W: W
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
SETTLING TIME DOWN
MAX5134-MAX5137 toc19
400ns/div
500mV/div
CROSSTALK
MAX5134-MAX5137 toc20
4μs/div
10mV/div
2V/div
DIGITAL FEEDTHROUGH
MAX5134-MAX5137 toc21
40ns/div
5V/div
50mV/div
SCLK
VOUT_
DIGITAL SUPPLY CURRENT vs.
DIGITAL SUPPLY VOLTAGE
MAX5134-MAX5137 toc22
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (nA)
4.74.23.73.2
2.0
2.5
3.0
0.5
1.0
1.5
3.5
4.0
0
2.7 5.2
VAVDD = 5.25V, SCLK = 0Hz
REFERENCE VOLTAGE vs.
SUPPLY VOLTAGE
MAX5134-MAX5137 toc23
SUPPLY VOLTAGE (V)
VREFO (V)
4.74.23.73.2
2.42
2.44
2.46
2.48
2.50
2.40
2.7 5.2
TA = -40°CTA = +105°C
TA = +25°C
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX5134-MAX5137 toc24
TEMPERATURE (°C)
VREFO (V)
100806040200-20
2.4375
2.4380
2.4385
2.4390
2.4395
2.4400
2.4405
2.4370
-40
DIGITAL SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
MAX5134-MAX5137 toc25
DIGITAL INPUT VOLTAGE (V)
DIGITAL SUPPLY CURRENT (µA)
54321
500
1000
1500
2000
2500
3000
0
0
VAVDD = VDVDD = 5.25V
UP
DOWN
FULL-SCALE OUTPUT
vs. TEMPERATURE
MAX5134-MAX5137 toc26
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
10080-20 0 20 40 60
2.44
2.45
2.46
2.47
2.48
2.49
2.50
2.51
2.43
-40
EXTERNAL
REFERENCE
2.500V
INTERNAL
REFERENCE
OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX5134-MAX5137 toc27
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
252015105
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.00
030
VAVDD = 3.3V
VAVDD = 5V
Maxim Integrated 7
MAX5134–MAX5137
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
WWW
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
FULL-SCALE REFERENCE FEEDTHROUGH
MAX5134-MAX5137 toc28
500mV/div
500mV/div
0V VREF
0V VOUT
VOUT_
REF
ZERO-SCALE REFERENCE FEEDTHROUGH
MAX5134-MAX5137 toc29
20μs/div
10mV/div
500mV/div
VOUT_
VREF
REFERENCE INPUT RESPONSE
vs. FREQUENCY
MAX5134-MAX5137 toc30
INPUT FREQUENCY (kHz)
ATTENUATION (dB)
10,000100010010
-40
-35
-30
-25
-20
-15
-10
-5
0
5
-45
1
POWER-UP GLITCH, ZERO SCALE,
EXTERNAL REFERENCE
MAX5134-MAX5137 toc31
1V/div
2V/div
VOUT_
VAVDD
POWER-UP GLITCH, ZERO SCALE,
INTERNAL REFERENCE
MAX5134-MAX5137 toc32
2V/div
1V/div
VAVDD
VOUT_
POWER-UP GLITCH, MIDSCALE,
EXTERNAL REFERENCE
MAX5134-MAX5137 toc33
2V/div
1V/div
VAVDD
VOUT_
POWER-UP GLITCH, MIDSCALE,
INTERNAL REFERENCE
MAX5134-MAX5137 toc34
2V/div
1V/div
VAVDD
VOUT_
DC NOISE SPECTRUM, FFT PLOT
MAX5134-MAX5137 toc35
2.5kHz/div 25kHz
-40dBm
10dB/div
8 Maxim Integrated
MAX5134–MAX5137
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Detailed Description
The MAX5134–MAX5137 is a family of pin-compatible
and software-compatible 16-bit and 12-bit DACs. The
MAX5134/MAX5135 are low-power, quad 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5136/MAX5137 are low-power, dual 16-/12-bit,
buffered voltage-output, high-linearity DACs. The
MAX5134–MAX5137 minimize the digital noise
feedthrough from input to output by powering down the
SCLK and DIN input buffers after completion of each 24-
bit serial input. On power-up, the MAX5134–MAX5137
reset the DAC outputs to zero or midscale, depending on
the state of the M/Zinput, providing additional safety for
applications that drive valves or other transducers that
need to be off on power-up. The MAX5134–MAX5137
contain a segmented resistor string-type DAC, a serial-in
parallel-out shift register, a DAC register, power-on reset
(POR) circuit, and control logic. On the falling edge of
the clock (SCLK) pulse, the serial input (DIN) data is
shifted into the device, MSB first. During power-down, an
internal 80kΩresistor pulls DAC outputs to GND.
Output Amplifiers (OUT0–OUT3)
The MAX5134–MAX5137 include internal buffers for all
DAC outputs. The internal buffers provide improved load
regulation and transition glitch suppression for the DAC
outputs. The output buffers slew at 1.25V/µs and drive up
to 2kΩin parallel with 200pF. The analog supply voltage
(AVDD) determines the maximum output voltage range
of the device as AVDD powers the output buffers.
DAC Reference
Internal Reference
The MAX5134–MAX5137 feature an internal reference
with a nominal output of +2.44V. Connect REFO to REFI
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Maxim Integrated 9
MAX5134–MAX5137
Pin Description
PIN
MAX5134
MAX5135
MAX5136
MAX5137
TQFN-EP TSSOP TQFN-EP TSSOP
NAME FUNCTION
1 3 1 3 OUT0 Channel 0 Buffered DAC Output
2, 5, 8,
11, 14, 17,
20, 23
2, 5, 6, 8,
11, 13, 14,
17, 20, 23
6, 11 N.C. No Connection. Not internally connected.
3 4 3 4 DVDD Digital Power Supply. Bypass DVDD with a 0.1μF capacitor to GND.
4 5 4 5 READY Active-Low Ready. Indicated configuration ready. Use READY as CS for
consecutive part or as feedback to the μC.
6 6 OUT3 Channel 3 Buffered DAC Output
7, 19 7, 15 7, 19 7, 15 GND Ground
9 8 9 8 DIN Data In
10 9 10 9 CS Active-Low Chip-Select Input
12 10 12 10 SCLK Serial-Clock Input
13 11 OUT2 Channel 2 Buffered DAC Output
15 12 15 12 LDAC Load DAC Input. Active-low hardware load DAC input.
16 13 16 13 M/Z
Power-Up Reset Select. Connect M/Z to VAVDD to power up the DAC
outputs to midscale. Connect M/Z to GND to power up the DAC outputs to
zero.
18 14 18 14 OUT1 Channel 1 Buffered DAC Output
21 16 21 16 REFO Reference Voltage Output
22 1 22 1 REFI
Reference Voltage Input. Bypass REFI with a 0.1μF capacitor to GND
when using external reference.
24 2 24 2 AVDD Analog Power Supply. Bypass AVDD with a 0.1μF capacitor to GND.
— — — — EP
Exposed Pad. Not internally connected. Connect to a ground or leave
unconnected. Not intended as an electrical connection point.
www.ma m legraled.comlgroduclslreferences
when using the internal reference. Bypass REFO to
GND with a 47pF (maximum 100pF) capacitor.
Alternatively, if heavier decoupling is required, use a
1kΩresistor in series with a 1µF capacitor in parallel
with the existing 100pF capacitor. REFO can deliver up
to 100µA of current with no degradation in perfor-
mance. Configure other reference voltages by applying
a resistive potential divider with a total resistance
greater than 33kΩfrom REFO to GND.
External Reference
The external reference input features a typical input
impedance of 113kΩand accepts an input voltage
from +2V to AVDD. Connect an external voltage
supply between REFI and GND to apply an ex-
ternal reference. Leave REFO unconnected. Visit
www.maximintegrated.com/products/references for
a list of available external voltage-reference devices.
AVDD as Reference
Connect AVDD to REFI to use AVDD as the reference
voltage. Leave REFO unconnected.
Serial Interface
The MAX5134–MAX5137 3-wire serial interface is com-
patible with MICROWIRE, SPI, QSPI, and DSPs (Figures
2, 3). The interface provides three inputs, SCLK, CS,
and DIN and one output, READY. Use READY to verify
communication or to daisy-chain multiple devices (see
the
READY
section). READY is capable of driving a
20pF load with a 30ns (max) delay from the falling edge
of SCLK. The chip-select input (CS) frames the serial
data loading at DIN. Following a chip-select input’s
high-to-low transition, the data is shifted synchronously
and latched into the input register on each falling edge
of the serial-clock input (SCLK). Each serial word is 24
bits. The first 8 bits are the control word followed by 16
data bits (MSB first), as shown in Table 1. The serial
input register transfers its contents to the input registers
after loading 24 bits of data. To initiate a new data
transfer, drive CS high, keep CS high for a minimum of
33ns before the next write sequence. The SCLK can be
either high or low between CS write pulses. Figure 1
shows the timing diagram for the complete 3-wire serial-
interface transmission.
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
10 Maxim Integrated
MAX5134–MAX5137
24-BIT WORD
CONTROL BITS DATA BITS
MSB LSB
C7 C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6–D0
DESC FUNCTION
0 0 0 0 0 0 0 0 X X X X X X X X X X NOP No operation.
0 0 0 0 0 0 0 1 XXXX
DAC
3
DAC
2
DAC
1
DAC
0X X LDAC
Move contents of input
to DAC registers
indicated by 1’s. No
effect on registers
indicated by 0’s.
0 0 0 0 0 0 1 0 X X X X X X X X X X CLR Software clear.
0 0 0 0 0 0 1 1 XXXX
DAC
3
DAC
2
DAC
1
DAC
0READY_EN X Power
Control
Power down DACs
indicated by 1’s.
Set READY_EN = 1 to
enable READY.
0 0 0 0 0 1 0 1 0 0 0 0 0 0 LIN 0 0 0 Linearity Optimize DAC linearity.
0 0 0 1 DAC
3
DAC
2
DAC
1
DAC
0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Write
Write to selected input
registers (DAC output
not affected).
0 0 1 1 DAC
3
DAC
2
DAC
1
DAC
0D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Write-
through
Write to selected input
and DAC registers,
DAC outputs updated
(writethrough).
0 0 1 0 0 0 0 0 X X X X X X X X X X NOP No operation.
Table 1. Operating Mode Truth Table*
*
For the MAX5136/MAX5137, DAC2 and DAC3 do not exist. For the MAX5135/MAX5137, D0–D3 are don’t-care bits.
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Maxim Integrated 11
MAX5134–MAX5137
SCLK
DIN
READY*
CS
SI*
I/O
SO
SK
MICROWIRE
PORT
*THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICES
*BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
MAX5134–
MAX5137
Figure 2. Connections for MICROWIRE
The MAX5134–MAX5137 digital inputs are double
buffered. Depending on the command issued through the
serial interface, the input register(s) can be loaded without
affecting the DAC register(s) using the write command. To
update the DAC registers, either pulse the LDAC input low
to synchronously update all DAC outputs, or use the soft-
ware LDAC command. Use the writethrough commands
(see Table 1) to update the DAC outputs immediately after
the data is received. Only use the writethrough command
to update the DAC output immediately.
The MAX5134/MAX5136 DAC code is unipolar binary
with VOUT_ = (code/65,536) x VREF. The MAX5135/
MAX5137 DAC code is unipolar binary with VOUT_ =
(code/4096) x VREF. See Table 1 for the serial interface
commands.
Connect the MAX5134–MAX5137 DVDD supply to the
supply of the host DSP or microprocessor. The AVDD
supply may be set to any voltage within the operating
range of 2.7V to 5.25V, but must be greater than or
equal to the DVDD supply.
Writing to the Devices
Write to the MAX5134–MAX5137 using the following
sequence:
1) Drive CS low, enabling the shift register.
2) Clock 24 bits of data into DIN (C7 first and D0 last),
observing the specified setup and hold times. Bits
D15–D0 are the data bits that are written to the
internal register.
3) After clocking in the last data bit, drive CS high. CS
must remain high for 33ns before the next transmis-
sion is started.
Figure 1 shows a write operation for the transmission of
24 bits. If CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
READY*
DIN
SCLK
CS
SCK
SS
I/O
MOSI
+5V
MISO*
SPI/QSPI
PORT
*THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICES BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
MAX5134–
MAX5137
Figure 3. Connections for SPI/QSPI
CS
DIN
SCLK
READY 1
READY 3
READY 2
12324222120432 1 23 2422215432 1 23 2422215432
SLAVE 1 DATA SLAVE 2 DATA SLAVE 3 DATA
Figure 4. READY Timing
READY
Connect READY to a microcontroller (µC) input to moni-
tor the serial interface for valid communications. The
READY pulse appears 24 clock cycles after the nega-
tive edge of CS (Figure 4). Since the MAX5134–
MAX5137 look at the first 24 bits of the transmission fol-
lowing the falling edge of CS, it is possible to daisy
chain devices with different command word lengths.
READY goes high 16ns after CS is driven high.
Daisy chain multiple MAX5134–MAX5137 devices by
connecting the first device conventionally, then connect
its READY output to the CS of the following device.
Repeat for any other devices in the chain, and drive the
SCLK and DIN lines in parallel (Figure 5). When sending
commands to daisy-chained devices, the devices are
accessed serially starting with the first device in the
chain. The first 24 data bits are read by the first device,
the second 24 data bits are read by the second device
and so on (Figure 4). Figure 6 shows the configuration
when CS is not driven by the µC. These devices can be
daisy chained with other compatible devices such as the
MAX15500 output conditioner.
To perform a daisy-chain write operation, drive CS low
and output the data serially to DIN. The propagation of
the READY signal then controls how the data is read by
each device. As the data propagates through the daisy
chain, each individual command in the chain is execut-
ed on the 24th falling clock edge following the falling
edge of the respective CS input. To update just one
device in a daisy chain, send the no-op command to
the other devices in the chain.
If READY is not required, write command 0x03 (power
control) and set READY_EN = 0 (see Table 1) to dis-
able the READY output.
Clear Command
The MAX5134–MAX5137 feature a software clear com-
mand (0x02). The software clear command acts as a
software POR, erasing the contents of all registers. All
outputs return to the state determined by the M/Zinput.
Power-Down Mode
The MAX5134–MAX5137 feature a software-controlled
individual power-down mode for each channel. The
internal reference and biasing circuits power down to
conserve power when all 4 channels are powered
down. In power-down, the outputs disconnect from the
buffers and are grounded with an internal 80kΩresis-
tor. The DAC register holds the retained code so that
the output is restored when the channel powers up. The
serial interface remains active in power-down mode.
Load DAC (
LDAC
) Input
The MAX5134–MAX5137 feature an active-low LDAC
logic input that allows the outputs to update asynchro-
nously. Keep LDAC high during normal operation
(when the device is controlled only through the serial
interface). Drive LDAC low to simultaneously update all
DAC outputs with data from their respective input regis-
ters. Figure 7 shows the LDAC timing with respect to
OUT_. Holding LDAC low causes the input registers to
become transparent and data written to the DAC regis-
ters to immediately update the DAC outputs. A software
command can also activate the LDAC operation. To
activate LDAC by software, set control word 0x01 and
data bits A11–A8 to select which DAC to load, and all
other data bits to don’t care. See Table 1 for the data
format. This operation updates only the DAC outputs
that are flagged with a 1. DAC outputs flagged with a 0
remain unchanged.
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
12 Maxim Integrated
MAX5134–MAX5137
μC
SLAVE 1
SCLK
DIN
CS READY
MOSI
I/O
SCK
SLAVE 3
SCLK
DIN
CS READY
SLAVE 2
SCLK
DIN
CS READY
MAX5134–
MAX5137
MAX5134–
MAX5137
MAX5134–
MAX5137
Figure 5. Daisy-Chain Configuration
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Maxim Integrated 13
MAX5134–MAX5137
CS
DWRITE
SCLK
DREAD
CS
SCLK
DIN
SLAVE 1
SLAVE 2
SLAVE N
ERROR
INT
μC
CS1
CSm
TO OTHER CHIPS/CHAINS
READY
DOUT
CS
SCLK
DIN
READY
CS
SCLK
DIN
READY
MAX5134–
MAX5137
MAX5134–
MAX5137
MAX15500
Figure 6. Daisy Chain (CS Not Used)
Applications Information
Power-On Reset (POR)
On power-up, the input registers are set to zero, DAC
outputs power up to zero or midscale, depending on
the configuration of M/Z. Connect M/Zto GND to power
the outputs to GND. Connect M/Zto AVDD to power the
outputs to midscale.
To guarantee DAC linearity, wait until the supplies have
settled. Set the LIN bit in the DAC linearity register; wait
10ms, and clear the LIN bit.
Unipolar Output
The MAX5134–MAX5137 unipolar output voltage range
is 0 to VREFI. The output buffers each drive a load of
2kΩin parallel with 200pF.
Bipolar Output
Use the MAX5134–MAX5137 in bipolar applications with
additional external components (see the
Typical
Operating Circuit
).
Power Supplies and
Bypassing Considerations
For best performance, use a separate supply for the
MAX5134–MAX5137. Bypass both DVDD and AVDD
with high-quality ceramic capacitors to a low-imped-
ance ground as close as possible to the device.
Minimize lead lengths to reduce lead inductance.
Connect both MAX5134–MAX5137 GND inputs to the
analog ground plane.
Layout Considerations
Digital and AC transient signals on GND inputs can cre-
ate noise at the outputs. Connect both GND inputs to
form the star ground for the DAC system. Refer remote
DAC loads to this system ground for the best possible
performance. Use proper grounding techniques, such
as a multilayer board with a low-inductance ground
plane, or star connect all ground return paths back to
the MAX5134–MAX5137 GND. Carefully lay out the
traces between channels to reduce AC crosscoupling
and crosstalk. Do not use wire-wrapped boards and
sockets. Use shielding to improve noise immunity. Do
not run analog and digital signals parallel to one anoth-
er (especially clock signals) and avoid routing digital
lines underneath the MAX5134–MAX5137 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a best fit straight line drawn between two codes.
For the MAX5134/MAX5136, this best fit line is a line
drawn between codes 3072 and 64,512 of the transfer
function, once offset and gain errors have been nullified.
For the MAX5135/MAX5137, this best fit line is a line
drawn between codes 192 and 4032 of the transfer func-
tion, once offset and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height
and the ideal value of 1 LSB. If the magnitude of the
DNL is greater than -1 LSB, the DAC guarantees no
missing codes and is monotonic.
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
14 Maxim Integrated
MAX5134–MAX5137
DAC LATCH CONTENTS
MSB LSB ANALOG OUTPUT, VOUT_
1111 1111 1111 1111 VREF x (65,535/65,536)
1000 0000 0000 0000 VREF x (32,768/65,536) = 1/2 VREF
0000 0000 0000 0001 VREF x (1/65,536)
0000 0000 0000 0000 0
LDAC
OUT_
±2 LSB
tS
tLDACPWL
Figure 7. Output Timing
Table 2. MAX5134/MAX5136 Input Code
vs. Output Voltage
DAC LATCH CONTENTS
MSB LSB ANALOG OUTPUT, VOUT_
1111 1111 1111 XXXX VREF x (4095/4096)
1000 0000 0000 XXXX VREF x (2048/4096)
0000 0000 0001 XXXX VREF x (1/4096)
0000 0000 0000 XXXX 0
Table 3. MAX5135/MAX5137 Input Code
vs. Output Voltage
THIN QFN (Amm x 4mm) REH E AVDD 2 mm) a DVDD 4 LILILIL‘ILILILILI
Offset Error
Offset error indicates how well the actual transfer func-
tion matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified is
at or near the zero-scale point of the transfer function.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines
are toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB
changes from high to low and all other bits change from
low to high. The duration of the magnitude of the
switching glitch during a major carry transition is
referred to as the digital-to-analog glitch impulse.
Digital-to-Analog Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
DC DAC-to-DAC Crosstalk
Crosstalk is the amount of noise that appears on a DAC
output set to 0 when the other DAC is updated from 0 to
AVDD
Chip Information
PROCESS: BiCMOS
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Maxim Integrated 15
MAX5134–MAX5137
Pin Configurations
23
24
22
21
8
7
9
N.C.
READY
N.C.
OUT3**
10
OUT0
N.C.
LDAC
N.C.
OUT1
OUT2**
12
REFI
456
1718 16 14 13
N.C.
AVDD
CS
DIN
*EXPOSED PAD.
**N.C. FOR THE MAX5136/MAX5137.
*EP N.C.
GND
MAX5134–
MAX5137
DVDD M/Z
3
15
REF0
20 11 N.C.
N.C.
19 12 SCLK
GND
+
TOP VIEW
16
15
14
13
12
11
10
1
2
3
4
5
6
7
REFO
GND
OUT1
M/Z
DVDD
OUT0
AVDD
REFI
MAX5134–
MAX5137
LDAC
OUT2**
SCLKGND
OUT3
98CSDIN
READY
TSSOP
+
fly BUFFE 7 BUFFE W WW BUFFER F
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
16 Maxim Integrated
MAX5134–MAX5137
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
12-/16-BIT
DAC
12-/16-BIT
DAC
12-/16-BIT
DAC
12-/16-BIT
DAC
BUFFER
BUFFER
BUFFER
BUFFER
CONTROL LOGIC
POR POWER-DOWN
CONTROL
SERIAL-TO-
PARALLEL
CONVERTER
CS
SCLK
DIN
OUT0
REFI
REFERENCE
AVDD DVDD
OUT1
LDAC
OUT2
OUT3
READY
REFO
GND
M/Z
MAX5134
MAX5135
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
Functional Diagrams
Y f BUFFER
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Maxim Integrated 17
MAX5134–MAX5137
INPUT
REGISTER
INPUT
REGISTER
12-/16-BIT
DAC
12-/16-BIT
DAC
BUFFER
BUFFER
CONTROL LOGIC
POR POWER-DOWN
CONTROL
SERIAL-TO-
PARALLEL
CONVERTER
CS
SCLK
DIN
OUT0
REFI
REFERENCE
AVDD DVDD
LDAC
OUT1
READY
REFO
GND
M/Z
MAX5136
MAX5137
DAC
REGISTER
DAC
REGISTER
Functional Diagrams (continued)
www.ma integrated.camlpackages 21-0139 90-0022 21-0066 90-0117
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
18 Maxim Integrated
MAX5134–MAX5137
DAC
CS
SCLK
DIN
R1 R2
DVDD AVDD
OUT
REFO
GND
100nF
M/Z
LDAC
DIGITAL POWER
SUPPLY
ANALOG POWER
SUPPLY
100nF
READY
REFI
47pF
100nF
NOTE: SHOWN IN BIPOLAR CONFIGURATION.
MAX5134–
MAX5137
Typical Operating Circuit
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
24 TQFN-EP T2444+4 21-0139 90-0022
16 TSSOP U16+2 21-0066 90-0117
maxim Integrated
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
MAX5134–MAX5137
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
19
© 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 7/08 Initial release of MAX5134.
1 10/08 Initial release of MAX5135/MAX5136/MAX5137. 1–19
Added the TSSOP package to the Ordering Information table, Absolute Maximum Ratings
section, and Pin Description table. 1, 2, 9
Changed the Major Code Transition Analog Glitch Impulse parameter in the Electrical
Characteristics table from 12nVs (typ) to 25nVs (typ). 3
In the Typical Operating Characteristics; added “SCLK = 0Hz” to TOC22, changed
TOC28 to “500mV/div” from “500mV”; and changed the title of TOC30 to “Reference Input
Response vs. Frequency.”
7, 8
Added a statement to the Internal Reference section regarding using a resistor in series. 10
Changed the Functional Diagrams to show LDAC drawn to the DAC register. 16, 17
2 1/10
Replaced the Typical Operating Circuit to show the correct op amp. 18
3 1/13 Revised the Absolute Maximum Ratings and added the Package Thermal Characteristics
section. Updated the Electrical Characteristics table. 2–4, 9
4 11/13 Revised Ordering Information.1

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