ANALOG Rugged, Military Temperature Range, DEVICES 10 kHz Bandwidth Isolation Amplifier ADZIJ3SN FEATURES Rugged Designcharacterlzed to MIL-stones Environmental Test Methods 1004 (Moisture Resistance) 1010 Condition B (Temperature Cycling, —55°C to +125°C) 2002 Condition B (Mechanical Shock @ 1,500 g [or 0.5 ms) 2004 (Lead Integrity) 2007 Condition A (Variable Frequency Vibration @ 2° 9) 2015 (Resistance to Solvents) Reliable D n: Coniorms to stringent Quality and Reliabl ty Standards Characterized to the Full Military Temperature Range —55°C to +125°c Rated Performance 10 kHz Full Power Bandwidth Low Nonlinearity: 10.05% max Wide Output Range: tIOV min (Into a 2.5 kfl Load) High CMV Isolation: 1500 V RMS Continuous Isolated Power: :15 V DC @ :5 mA Small Size: 2.23"><0r83”xo.65” 56.5="" mmxzli="" mmx16.5="" mm="" unoommitted="" input="" ampl="" er="" two-port="" isolation="" through="" transformer="" coupling="" isolation="" amplifiers="" provide="" galvanic="" isolation="" between="" the="" input="" and="" output="" stages="" eliminate="" ground="" loops="" reject="" high="" common="" mode="" voltages="" and="" noise="" protect="" sensitive="" electronic="" signal="" processing="" systems="" from="" transient="" and/or="" fault="" voltages="" applications="" include="" monitoring="" and="" control="" multichannel="" data="" acqu="" instrumentation="" and/or="" control="" current="" shunt="" measurements="" high="" voltage="" instrumentation="" amplifier="" general="" description="" the="" adzossn="" is="" designed="" and="" built="" expressly="" for="" use="" in="" hostile="" operating="" environmeurs.="" the="" adzossn="" is="" also="" an="" integral="" mem-="" ber="" of="" analog="" devices'="" adzoo="" series="" of="" low="" cost,="" high="" perfor-="" mance,="" transformer="" coupled="" isolation="" amplifiers.="" technological="" innovations="" in="" circuit="" design,="" transformer="" construction,="" surface="" mount="" components="" and="" assembly="" automation="" have="" resulted="" in="" a="" rugged,="" economical,="" military="" temperature="" range="" isolator="" that="" either="" retains="" or="" improves="" upon="" the="" key="" performance="" spec="" flea-="" tions="" of="" the="" adzoz/adzm="" line.="" rev.="" a="" dorurnent="" feedback="" lmmmwmmbmmhmmmmm="" wbmwmwmhmmnmmmmam="" mmmflnmmmmmmuswmmwmmmw="" mkwmmmummummawmwmmmmm="" immwmmmmmrmmm="" functional="" block="" diagram="" aomsn="" :lreuwuumr="" $th="" \_.="" mm="" aw="" escautun="" l="" mural="" puma“="" the="" adzobsn="" provides="" total="" galvanic="" isolation="" between="" the="" in-="" put="" and="" output="" stages="" of="" the="" isolation="" amplifier,="" including="" the="" power="" supplies,="" through="" the="" use="" of="" internal="" transformer="" cou-="" pling,="" the="" functionally="" complete="" design="" of="" the="" adzobsn,="" pow-="" ered="" by="" a="" single="" +15="" v="" dc="" supply,="" elimimres="" the="" need="" for="" an="" external="" dc/dc="" converter.="" this="" permits="" the="" designer="" to="" minimize="" the="" necessary="" circuit="" overhead="" and="" consequently="" reduce="" the="" over-="" all="" dcsign="" and="" component="" costs.="" furthermore,="" the="" power="" con-="" sumption,="" nonlinearity="" and="" drifr="" characteristics="" of="" transformer="" coupled="" devices="" are="" vastly="" superior="" to="" those="" achievable="" with="" other="" isolation="" technologies,="" without="" sacrificing="" bandwidth="" or="" noise="" performance,="" finally,="" the="" adzossn="" will="" maintain="" its="" high="" operating="" performance="" even="" under="" sustained="" common="" mode="" stress.="" the="" design="" of="" the="" adzossn="" emphasizes="" maximum="" flexibility="" and="" ease="" of="" use="" in="" a="" broad="" range="" of="" applications="" where="" signals="" must="" be="" measured="" or="" transmitted="" under="" high="" cmv="" condirions.="" the="" adzossn="" has="" a="" :10="" v="" output="" range,="" an="" uncommitted="" in»="" put="" amplifier,="" an="" output="" buffer,="" a="" 10="" khz="" rull="" power="" bandwidth="" and="" a="" front-end="" isolated="" power="" supply="" or="" :15="" v="" dc="" (a:="" :5="" ma.="" one="" technology="" way,="" p.0.="" box="" 9105,="" norwood,="" ma="" nzoszralos,="" u.5.a.="" tel:="" 7313214700="" @2015="" analog="" devices,="" inc.="" all="" rights="" reserved,="" yethniril="" suwovt="">
r.ANALOG
WDEVICES
Rugged,
Military
Temperature
Range,
1 0
kHz
Bandwidth
Isolation
Amplifier
FEATURES
Rugged Design:
Environmental
Test
Methods
1004
(Moisture
Resistance)
1010
Condition
B (Temperature Cycling,
-55°C
to
+125°C)
2002
Condition
B (Mechanical
Shock@
1,500 g
for
0.5 ms)
2004 (Lead
Integrity)
2007
Condition
A (Variable Frequency
Vibration
@20g)
2015 (Resistance
to
Solvents)
Reliable Design:
Conforms
to
Stringent
Quality
and
Reliability
Standards
Characterized
to
the
Full
Military
Temperature
Range
-55°C
to
+125°C Rated Performance
10 kHz Full
Power
Bandwidth
Low
Nonlinearity:
±0.025%
max
Wide
Output
Range:
±10
V
min
(Into a 2.5
k!l
Load)
High
CMV
Isolation: 1500 V RMS
Continuous
Isolated
Power:
±15
V
DC@
±5
mA
Small
Size: 2.23"x0.83"x0.65"
56.6
mmx21.1
mmx16.5
mm
Uncommitted
Input
Amplifier
Two-Port
Isolation
Through
Transformer
Coupling
ISOLATION AMPLIFIERS
Provide Galvanic Isolation Between
the
Input
and
Output
Stages
Eliminate
Ground
Loops
Reject High
Common
Mode
Voltages
and Noise
Protect Sensitive Electronic Signal Processing Systems
from
Transient
and/or
Fault
Voltages
APPLICATIONS INCLUDE
Engine
Monitoring
and
Control
Mobile
Multichannel
Data
Acquisition
Systems
Instrumentation
and/or
Control
Signal Isolation
Current
Shunt
Measurements
High
Voltage
Instrumentation
Amplifier
GENERAL DESCRIPTION
The
AD203SN
is
designed and built expressly for use in hostile
operating environments.
The
AD203SN
is
also an integral mem-
ber
of
Analog Devices' AD200 Series of low cost, high perfor-
mance, transformer coupled isolation amplifiers. Technological
innovations in circuit design, transformer construction, surface
mount components and assembly automation have resulted in a
rugged, economical, military temperature range isolator that
either retains or improves upon the key performance specifica-
tions
of
the AD202/AD204 line.
AD203SN
I
FUNCTIONAL BLOCK DIAGRAM
MODULATOR
DEMODULATOR
'I
INPUT
PORT~
~OUTPUT
PORT
The
AD203SN provides total galvanic isolation between the in-
put
and output stages
of
the isolation amplifier, including the
power supplies, through the use
of
internal transformer cou-
pling.
The
functionally complete design
of
the AD203SN, pow-
ered by a single +
15
V de supply, eliminates the need for an
external de/de converter. This permits the designer to minimize
the necessary circuit overhead and consequently reduce the over-
all design and component costs. Furthermore, the power con-
sumption, nonlinearity and drift characteristics
of
transformer
coupled devices are vastly superior to those achievable with
other isolation technologies, without sacrificing bandwidth or
noise performance. Finally, the AD203SN will maintain its high
operating performance even under sustained common mode
stress.
The
design
of
the AD203SN emphasizes maximum flexibility
and ease
of
use in a broad range
of
applications where signals
must be measured or transmitted under high CMV conditions.
The
AD203SN has a ±
10
V output range, an uncommitted in-
put
amplifier, an output buffer, a
10
kHz
full power bandwidth
and a front-end isolated power supply
of
±
15
V de
(CT;
± 5 mA.
C
GAIN Range Error vso Temperature‘ i55°C to + IZS°C 755°C to +25°C -40"C to +25°C -ZS“C to +ZS°C +25°C to +125°C vs. Time vs, Supply Voltage Nonlineatityz, G=l WV, :10 V Output Swing “12035" —SPEC|FICATIONS (typical @ +25%. Vs = +15 V dcyllnless otherwise noted) 1 V/V—loo WV :1% typ (14% max) 50 1:13me 100 ppm/“C 80 ppm/“C 60 ppm/”C S ppm/T :50 ppm/ 1000 bouts :CLOOS'WV *0.0l2% (*0.025% max) INPUT VOLTAGE RATINGS Linear Differential Range Max CMV Input to Output AC, 60 Hz, Continuous Continuous (ac and dc) Common Mode Rejection (CMR) @ 60 Hz R5 $100 a (1-11 at L0 Inputs), G :1VN G = 100 V/V R; s 1 kn (Input, 1H, L0 or Both), G = 1—100 V/V Leakage Current, Input to Output @ 240 V ms, 60 Hz :10V 1500 V [Ins :2000 V peak 106dB lZOdB 96dB (min) 4,0111% nns (max) INPUT IMPEDANCE Differential (G : 1 VN) 1012 9 Common Mode 2 13011415 pF INPUT BIAS CURRENT Initial @ +25“C 30 pA Current @ +125°C 30 nA INPUT DIFFERENCE CURRENT Initial @ +25°C :5 pA Currant (13 +125“C :5 11A INPUT NOISE Voltage, 0.1 Hz to 100 Hz 4 11V p—p Voltage, Frequency > 200 Hz 50 nV/\/Hz FREQUENCY RESPONSE Bandwidth (vOUT s 20 V p—p, G = 1-100 WV) 10 kHz Slew Rate 0.5 V/ps Settling Time to 20.10% 160 us OFFSET VOLTAGE, REFERRED TO MUT (RTI) Initial @ +25°c (Adjustable to Zero) vet Temperature (—55°C to +1290 : (5 + ZS/G) luv (max) 1 (a + 100/0) lLV/“C RATED OUTPUTa Voltage (Out H1 10 Out 1.0) @ RL : 5,0 km :10 V (min) Current :4 mA Maximum Capacitive Lond‘ 270 pF Output Resistance 02 0 Output Ripple, 100 kHz Bandwidth 15 mV p—p 5 kHz Bandwidth 0 7 mV rrns ISOLATED POWER OUTPUT5 Voltage, No Load :15 v Accuncy 1 5% Current (Either Output) 5 mA Ragulatlon, No Load (0 Full Load 5% ' Ripple, 100 kHz Bandwidth, Full Load 110 mV p—p POWER SUPPLY Voltage, Rated Performance Voltage, Opemting Performance6 Current, No Load (Va : +15 V dc) +15Vdc(:5%) +12Vde to +16Vdc ZOmA
-\
AD203SN-SPECIFICAJIQNS
(typical@
+25°C,
Vs=
+15
V
de
~\iless
otherwise
noted)
GAIN
,!
I
Range 1 VN-100
VN
Error ±1% typ (±4% max)
vs.
Temperature1
-55°C to +
125°C
50
ppm/°C
-55°C to +25°C
100
ppm/°C
-40°C
to +
25°C
80
ppm/°C
-
25°C
to +
25°C
60
ppm/°C
+
25°C
to +
125°C
5 ppm/°C
vs.
Time ±
50
ppm/1000 hours
vs.
Supply Voltage
±0.005%N
Nonlinearity2,
G=
1
VN,
±10 V Output Swing ±0.012% (±0.025% max)
INPUT
VOLTAGE RATINGS
Linear Differential Range
±lOV
Max CMV Input to Output
AC,
60
Hz, Continuous
1500
V rms
Continuous
(ac
and de) ±2000 V peak
Common Mode Rejection (CMR) @
60
Hz
Rs
'.'S
100
!1
(HI & LO Inputs), G = 1
VN
106dB
G =
100
VN
120dB
Rs
'.'S
1
k!1
(Input, HI, LO or Both), G = 1-100
VN
96dB (min)
Leakage Current, Input to
Output@
240
V rms,
60
Hz 4.0µA rms (max)
INPUT
IMPEDANCE
Differential
(G
= 1
VN)
1012
n
Common Mode 2
G!1ll4.5
pF
INPUT
BIAS CURRENT
Initial @ +
25°C
30
pA
Current @ +
125°C
30
nA
INPUT
DIFFERENCE CURRENT
Initial @ +
25°C
±5
pA
Current @ +
125°C
±5
nA
INPUT
NOISE
Voltage, 0.1
Hz
to
100
Hz 4 µV
p-p
Voltage,
Frequency>
200
Hz
50
nV/VHz
FREQUENCY RESPONSE
Bandwidth
(VoUT
'.'S
20
V p--p, G = 1-100
VN)
10
kHz
Slew
Rate 0.5 V/µs
Settling Time to ±0.10%
160
µs
OFFSET VOLTAGE, REFERRED
TO
INPUT (RTI)
Initial @ +
25°C
(Adjustable to Zero) ±
(5
+
25/G)
mV (max)
vs.
Temperature
(-55°C
to +
125°C)
±
(6
+
100/G)
µVl°C
RATED OUTPUT3
Voltage (Out
HI
to Out LO) @
RL
= 5.0
k!1
±10 V (min)
Current
±4mA
Maximum Capacitive Load4
270
pF
Output Resistance 0.2 n
Output Ripple,
100
kHz Bandwidth
15
mV
p-p
5 kHz Bandwidth 0.7 mV rms
ISOLATED POWER OUTPUT5
Voltage, No Load ±15 v
Accuracy ±5%
Current (Either Output)
5mA
Re~ulation,
No Load to Full Load
5%
Ripple,
100
kHz
Bandwidth, Full Load llO
mV
p--p
POWER SUPPLY .
Voltage, Rated Performance +
15
V de (±5%)
Voltage, Operating Performance6 +
12
V de to +
16
V de
Current, No Load
(Vs=
+15 V de)
20mA
-2-
Rev. B
TEMPERATURE RANGE Rated Performance -55“C Io — 125°C ADZU3SN Smxag: —55°C to +125°C PACKAGE DIMENSIONS Inches 2.23 X 0.83 x 0.65 Minimum-s 56.6% 21.! X 16 i NOTES 'Refer m FIguIe I fox 3 plol ofgaln versus Imperaulre. 1m gmns gmm man so WV, 8 100 pF mpammr from m: feedback InnnmnI om: Input an amp [Pm say no the Inpul cnnunon mmmai (Pm 2) is recommended “1 order m mimmize m: gain nonlincimy. Rcfu w mum 17 Im a mun schmmic. ’Far mammal Infurmauon on {ht Izmd 0mm Dmmclels, mm In Figm 9 for a plu! um: Output Voluge Swing vs. Pm! Supply Vollagc, End FIxure In for In: Oumuz Cunt-It vs. Tempemm and Pam Supply Vulmgt relauunship. ‘For luger clpacilivc loads, n is mumandcd ma: n 4.7 n resumr he placed m scrim with [he Ioad m order [0 snppms poSSIble uulpul oscillauons. 51.0 “F (mm) decoupling Is minim. “Refer [a Figure 9 [or a plot ofuulpllt voltagz swung Venus supply volllge. Speaficatmns snbiecl [a change wnnnuz mace. ACIDSZ MATING SOCKET ADZOJSN PIN DESIGNATION us (57 H mm“ mm“ PIN DESIGNATION FUNC‘HON roar ib 1 um Imur or Amp: NONINVERTING INPUT INPUT 1 IN com I PUI’ common IIII-Irr .54. A — _ .10 1.,_ ‘ 3 IN7 INFUY OP AM! INVERrING INPUT INPUT , I Is ow RYN oumIT RETURN auwuv i i 19 cm NI onnuT SIGNAL cum" :0 m IN IIc rowan sun“ mruT OUTPUY — G) __ — ‘ — 71;“; 321“; 21 NONE NONE » ‘ :2 9w: com Ix: rowan sumv ooMMoN ouwur i i as In,“ ISOLATED rows mpur -a-u~u ,fig___, :7 :1 v“. Isaursnmws INPUT ‘ ' ‘ as m INFUY on Am oummszmucx INPUY / m2! m—A lv :1 Imus) m as m “1’ o no (A u. an m 2 mass conoLLmG DIMENSIONS ARE IN mcnss, mumsran mMENsInNs ARE cnwERIEn EnulVALENTS AND sHDuLD Nor a: user: FOR DESIGN CAUTION ESD (electrosmic discharge) scnsmve device. Permanent damage may occur on unconnecxed devices subiect to high energy elemostaric fields. Unused devices must be discharged (0 The destination socket befom devices are removed. Note: Per MIL-STD-883C, Method 3015, this device have been classified as a Category 2 ESD scan I we device. WARNING!
AD203SN
TEMPERATURE RANGE
Rated Performance
Storage
PACKAGE DIMENSIONS
Inches
Millimeters
NOTES
'R
efer
to
Figure 1 for a plot
of
ga
in
ve
rsus temperature.
-55°C to +
125
°C
-
55
°C to +
125
°C
2.23 x 0.83 x 0.65
56.6·X 21.l X
16
5
2
For
gains greater than
50
VN,
a 1
00
pF
capacitor from
th
e feedback terminal of the input op amp (Pin
38
) to the input
co
mmon terminal (Pin 2)
is
recommended in order
to
minimize the gain nonlinearity. Refer
to
Figure
17
for a circuit schematic.
3
For
additional information on the Rated Output parameters, refer
to
Figure 9 for a plot
of
the Output
Vo
ltage Swing
vs.
Power Supply Voltage, and
Figure
10
for the Output Current vs.
Te
mperature and Po
we
r Supply Voltage
re
lationship.
•For larger capacitive
lo
ads, it is recommended that a 4. 7
fl
resistor be placed in series with the load in order to suppress possible output oscillation
s.
'
LO
µF
(min) decoupling is required.
6Refer
to
Figure 9 for a plot
of
output voltage
sw
ing versus supply
vo
ltage.
Specifications subject to change without notice.
AC1062
MATING
SOCKET
AD203SN
PIN
DESIGNATIONS
I'
..
,.
____
:::
::
·
::
___
_ I
·1
l~~
~+--'--
ol
o=-
-
=--=--
-
-
-=--'--olo-
o
-
:-
T~1
- 0
--
--
----
+ - 0.600 0.825
-!
-0-
0
-----
---
----
0-!-J:_
J(21.0)
I I I
PIN DESIGNATION FUNCTION
1
IN+
INPUT OP
AMP
: NONINVERTING INPUT
2
INCOM
INPUT COMMON
3
IN-
INPUT OP
AMP
: INVERTING INPUT
18
OUT RTN OUTPUT RETURN
19
OUTHI
OUTPUT SIGNAL
20
PWRIN
DC POWER SUPPLY INPUT
21
NONE NONE
22
PWRCOM
DC
POWER SUPPLY
COMMON
36
V
;so+
ISOLATED POWER: + DC
37
VISO- ISOLATED POWER: - DC
38
FB
INPUT OP
AMP
: OUTPUT/FEEDBACK
0.125
TYP--11--
0.
100
(2
.
5)
DIA
.
C/S
TO
l3·2l
0.
180
(4.6)
DIA
. TYP
2 PLACES
CON
TROLL
ING
DIMEN
SIO
NS
ARE
IN
INCHES
, MILLIMETER DIMENSIONS
ARE CONVERTED EQUIVALENTS AND SHOULD
NOT
BE
USED
FOR
DESIGN
.
PORT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
-
OUTPUT
INPUT
INPUT
INPUT
CAUTION~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
ESD (electrostatic discharge) sens1uve device. Permanent damage m
ay
occur on unconnected
devices subject to high energy electrostatic field
s.
Unused devices must be discharged to the
destination
soc
ket before devices are removed.
Note: Per MIL-STD-883C, Method
3015
, this device have been classified
as
a Category 2 ESD
sensiti
ve
device.
-3-
WARNING!
0
~
~ENS
l
llVl
UtV
I
Cl
Rev. B
1102038" PRODUCT HIGHLIGHTS Rugged Design. The ADZD3SN is specifically designed for applications where ruggedness and high performance are the key requirements. The ruggedness of the ADZOSSN design meets MIL-STD-SSSC Methods 1004 (Moisture Resistance), 1010 Condition 13 (Temperature Cycling, —55‘C to +125°C), 2002 Condition B (Mechanical Shock ((2) 1,500 g for 0.5 ms), 2004 (Lead Integrity), 2007 Condition A (Variable Frequency Vibra- tion @ 20 g) and 2015 (Resistance to Solvents). Engine and vehicular monitor/control systems as well as mobile instrumentation and control systems are some examples of appli- cations for which the AD203SN is welI suited. Military Temperature Range Rating. With its perfonnanoe rated over the *SS°C to +125°C MIL specification temperature range, the ADZOSSN is an excellent choice in applications where severe environmental conditions may be encountered. Examples include engine monitoring/control systems and remote power line monitoring. to kHz Bandwidth. With a full power bandwidth of 10 kHz, the ADZO3SN is effective in control loop applications where a smaller bandwidth could induce control system instabilities. Excellent Common Mode Performance. The ADzozSN pmr vides a 1.5 kV rms continuous common mode isolation. A low common mode input capacitance of 4.5 pF, inclusive of power isolation, results in a minimum 9o dB of CMR as well as a very low leakage current of 4.0 uA rtns (max @t 240 v ms. 60 Hz). High Accuracy. Exhibiting a maximum nonlinearity of 10.05% and a low gain temperature coefficient, averaging 50 ppml°C over the full temperature range, the ADZOiSN pro- vides high isolation without loss of signal integrity and quality. Isolated Power, An isolated power supply capable of deliver- ing :15 V dc @ :5 mA is available at the input port of [he isolator. This permits the AD203SN to power up floating signal conditioners, front-end amplifiers or remote transducers at the input. Flexible input Stage. An uncommitted op amp is provided on the input stage. This amplifier provides input bullering and gain as needed. It also facilitates a host of alIeImIIVe input functions including filtering, summing, high voltage ranges and current (transimpedancc) inputs. DESCRIPTION OF KEY SPECIFICATIONS Gain Nonlinearity. Nonlinearity is defined as the peak devia- tion of the output voltage from the best straight line and is ex- pressed as a percent of peak—to—peak output voltage span. The nonlinearin of the model ADZOSSN, which operates at a 20 V p—p output span, is :0.025% or :5 my. Good nonlinearity is critical for retaining signal fidelity. Max CMV, Input to Output. Maximum common mode volt age (CMV) describes the amount of voltage that may be applied across both Inpul terminals with respect to the output terminals without degrading the integrity of the isolation barrier. High input»to-output CMV capability is necessary in applications where high CMV inputs exist or high voltage transients may occur at the input. Common Mode Reiection (CMR). CMR describes the isola- tor‘s ability to reiect common mode voltages that may exist be- tween the inputs and the outputs. High CMR is required when it is necessary to process small signals riding on high common mode voltages. Leakage Current. This is the current that flows from the in- put common across the lsolatlon barrier to the output common when the power-line voltage (either 115 V or 240 v ms, 60 Hz) is impressed on the inputs. Leakage current is dependent on the magnitude of the coupling capacitance between the input and the output ports. Line frequency leakage current levels are unaf- fected by the power ON or OFF condltlon of the ADZOSSN. Common Mode Input Impedance. This is defined to he the impedance seen across either input terminal (he, +IN or —IN) and the input common. Input Noise. This specification characterizes the voltage noise levels that are generated internally by the isolation amplifier. In order to facilitate a comparison between the “isolator back- ground noise“ levels and the expected input signal levels the input noise parameter is referred to the input. Input noise is a function of the noise bandwidth, is, the fre- quency range over which the noise characteristics are measured. Offset Voltage, Referred to Input (RTI). The offset voltage describes the isolation amplifier’s total dc offset voltage with the inputs grounded. The offset voltage is referred to the input in order to allow for a comparison of the dc offset voltages with the expected input signal levels. The total offset comes from two sources, namely from the input and output stages, and is gain dependent. To compute the offset voltage, RTI, the isolator is modelled as two cascaded amplifier stages. The input stage has a variable gain 0 while the output isolation stage has a fixed gain of 1. RT] onset is then given by: ED: (RTI) = East + 5052/0 where: E05, : Total input stage offset voltage E05, = Output stage onset voltage G = Input stage gain. Offset voltage drift, RTI, is calculated in an identical manner. Isolated Power Output. Dual supply voltages, completely isolated from the input power supply terminals, provide the mpability to excite floating input signal conditioners as well as remote transducers.
AD203SN
PRODUCT
HIGHLIGHTS
Rugged Design.
The
AD203SN is specifically designed for
applications where ruggedness and high performance are the key
requirements. The ruggedness
of
the AD203SN design meets
MIL-STD-883C Methods
1004
(Moisture Resistance),
1010
Condition B (Temperature Cycling, -SS°C to + 125°C), 2002
Condition B (Mechanical Shock @ 1,500 g for 0.5 ms), 2004
(Lead Integrity), 2007 Condition A (Variable Frequency Vibra-
tion @
20
g)
and
2015
(Resistance to Solvents).
Engine and vehicular monitor/control systems
as
well
as
mobile
instrumentation and control systems are some examples
of
appli-
cations for which the AD203SN
is
well suited.
Military
Temperature
Range Rating. With its performance
rated over the -SS°C to +
125°C
MIL
specification temperature
range, the AD203SN
is
an excellent choice in applications where
severe environmental conditions may be encountered. Examples
include engine monitoring/control systems and remote power
line monitoring.
10 kHz Bandwidth. With a full power bandwidth
of
10
kHz,
the AD203SN
is
effective in control loop applications where a
smaller bandwidth could induce control system instabilities.
Excellent Common
Mode
Performance. The AD203SN pro-
vides a
1.5
kV rms continuous common mode isolation. A low
common mode input capacitance
of
4.5
pF,
inclusive
of
power
isolation, results in a minimum
96
dB
of
CMR as well
as
a very
low leakage current
of
4.0 µA rms (max @ 240 V rms,
60
Hz).
High Accuracy. Exhibiting a maximum nonlinearity
of
±0.025% and a low gain temperature coefficient, averaging
SO
ppm/°C over the full temperature range, the AD203SN pro-
vides high isolation without loss
of
signal integrity and quality.
Isolated Power. An isolated power supply capable
of
deliver-
ing ±
15
V de @ ± 5 mA
is
available at the input port
of
the
isolator. This permits the AD203SN to power
up
floating signal
conditioners, front-end amplifiers or remote transducers at the
input.
Flexible
Input
Stage. An uncommitted op amp
is
provided on
the input stage. This amplifier provides input buffering and gain
as
needed.
It
also facilitates a host
of
alternative input functions
including filtering, summing, high voltage ranges and current
(transimpedance) inputs.
DESCRIPTION
OF
KEY
SPECIFICATIONS
Gain
Nonlinearity. Nonlinearity
is
defined
as
the peak devia-
tion
of
the output voltage from the best straight line and
is
ex-
pressed as a percent
of
peak-to-peak output voltage span.
The
nonlinearity
of
the model AD203SN, which operates at a
20
V
p-p
output span,
is
±0.025% or
±5
mV. Good nonlinearity
is
critical for retaining signal fidelity.
Max
CMV,
Input
to
Output. Maximum common mode volt-
age (CMV) describes the amount
of
voltage that may be applied
across both input terminals with respect to the output terminals
without degrading the integrity
of
the isolation barrier. High
input-to-output CMV capability
is
necessary in applications
where high CMV inputs exist or high voltage transients may
occur at the input.
Common
Mode
Rejection (CMR). CMR describes the isola-
tor's ability to reject common mode voltages that may exist be-
tween the inputs and the outputs. High CMR
is
required when
it
is
necessary to process small signals riding on high common
mode voltages.
Leakage Current. This is the current that flows from the in-
put
common across the isolation barrier
to
the output common
when the power-line voltage (either
115
V or 240 V rms,
60
Hz)
is
impressed on the inputs. Leakage current
is
dependent on the
magnitude
of
the coupling capacitance between the input and
the output ports. Line frequency leakage current levels are unaf-
fected by the power
ON
or
OFF
condition
of
the AD203SN.
Common
Mode
Input Impedance. This
is
defined to be the
impedance seen across either input terminal (i.e.,
+IN
or -IN)
and the input common.
Input
Noise. This specification characterizes the voltage noise
levels that are generated internally by the isolation amplifier.
In
order to facilitate a comparison between the "isolator back-
ground noise" levels and the expected input signal levels the
input noise parameter
is
referred
to
the input.
Input noise
is
a function
of
the noise bandwidth, i.e., the fre-
quency range over which the noise characteristics are measured.
Offset Voltage, Referred
to
Input
(RTI). The offset voltage
describes the isolation amplifier's total de offset voltage with the
inputs grounded. The offset voltage
is
referred to the input in
order to allow for a comparison
of
the de offset voltages with the
expected input signal levels.
The
total offset comes from two
sources, namely from the input and output stages, and
is
gain
dependent. To compute the offset voltage,
RTI,
the isolator
is
modelled
as
two cascaded amplifier stages. The input stage has a
variable gain G while the output isolation stage has a fixed gain
of
1.
RTI
offset
is
then given by:
E
05
(RT!)
= E
051
+ E
05
iG
where:
E
081
= Total input stage offset voltage
E0s2 =
Output
stage offset voltage
G = Input stage gain.
Offset voltage drift,
RTI,
is
calculated in an identical manner.
Isolated Power Output. Dual supply voltages, completely
isolated from the input power supply terminals, provide the
capability to excite floating input signal conditioners
as
well
as
remote transducers.
-4-
Rev. B
ADZD3SN PERFORMANCE CHARACTERISTICS This section details the key specifications of the ADZOSSN that exhibit a functional dependence on such variables as frequency, power supply load, output voltage swing, bypass capacitance and temperature. Table 1 summarizes the performance charac» teristics that will be discussed in this section. For the sake of completeness, a typical dynamic output response of the AD203SN is included. Gain Temperature Coellicient. Figure 1 presents the ADZOSSN's gain temperature coefficient over the entire ~55°C to +125°C temperature range. use .rn ~55 -w as o m at an rrnptnwar V to Figure 1. Gain (ppm of Span) vs. Temperature (“0) None: 1 ppm (part per million) is equivllent to 0.0001%, Gain Nonlinearity. The maximum nonlineanty error of the ADZOSSN, at a gain of 1 WV, is specified as :01025% or :5 mV. The nonlinearity performance of die ADZO3SN is de~ pendent on the output volmge swing and this dependency is il- lustrated in Figure 2. The horizontal axis represents the gain error, expressed either in percent of peak-(opeak oulpul span Ge, “/0 of 20 V) on the left axis or in mV on the right axis. The vertical axis indicates the magnitude of the output voltage swing. ERROR - mV 410 —8 —6 —A -2 0 +2 +4 +6 +3 +10 OUTPUT VOLTAGE SWING - v Figure 2, Gain Nonlinearity Error (% p—p Output Range and WW Vs. Output Voltage Swing (V), with a Gain of 1 V/V Parameter Rey Specifications As a Function of Shown 1n Gain Gain (ppm of Span) Temperature ("C) Figure l Gain Nonlinearity (Expressed in mV Output Voltage Swing (V) Figure 2 and % of 1%}: Output) Input Voltage Rating Common Mode Rejection (dB) Common Mode Signal Frequency Figure 3 (Hz), Amplifier Gain (VN) and Input Source Resistance (0) Input Noise Input Noise (nV/vfiE) Frequency (Hz) Figure 4 Frequency Response Frequency Response: Gain (dB) Frequency (Hz) Figure 5 Frequency Response: Phase Shirt (Degree) Frequency (1-12) Figure 6 Dynamic Response N/A Figure 7 Offset Output Oflset Voltage (mV) Temperature (°C) Figure 8 Rated Out Output Voltage Swing (V) Supply Voltage (V dc) Figure 9 Output Cunenl (mA) Supply Voltage (V dc) Figure 10 Isolated Power Supply Isolated Power Supply Voltage (V) Current Delivered to the Load (rnA) Figure 11 Isolated Power Supply Ripple (mV p—p) ()lrrent Delivered to the Load (mA) Figure 12 Isolated Power Supply Ripple (v p—p) Bypass Capacitance (uF) Figure 13 Table 1. Performance Characteristics Detailed in the ADZDJSN Data Sheet
PERFORMANCE CHARACTERISTICS
This section details the key specifications of the AD203SN that
exhibit a functional dependence on such variables
as
frequency,
power supply load, output voltage swing, bypass capacitance
and temperature. Table I summarizes the performance charac-
teristics that will be discussed in this section. For the sake of
completeness, a typical dynamic output response of the
AD203SN
is
included.
Gain Temperature Coefficient. Figure 1 presents the
AD203SN's gain temperature coefficient over the entire
-55°C
to +
125°C
temperature range.
0.5k
-1k
/
-2k
E
-3k
c.
c.
I
-4k
2
<i
(!)
-5k
-6k
-7k
-Bk
I
I
I
I
I
I
-55
-40 -25
II"
+25 +85
+125
TEMPERATURE
-"C
Figure
1.
Gain {ppm
of
Span)
vs.
Temperature
(°C)
Note: 1 ppm (part per million)
is
equivalent to 0.0001
%.
Parameter Key Specifications
Gain Gain (ppm of Span)
Gain Nonlinearity (Expressed in mV
and % of
p-p
Output)
Input Voltage Rating Common Mode Rejection (dB)
Input Noise Input Noise (nV/VHz)
Frequency Response Frequency Response: Gain (dB)
AD203SN
Gain Nonlinearity. The maximum nonlinearity error of the
AD203SN, at a gain of 1
VIV,
is
specified
as
±0.025% or
± 5 m
V.
The nonlinearity performance of the AD203SN
is
de-
pendent on the output voltage swing and this dependency
is
il-
lustrated in Figure
2.
The horizontal axis represents the gain
error, expressed either in percent of peak-to-peak output span
(i.e., % of
20
V)
on the left axis or in mV on the right axis. The
vertical axis indicates the magnitude of the output voltage
swing.
+0.02
#.
+0.01
I
a:
0
0
~
-0.01
w
-0.02
-10
-8
-6 -4
-2
0
+2
+4
+6 +8
+10
OUTPUT VOLTAGE SWING
-V
+4
+2
0
-2
-4
>
E
I
a:
0
a:
a:
w
Figure
2.
Gain
Nonlinearity
Error
(%
p-p
Output
Range
and
mV)
vs.
Output
Voltage
Swing
(V),
with
a Gain
of
1 VIV
As
a Function
of
Shown
In
Temperature (0C) Figure 1
Output Voltage Swing
(V)
Figure 2
Common Mode Signal Frequency Figure 3
(Hz), Amplifier Gain
(VIV)
and
Input Source Resistance (!1)
Frequency (Hz) Figure 4
Frequency (Hz) Figure 5
Frequency Response: Phase Shift (Degree) Frequency (Hz) Figure 6
Dynamic Response
NIA
Figure 7
Offset Output Offset Voltage (mV) Temperature (0C) Figure 8
Rated Out Output Voltage Swing
(V)
Supply Voltage
(V
de) Figure 9
Output Current (mA) Supply Voltage
(V
de) Figure
10
Isolated Power Supply Isolated Power Supply Voltage
(V)
Current Delivered to the Load (mA) Figure
11
Isolated Power Supply Ripple (m V p-p) Current Delivered to the Load (mA) Figure
12
Isolated Power Supply Ripple
(V
p-p) Bypass Capacitance (µF) Figure
13
Table
I.
Performance Characteristics Detailed in the AD203SN Data Sheet
-5-
Rev. B
ADZfl3SN Common Mode Rejection. Figure 3 illustrates the common mode rejection (CMR), expressed in dB, of the ADZOBSN versus frequency (Hz), gain WW) and source impedance imbal- ance (in. To achieve the optimal common mode rejection of unwanted signals, it is recommended that the source imbalance be kept as low as possible and that the input circuitry be care- fully inid uul so as [0 avoid adding excessive stray capacitances at the isolator’s input terminal; in I39 tzo onwmn Moos lEJEflION A d! 3 10 mo moo meousucv . Mr mm Figure 3. Common Mode Rejection (6MB) vs. Frequency (Hz), Gain (WV) and Resistance ((2) Input Noire. Figure 4 presents the typical input noise charac- teristics, in nV/VHz, of the ADZOSSN tor it frequency range from 1 Hz to 100 kHz. lonn ion to lNPUV NOISE voUAGE A HVW too mnumcv . N! it let look Figure 4. Input Noise rnV/x/l-E) vs. Frequency (Hz) Frequency Response: Gain and Phase Shifl. Figure 5 illus- trates the ADZOSSN’s gain as a iunction of frequency while Fig- ure 6 illustrates the corresponding phase shift vs. frequency. The ADZOSSN’S low phase shift and 10 kHz bandwidth perfor- mute make it ideal in power monitoring and control system applications. Grtwwv cm _ an tit Frequency . Hx son Ion Figure 5‘ Gain (dB) as a Function of Frequency (Hz) mes 6:: WV Eiéi: was: G=IIIDVIV ms: rum 4 nit"... it.itii §§§§S§§ 5w 1k Frizuusucv , nz Ink Figure 6. Phase Shift M") as a Function of Frequency (Hz) Dynamic Response or the ADzoaSN, To illustrate the speed, dynamic range and rapid settling tune of the ADzossN, the iso- lator’s output response to a 20 V p—p step function is shown in Figure 7. Figure 7. Dynamic Response of the ADZHESN (20 V p—p Step)
AD203SN
Common
Mode
Rejection. Figure 3 illustrates the common
mode rejection (CMR), expressed in dB,
of
the AD203SN
versus frequency (Hz), gain
(VIV)
and source impedance imbal-
ance (D).
To
achieve the optimal common mode rejection
of
unwanted signals, it
is
recommended that the source imbalance
be kept as low
as
possible and that the input circuitry be care-
fully laid out
so
as
to avoid adding excessive stray capacitances
at the isolator's input terminals.
140 '
"'
130
.,,
I 120
2
~
110
<..>
w
...,
100
w
a:
90
w
Q
0
80
:;;
2 70
0
:;;
60
:;;
0
50
<..>
-,
-.........
.....
'-.
'-,
-"'r-.
lls~O"'"
....
...
-
....
~
-
......
11.,,,0
-
~
.........
....
"
-..........:
lis~so;
.........._
--~"1ok
-
...
-"-
....
r-......
......
-
11.*
....
r--
...
....
.........._
--
-....._
....
40
-G=1
--G=100
10 100 1000 10000
FREQUENCY -
Hz
Figure
3.
Common
Mode
Rejection (CMR)
vs.
Frequency
(Hz),
Gain
(VN)
and
Resistance {[})
Input
Noise. Figure 4 presents the typical input noise charac-
teristics, in
nV/VHz,
of
the AD203SN for a frequency range
from 1
Hz
to
100
kHz.
1000
~
>
c
~
100
t!J
;::
cl
>
w
CJ)
i5
2
,_ 10
::0
0.
~
1
......
1
I'
....
..
_
~
10 100 1k 10k 100k
FREQUENCY -Hz
Figure
4.
Input
Noise
(nVl\!Hz)
vs.
Frequency
(Hz)
Frequency
Response:
Gain
and Phase Shift. Figure 5 illus-
trates the AD203SN's gain
as
a function
of
frequency while Fig-
ure 6 illustrates the corresponding phase shift vs. frequency.
The
AD203SN's low phase shift and
10
kHz
bandwidth perfor-
mance make it ideal in power monitoring and control system
applications.
-6-
50
40
30
20
10
-10
-20
-30
-40
-50
-60
-70
I
500
I
I
G=100V/V
G=1V/V
1k
FREQUENCY -
Hz
~'"
\.
\
~
'\
\ \
10k 50k
Figure
5.
Gain (dB) as a Function
of
Frequency
(Hz)
-30
-60
*
-90
m
-120
~
~
-150
,_
!:!:
-180
:i:
~
-210
CJ)
:i:
-240
0.
-270
-300
-330
I
I
I
~
PHASE
G=1
VIV
~I
~
I I
PHASE
G=100V/V
r\\
\
\
~
~
I I
500 1k 10k 50k
FREQUENCY -
Hz
Figure
6.
Phase
Shift
(.1°)
as a Function
of
Frequency
{Hz)
Dynamic Response
of
the AD203SN.
To
illustrate the speed,
dynamic range and rapid settling time
of
the AD203SN, the iso-
lator's output response to a
20
V
p-p
step function
is
shown in
Figure
7.
Figure
7.
Dynamic
Response
of
the AD203SN (20 V
p-p
Step}
Rev. B
ADZfl3SN Output offset Voltaget The ADZOSSN exhibits a low output offset voltage temperature coefficient over the +ZS”C to +125"C temperature range as shown in Figure 8. WIN! emu VOLYmE . mV 75540725 0 .25 as ms IEMPEIM‘IIIRE _ c Figure 8. Output Offset Voltage mm vs. Temperature (“'0 with 5:1 V/V nuwuv VOLYIGE SWVM _ xv w n 1: l3 u sun-u vamoe , v be IS is Figure 9, Output Voltage Swing (: V) vs. Power Supply Input Voltage (V DC), with a 2.5 kg Load —sse IO t125'c ourvur CURREM 4 MA '25‘C 10 mm *5 u 15 M5 ms sumv vomct . v DC ISOO Figure 10, Output Current (mA; vs. Supply Voltage (v DC) and Temperature (“CL with M50 Loaded at 5 mA Rated Output, The rated output voltage, Across the OUT HI and OUT L0 terminals, for [he ADZOESN is specified at :10 V. This specification applies when the ADZOSSN is pow- ered by at +15 V dc supply The rated output voltage level is, however, affected by the input power supply voltage and the loads placed on the isohled power supply. This dependency is illustrated in Figure 9. The current delivered by the output terminals of the ADZOSSN will vary as a function of the supply voltage and operating tem perature. These relationships are illustrated in Figure 10. Isolated Power. The load characteristics of the ADZOfiSN‘s iso- lated power supplies (i.e., +15 V dc and *15 V dc) are plotted in Figure 11. The isolated power supply exhibits some ripple which varies as a function of the load current Figure 12 demonstrates this relntionshipt The ADzosSN has internal bypass capacitors that optimize the rtadeotf between output ripple and power supply performance, even under full load, If a specific application requires more bypassing on the isolated power supplies, external capacitors may be added Figure 13 plots the isolated power supply ripple as a function of external bypass capacitance under {on load conditions (i.e., 5 mA). \ ,u isotArED POWER sumv VoLrAGE v v m: :5 2w ‘5 LOAD , mA Figure 11. Isolated Power Supply Voltage (V DC) vsv Load lmA} A r > 7‘“ / H a 7v“ / 5 I] '5‘ // “’W gm 5 a 5 u 1 a 5 7 m n my-” Figure 12‘ Isolated Power Supply Ripple {mV p47) Vs. Load lmAl
Output Offset Voltage. The AD203SN exhibits a low output
offset voltage temperature coefficient over the +
25°C
to +
125°C
temperature range
as
shown in Figure
8.
>
E
I
w
~
2
~
,_
w
ff
~
-2
,_
:>
~
-4
:>
0
-6
-8
\
I\
\.
i'-...
~
.........
'
'\
\
-55 -40 -25
+25 +85
+125
TEMPERATURE -
°C
Figure
8.
Output
Offset
Voltage rmV)
vs.
Temperature
r°C)
with
G=1
VN
>
ti
13
12
I 11
(!)
z
ii:
10
"'
w
~
9
0
> 8
,_
:>
0.
5 7
0
~v
/
..,,,..,
~=+10V
.J'......-
/ /
.....
v v
~/
V0
=-10V
/
10
11
12
13
14
15
16
SUPPLY VOLTAGE - V
DC
Figure
9.
Output
Voltage
Swing
r±V)
vs.
Power
Supply
Input
Voltage
(V
DC),
with
a 2.5
kn
Load
V0
=+10
V
-55°C
TO
+125°C
~
2
1--------+-----+----------j
,_ 1
1--------+-----+----------j
i'E
a:
a:
:>
t.>
5
-1
1--------+-----+----------j
e:
V0
=-10
V
i5
-2
~-----+------+----------j
-5L._
___
----1.
____
__L
__
_:::::,,,,,_,
14.25 14.5 14.75 15.00
SUPPLY
VOLTAGE-V
DC
Figure
10.
Output
Current
rmA)
vs.
Supply
Voltage
(V
DC)
and
Temperature
r°C),
with
V
150
Loaded
at
5
mA
-7-
AD203SN
Rated Output. The rated output voltage, across the
OUT
HI
and
OUT
LO terminals, for the AD203SN
is
specified at
±IO
V.
This specification applies when the AD203SN is pow-
ered by a +
15
V de supply. The rated output voltage level is,
however, affected by the input power supply voltage and the
loads placed on the isolated power supply. This dependency
is
illustrated in Figure
9.
The
current delivered by the output terminals
of
the AD203SN
will vary
as
a function of the supply voltage and operating tem-
perature. These relationships are illustrated in Figure
IO.
Isolated Power. The load characteristics
of
the AD203SN's iso-
lated power supplies (i.e., +
15
V de and
-15
V de) are plotted
in Figure
11.
The isolated power supply exhibits some ripple which varies
as
a function of the load current. Figure
12
demonstrates this
relationship.
The
AD203SN has internal bypass capacitors that
optimize the tradeoff between output ripple and power supply
performance, even under full load.
If
a specific application
requires more bypassing on the isolated power supplies, external
capacitors may be added. Figure
13
plots the isolated power
supply ripple
as
a function of external bypass capacitance under
full load conditions (i.e., 5 mA).
t.>
~
±15~------=F"""'-..~--+-----~
I
w
~
0
>
±14
1--------+-----~------t
'.'.;
0.
0.
:>
"'
a:
w
~
±13
1---------+-----+--·-----t
0.
fil
,_
:5
0
'!?
±1
±5
±10
±15
LOAD -
mA
Figure
11.
Isolated
Power
Supply
Voltage
(V
DC)
vs.
Load
rmA)
~
>
7
40~-+--+-----+---+-~~-~
~
0.
0.
ii:
~
30~-+-~-i""'-~"--t----t----~
0.
0.
:>
"'
a:
~
201£---+--+----+---+----~
~
0
w
:;;:
5
101----+---+-----+---+----+---I
'!?
10
11
LOAD-
mA
Figure
12.
Isolated
Power
Supply
Ripple
rmv
p-p)
vs.
Load
rmA)
Rev. B
ADZI]3SN ooo § .ur isomto mwza SUFFIV nmt .nv rep at . to u» “we GMAEIYAME - or Figure 13 Isolated Power Supply Hippie {mV P—P) vs. Ey- pass Capacitance {pf}, with a 5 mA Load on iv“, and Noise Bandwidth of 1 MHz. The curves in Figures 12 and 13 were generated by measuring the power supply ripple over a 1 MHz bandwidth. CAUTION: The AD203SN does not provide for short circuit protection of its isolated power supply. A current limiting resis- tor my be placed in series with the isolated power terminals and the load in order to pmtect the supply against inadvertent shorts. APPLICABLE STANDARDS The tests and methods employed in the design verification pm- oess ate summarized in Table II. A copy oi the AD203SN Qual- ity G! Reliability Summaries test report, which documents the results of the tests listed in Table II, is available on request. Test Method Test Description MILVSTDVSSBC, Method 1004 MIL»STD»883C, Mediod 1010 Condition B MIL»STD-883C, Method 2002, Condition B MlL-STD»833C, Method 2003 MIL-STD-833C, Method 2004 MIL-STD-SXSC, Method 2007, Condition A MIL-STD-883C, Method 2015 MlL-STD-883C, Method 3015.5 Analog Devices Product Reliability Program Moisture Resistance Temperature Cycling, eSS‘C to + 125°C Mechanical Shock @: 1,500 g for 05 ms Solderability of Terminations Integrity of Microelectronic Device Leads Variable Frequency Vibration @ 20 g Resistance to Solvents Electrostatic Discharge Sensitivity Classification MTBF Calculation (per MIL»HDBK-217D) and Verification Table II. Tests Used to Verify the Huggedness, Reliability and Quality of the ADZQ3SN Design Per 883C Method 3015.5, the ADZOSSN has been classified as a Class 2 ESD (electrostatic discharge) sensitive device. As 2 Class 2 device, the AD203SN is insensitive to static discharge voltages of less than 2000 V. INSIDE THE AD203SN The functional block diagram of the ADZO3SN is shown in Fig» ute 14. The ADzosSN employs amplitude modulation tech- niques to implement transformer coupling of signals down to dc. The 35 kHz, 30 v p—p square wave carrier used by the ADZOBSN is generated by an internal oscillator located in the » output port of the isolator. This oscillator is powered by at +15 V dc supply. A full wave modulator translates the input Signal to the earlier frequency which is then transmitted across transformer T1. The synchronous demodulator in the output port extracts the input signal {tom the carrier, The 12 kHz two-pole filter is employed to minimize output noise and ripple. Furthermore, the filter serves as a low impedance Output hurtet. The input port of die AD203SN contains an uncommitted input op amp, a modulator and the power transformer T2. The pri- mary or the power transformer is driven by the 35 kHz square wave while the secondary, in coniunction with a rectifier net- work, supplies isolated power to the modulator, input op amp and any external load. The uncommitted input amplifier can be used to supply gain or to buffer the input signals, nmuwuvw l! nmmro—l Hm..." mm Figure 14. Functional Eloclt Diagram USING THE ADZIBSN Powering the ADZOSSN. The ADZOSSN requires only a single +15 v dc power supply connected as shown in Figure 15. A bypass capacitor is provided in the module. @_ @— mum HIVDCYD mv or: sham em 00M sumv oowaon Figure 15, Powering the AD203SN Unity Gain Input Configuration. The basic unity gain config- uration tor input signals of up to :10 v is shown in Figure 16. Figure 16. Basic Unity Gain Configuration
AD203SN
1000
~
>
E
I 200
w
~
0.
9:
100
"'
'.'.;
it
"
"'
"'
20
~
~
10
c
~
~
1
~...._
"""
'r--.r-.
"r--..._
0.1
10
BYPASS
CAPACITANCE
-µF
100
Figure
13.
Isolated
Power
Supply
Ripple
(mV
p-p}
vs.
By-
pass Capacitance (µF),
with
a 5
mA
Load
on
± V
150
,
and
Noise
Bandwidth
of
1 MHz.
The
curves in Figures
12
and
13
were generated by measuring
the power supply ripple over a 1 MHz bandwidth.
CAUTION:
The
AD203SN does not provide for short circuit
protection
of
its isolated power supply. A current limiting resis-
tor may be placed in series with the isolated power terminals
and the load in order to protect the supply against inadvertent
shorts.
APPLICABLE STANDARDS
The
tests and methods employed in the design verification pro-
cess are summarized in Table II. A copy
of
the
AD203SN
Qual-
ity & Reliability Summaries test report, which documents the
results
of
the tests listed in Table
II,
is
available on request.
Test Method
MIL-STD-883C, Method 1004
MIL-STD-883C, Method
1010
Condition B
MIL-STD-883C, Method 2002,
Condition B
MIL-STD-883C, Method 2003
MIL-STD-883C, Method 2004
MIL-STD-883C, Method 2007,
Condition A
MIL-STD-883C, Method
2015
MIL-STD-883C, Method 3015.5
Analog Devices Product
Reliability Program
Test Description
Moisture Resistance
Temperature Cycling, -
55°C
to +
125°C
Mechanical
Shock@
1,500 g
for 0.5 ms
Solderability
of
Terminations
Integrity of Microelectronic
Device Leads
Variable Frequency Vibration
@20
g
Resistance to Solvents
Electrostatic Discharge
Sensitivity Classification
MTBF
Calculation (per
MIL-HDBK-217D)
and Verification
Table
II.
Tests Used to Verify the Ruggedness,
Reliability
and
Quality
of
the AD203SN Design
Per 883C Method 3015.5, the AD203SN has been classified
as
a
Class 2 ESD (electrostatic discharge) sensitive device.
As
a Class
2 device, the AD203SN
is
insensitive to static discharge voltages
of
less than 2000
V.
INSIDE THE AD203SN
The
functional block diagram of the AD203SN
is
shown in Fig-
ure
14.
The
AD203SN employs amplitude modulation tech-
niques to implement transformer coupling
of
signals down to de.
The
35
kHz,
30
V
p-p
square wave carrier used by the
AD203SN
is
generated by an internal oscillator located in the
· output port
of
the isolator. This oscillator
is
powered by a
+
15
V de supply.
-8-
A full wave modulator translates the input signal to the carrier
frequency which is then transmitted across transformer
Tl.
The
synchronous demodulator in the output port extracts the input
signal from the carrier.
The
12
kHz two-pole filter
is
employed
to minimize output noise and ripple. Furthermore, the filter
serves
as
a low impedance output buffer.
The
input port of the AD203SN contains an uncommitted input
op amp, a modulator and the power transformer T2. The pri-
mary
of
the power transformer
is
driven by the
35
kHz
square
wave while the secondary, in conjunction with a rectifier net-
work, supplies isolated power to the modulator, input op amp
and any external load. The uncommitted input amplifier can be
used to supply gain or to buffer the input signals.
AD203SN
MODULATOR
T1
'.
'I
''
POWER
-.
DEMODULATOR
12
kHz
LP
FILTER
& OUTPUT
BUFFER
OSCILLATOR
t-41-----i
Ill
35kHz
'I
INPUT
PORT~
~OUTPUT
PORT
Figure
14.
Functional Block
Diagram
USING
THE AD203SN
Powering the AD203SN.
The
AD203SN requires only a single
+
15
V de power supply connected
as
shown in Figure
15.
A
bypass capacitor
is
provided in the module.
PWRIN
+12VDCTO
+16
V
DC
SUPPLY
PWRCOM
SUPPLY
COMMON
Figure
15.
Powering
the AD203SN
Unity Gain Input Configuration.
The
basic unity gain config-
uration for input signals
of
up
to ±
10
V
is
shown in Figure
16.
Vs1GNAL
(±10V)
Figure
16.
Basic
Unity
Gain
Configuration
Rev. B
ADZO3SN Input Configuration for a Gain Greater Than 1 (G>1). When small input signal levels must be amplified and isolated, Figure 17 shows how to get a gain greater than 1 while continuing to preserve a very high input impedance. In this circuit, the gain equation may be written as: Va = ll+Rp/Rol>
Input Configuration for a Gain Greater Than I (G > 1). When
small input signal levels must be amplified and isolated, Figure
17
shows how to get a gain greater than 1 while continuing to
preserve a very high input impedance.
In this circuit, the gain equation may be written
as:
where
V 0 Output Voltage
(V)
V
srG
Input Signal Voltage
(V)
RF
Feedback Resistor Value
(!1)
RG
= Gain Resistor Value (!1).
Note on the 100 pF Capacitor. Whenever a gain of
50
VIV
or
greater
is
required, a
100
pF
capacitor from the FB (input op
amp feedback) terminal to the
IN
COM (input common) termi-
nal,
as
shown with the dotted lines in Figure 17,
is
highly rec-
ommended.
The
capacitor acts to filter out switching noise and
will minimize the isolator's nonlinearity parameter.
Figure
17.
Input
Configuration
for
a Gain Greater than 1
Compensating the Uncommitted Input
Op
Amp.
The
open
loop gain and phase versus frequency for the uncommitted input
op amp are given in Figure
18.
These curves are to be used to
determine the appropriate values for the feedback resistor and
compensation capacitor in order to ensure frequency stability
when a gain greater than unity
is
required.
The
final values for
these components should also be chosen
so
as
to satisfy the
fol-
lowing constraints:
The
current drawn in the feedback resistor (Rp) is no greater
than 1 mA.
The
feedback (Rp) and gain resistor
(RG)
result in the desired
amplifier gain.
+ 100
+100°
',
+80
+80°
\
"'
\
~
.,,
\
+60°
~
I
+60
2 \
;; "
" \
~
~
+40
\
+40°
~
g \ "
\
0:
"
~
I
:;
0
+20
1
+200
~
ii:
-20
~-~-~-~-~--~-~
-20°
10 100
lk
10k 100k
1M
lOM
FREQUENCY -Hz
Figure
18.
Open
Loop
Gain
and
Phase
vs.
Frequency
for
the
Uncommitted
Input
Op
Amp
-9-
AD203SN
Inverting, Summing or Current Input Configuration. Figure
19
shows how the AD203SN can accommodate current inputs or
sum currents or voltages.
Figure
19.
Input
Configuration
for
Summing
or
Current
Input
In this circuit the output voltage equation can be written
as:
Vo=
-Rpx(Is+Vs1!Rs1+Vs2!Rs2+
... )
where
V 0 Output Voltage
(V)
V si Voltage of Input Signal 1
(V)
V
sz
Voltage of Input Signal 2
(V)
Is Input Current Source
(A)
RF
Feedback Resistor Value
(!1)
Source Resistance Associated with Input
Rs1 Signal 1
(!1)
Source Resistance Associated with Input
Rs2 Signal 2 (!1).
The
circuit of Figure
19
can also be used when the input signal
is
larger than the ±
10
V input range of the isolator. For exam-
ple, suppose that in Figure
19
only V s1, Rs1 and
RF
are con-
nected to the feedback, input and common terminals
as
shown
by the solid lines in Figure
19.
Now, a Vs 1 with a ±100 V span
can be accommodated with Rp =
20
k!1
and a total
Rs1 =200 k!1.
GAIN
AND
OFFSET ADJUSTMENTS
General Comments. When gain and offset adjustments are
required, the actual compensation circuit ultimately utilized will
depend on:
The
input configuration mode of the isolation amplifier
(i.e., noninverting or inverting).
The
placement of the adjusting potentiometer (i.e., on the
isolator's input or output side).
As
a general rule:
Offset adjustments are best accomplished on the isolator's in-
put
side,
as
it is much easier and more efficient to null the
offset ahead of any gain.
Gain adjustments are mostly easily accomplished
as
part of
the gain-setting resistor network at the isolator's input side.
Input adjustments, of the offset and/or gain, are preferred
when the adjusting potentiometers are
as
near
as
possible to
the input end of the isolator
(so
as
to minimize strays).
Output side adjustments may be necessary under the
conditions where adjusting potentiometers placed on the
input side would present a hazard to the user due to the
presence of high common mode voltages during the adjust-
ment procedure.
Rev. B
ADZIJ3SN o It is recommended that the offset adjustment precedes the gain adjustment. Adjustments for the Noninverfing Mode of Operation Offset Adjustment Figure 20 shows the suggested input adjust- ment connections when the isolator’s input amplifier is config- ured for the noninverting mode of operation The offset adjust- ment circuit injects a small voltage in series with the low side of the signal source. The adjustment potentiometer P1 modulates the injection voltage and is therefore responsible for nullmg out the offset voltage. Nch: 0 To minimize CMR degradation it is recommended that the resistor in series with the input L0 (i.e., RC) be below a few hundred ohms. 0 The offset adjustment circuit of Figure 20 will not work if the signal source has another current path to input common, or if current flows in the signal source L0 lead. If this is the case, use the output adjustment procedure. Gain Adjustment. Figure 20 also shows the suggested gain adjustment circuit. Note that the gain adjustment potentiometer P2 is incorporated into the gain-setting resistor network at the isolator’s input. Figure 20. Input Adjustments for the Noninvem‘ng Mode of Operation An RGA of 47.5 1(5). and a 5 kit potentiometer, resulting in a median RF value of 50 kn. (it, Rom + PZ/Z), will Work nicely for gains of 10 VN or greater. The gain adjusnnent becomes less effective at lower gains, in fact it is halved at (3:2 VN, so that potentiometer P2 will have to be a larger fraction of the total RF. At a gain of l VN attempting to adjust the gain down- wards Will compromise the isolator's input impedance. In this case it would be better to adjust the gain at the signal source or after the output. Input Adjustments for the Invem'ng Mode of Operation Offset Adjustment. Figure 21 shows the suggesred input adjust- ment connections when the isolator’s input amplifier is config- om mum VFigure 21. Input Adjustments for the Inverting Mode of Operation ured for the inverting mode of operation. Here the offset adiust- ment potentiometer P1 nulls the voltage at the summing node. This method is preferred over current injection since it is less affected by any subsequent gain adjustments. Gain Adjustment. Figure 21 also shows the suggested gain adjustment circuit In this circuit, the gain adjustment is made in the feedback loop using potentiometer P2. The adjustments will be effective for all guns In the l to 100 VN range. Output Adjustments Offset Adjustment. Figure 22 shows the recommended tech- nique for offset adjustment at the output. In this circuit, the :15 V dc voltage is supplied by an independent source. With reference to the output circuin shown in Figure 22, the mnxi- mum offset adjustment range is given by: RDXVS RD+R0 where, vS is are power supply volugc. A 20 kt} potentiometer (P0) should Work well in this adjustment circuit. EoFFsET = Figure 22. Output Side Offset Adjustment Circuit Gain Adjustment. Since the ADZOSSN’s output amplifier is fixed at unity, any desired output gain adjustments can only be made in a subsequent stage USING ISOLATED POWER The ADZOSSN provides :15 V dc power outputs referred to the input common. These may he used to power various acces» sory ClI‘C‘UiIS which must operate at the input common mode level. The input offset adjusunent circuits of the previous sec- tion are examples of this need. The isolated power supply output has a current capacity of 5 rnA which should be sufficient to operate adjustment circuits, references, op amps, signal conditioners and remote transducers. CAUTION: The AD203SN does not provide for short circuit protection of its isolated power supply. A current limiting resis- tor may be placed in series with the isolated power terminals and the load in order to protect the supply against inadvertent shorts. APPLICATIONS EXAMPLES Isolated Process Current to Voltage Convener Figure 23 shows how the ADZOSSN can be utilized as an iso- lated receiver that translates a 4—20 mA process current signal input into a 0 to +10 V output. The 25 {t shunt resistor con- verts the 4-20 mA current into a +100 to +500 mV signal. The signal is then offset by - 100 mV via the use of P0 to produce a 0 to +400 mV input. The signal is then amplified by a gain of 25 resulting in the desired 0 to +10 V output. With an open circuit on the input side, the ADZOBSN will have -Z.5 V on the output, corresponding to the 7100 mV offset voltage multiplied by a gain onS V/V. .10-
AD203SN
It
is recommended that the offset adjustment precedes the
gain adjustment.
Adjustments for the Noninverting Mode
of
Operation
Offset Adjustment. Figure
20
shows the suggested input adjust-
ment connections when the isolator's input amplifier is config-
ured for the noninverting mode of operation. The offset adjust-
ment circuit injects a small voltage in series with the low side of
the signal source.
The
adjustment potentiometer
Pl
modulates
the injection voltage and
is
therefore responsible for nulling out
the offset voltage.
Note:
To
minimize CMR degradation it is recommended that
the resistor in series with the input LO (i.e.,
Re)
be
below a
few
hundred ohms.
The
offset adjustment circuit of Figure
20
will not
work
if
the signal source has another current path to
input common, or
if
current flows in the signal source
LO
lead.
If
this
is
the case, use the output adjustment
procedure.
Gain Adjustment. Figure
20
also shows the suggested gain
adjustment circuit. Note that the gain adjustment potentiometer
P2
is
incorporated into the gain-setting resistor network at the
isolator's input.
GAIN
ADJUST
Figure 20.
Input
Adjustments
for
the
Noninverting
Mode
of
Operation
An
RGA
of 47.5
kf!
and a 5
kf!
potentiometer, resulting in a
median
RF
value
of
50
kf! (i.e.,
RGA
+ P2/2), will work nicely
for gains of
10
VN
or greater.
The
gain adjustment becomes
less effective at lower gains, in fact it
is
halved at
G=2
VN,
so
that potentiometer P2 will have to be a larger fraction of the
total Rp. At a gain of 1
VN
attempting to adjust the gain down-
wards will compromise the isolator's input impedance. In this
case it would be better to adjust the gain at the signal source or
after the output.
Input Adjustments for the Inverting Mode
of
Operation
Offset Adjustment. Figure
21
shows the suggested input adjust-
ment connections when the isolator's input amplifier
is
config-
GAIN ADJUST
Figure 21.
Input
Adjustments
for
the Inverting
Mode
of
Operation
ured for the inverting mode
of
operation. Here the offset adjust-
ment potentiometer
Pl
nulls the voltage at the summing node.
This method is preferred over current injection since it
is
less
affected by any subsequent gain adjustments.
Gain Adjustment. Figure
21
also shows the suggested gain
adjustment circuit.
In
this circuit, the gain adjustment
is
made
in the feedback loop using potentiometer P2.
The
adjustments
will be effective for all gains in the 1 to
100
VN
range.
Output Adjustments
Offset Adjustment. Figure
22
shows the recommended tech-
nique for offset adjustment at the output. In this circuit, the
±
15
V de voltage is supplied by an independent source. With
reference to the output circuitry shown in Figure 22, the maxi-
mum offset adjustment range is given by:
RDxVs
EoFFSET =
RD+
Ro
where, Vs
is
the power supply voltage. A
20
kf!
potentiometer
(P
0) should work well in this adjustment circuit.
OUTHI
OUT
ATN
PWRIN
(+12V
TO
+16V
DC)
PWRCOM
+15V
ZERO t
ADJUST Po
Ro
-15V
Figure
22.
Output
Side Offset
Adjustment
Circuit
Gain Adjustment. Since the AD203SN's output amplifier
is
fixed at unity, any desired output gain adjustments can only be
made in a subsequent stage.
USING
ISOLATED POWER
The
AD203SN provides ±
15
V de power outputs referred to
the input common. These may be used to power various acces-
sory circuits which must operate at the input common mode
level.
The
input offset adjustment circuits of the previous sec-
tion are examples of this need.
The
isolated power supply output has a current capacity of
5 mA which should be sufficient to operate adjustment circuits,
references, op amps, signal conditioners and remote transducers.
CAUTION:
The
AD203SN does not provide for short circuit
protection of its isolated power supply. A current limiting resis-
tor may be placed in series with the isolated power terminals
and the load in order to protect the supply against inadvertent
shorts.
APPLICATIONS EXAMPLES
Isolated Process Current to Voltage Converter
Figure
23
shows how the AD203SN can be utilized
as
an iso-
lated receiver that translates a 4-20 mA process current signal
input into a 0 to +
10
V output.
The
25
n shunt resistor con-
verts the 4-20 mA current into a +
100
to +500 mV signal.
The
signal
is
then offset by -
100
m V via the use
of
P
0 to produce a
0 to +400 mV input. The signal
is
then amplified by a gain of
25
resulting in the desired 0 to +
10
V output. With an open
circuit on the input side, the AD203SN will have -2.5 V on the
output, corresponding to the
-100
mV offset voltage multiplied
by a gain of
25
VN.
-10-
Rev. B
ADZU3$N I15”) aw to I“ Figure 23. Using the ADZOaSN as an Isolated Process Current to Voltage Converter For the circuit of Figure 23, the input to output transfer func- tion can he expressed as: Vow = 625 leezj V where vOUT : Output Voltage (V) lm Input Current in mflliamps (nth). This current is Limited to the 4 to 20 mA range. Current Shunt Measurements In addition to isolating and converting process current signals into voltage signals, the ADZOSSN can be used to indicate the value of any loop current in general, Figure 24 illustrates a typi- cal current shunt measurement application of the AD203SN. A small sensing resistor Rsmm-r, placed in series with the current loop, develops a small differential voltage that may be further scaled to provide an isolator output voltage that is directly pror - portions] to the current. The voltage developed across the shunt can potentially be several hundred to a thousand volts above ground, In this circuit, the ADZOSSN provides the necessary scaling of the shunt signal while providing high common-mode voltage isolation and high common mode rejection of do and 60 Hz components. ADZoisN Figure 24, Using the ADQOSSN for Current Shunt Measurements The transfer function for the circuit of Figure 24 can be written us: Vow : Rsppmx (I +Rp/Rgt xILoop where V0,“. : Output Voltage (V) . RSHUNT : Sense or Current Shunt Resistance (.0) RF = Feedback Resistance (0) RC = Gain Resistance (.fl.) ILoop = Loop Current (A). Low Level Inputs In applications Where low level signals need to be isolated (ther- mocouples are one such application), a low drift input amplifier can be used with the ADZOSSN. Figure 25 illustrates this impler mentalion of the AD203SN. The circuit design also includes a three-pole active filter which provides for enhanced common mode rejection at 60 Hz and normal mode rejection of frequen- cies above a few Hz. If any offset adjustments are desired, they are best done at the trim pins of the low drift input amplifier. Gain adjusu-nents can be done at the feedback resistor. exist-mt H mm I ioizvra «veer mum Figure 25. Using the AD203SN with Low Level Inputs The input-output relationship for the circuit shown in Figure 25 can be written as: Vow = me 11 +50 Ten/R6! - Output Voltage (V) 7 Low Level Input Voltage (V) IsolaLion Amplifier Gain Resistance (0). Noise Reduction in Data Acquis ‘on Systems The ADZO3SN uses amplitude modulation techniques with a 35 kHz carrier to pass both ac and dc signals across the isolation barrier. Some of the carrier’s harmonics are unavoidably passed through to the isolator output in the form of ripple. In most cases, this noise source is insignificant when compared to the measured signal. However, in some applications, particularly when a fast A/D converter is used following the isolator, it may be desirable to add filtering at the isohtor‘s output in order to reduce the carrier ripple. Figure 26 shows a circuit that will reduce the carrier ripple through the use of a two-pole output filter. mpFrI‘i o >-i H v... own In! tar low-FT mm o amt mum.“ Yousvncl WW common men sun” Figure 26, Noise Reduction in Data Acquisition Systems Using the AD203SN
Figure 23.
Using
the AD203SN as an Isolated Process
Current
to
Voltage
Converter
For the circuit of Figure 23, the input to output transfer func-
tion can be expressed
as:
where
VouT
IrN
Vour
=
625
xJJN-2.5
V
Output Voltage
(V)
Input Current in milliamps (mA). This current
is
limited to the 4 to
20
mA range.
Current Shunt Measurements
In
addition to isolating and converting process current signals
into voltage signals, the AD203SN can be used to indicate the
value of any loop current in general. Figure
24
illustrates a typi-
cal
current shunt measurement application of the AD203SN. A
small sensing resistor
RsHUND
placed in series with the current
·
1oop,
develops a small differential voltage that may be further
scaled to provide an isolator output voltage that is directly pro-
. portional to the current. The voltage developed across the shunt
can potentially be several hundred to a thousand volts above
ground.
In
this circuit, the AD203SN provides the necessary
scaling of the shunt signal while providing high common-mode
voltage isolation and high common mode rejection of de and
60
Hz components.
t
VouT
{±10V)
PWRIN
Figure 24. Using the AD203SN
for
Current
Shunt
Measurements
The
transfer function for the circuit of Figure
24
can be written
as:
VouT =
RsHuNrx(I+Rp/RG)xlwoP
where
VouT
Rs
HUNT
RF
RG
I
LOOP
Output Voltage
(V)
Sense or Current Shunt Resistance (D)
Feedback Resistance (D)
Gain Resistance (D)
Loop Current (A).
-11-
AD203SN
Low Level Inputs
In applications where low level signals need to be isolated (ther-
mocouples are one such application), a
low
drift input amplifier
can be used with the AD203SN. Figure
25
illustrates this imple-
mentation
of
the AD203SN. The circuit design also includes a
three-pole active filter which provides for enhanced common
mode rejection at
60
Hz and normal mode rejection of frequen-
cies above a
few
Hz.
If
any offset adjustments are desired, they
are best done at the trim pins of the low drift input amplifier.
Gain adjustments can be done at the feedback resistor.
Figure 25. Using the AD203SN
with
Low
Level Inputs
The input-output relationship for the circuit shown in Figure
25
can be written
as:
where
VouT
VrN
RG
Vour
=
VINx
(1
+SO
kWRG)
Output Voltage
(V)
Low Level Input Voltage
(V)
Isolation Amplifier Gain Resistance (D).
Noise Reduction in
Data
Acquisition Systems
The AD203SN uses amplitude modulation techniques with a
35
kHz carrier to pass both
ac
and de signals across the isolation
barrier. Some of the carrier's harmonics are unavoidably passed
through to the isolator output in the form of ripple. In most
cases, this noise source is insignificant when compared to the
measured signal. However, in some applications, particularly
when a fast
AID
converter is used following the isolator, it may
be desirable to add filtering at the isolator's output in order to
reduce the carrier ripple. Figure
26
shows a circuit that will
reduce the carrier ripple through the use of a two-pole output
filter.
Figure 26. Noise Reduction in Data
Acquisition
Systems
Using the AD203SN
Rev. B
‘Zl— SELECTION GUIDE FOR ANALOG DEVICES‘ FAMILY OF ISOLATION AMPLIFIERS Cnnslde‘r m: H You Nwd: A9202] A0202K 1502113511 ADZIMJ ADZMK ADZWAN ADZWBN A0210»! 2w Gcnm| lsplamn foI Mnln‘cnannal Applicaliuns Lowest Oosl Isnlam 3~Pon Isnlzuon Rugged, Millnry Tmperaulrc Range Isolawr Medic-l Isolalor Gain Low Nnnllnelnzy (: :0.01;%l :0.05% :0.025% :0.025% :0.05% :0.025% :0.025% :o.olz% :0.025% :0.05% ’ an Gain Temp. Ca. (:25 ppm 45 pnnnrc 45 ppnmc 50 ppm/“C 45 pvllll°C 45 ppm/“C 25 ppmrc 25 we 25 ppm/“C 75 nnmrc Isolation High cmv Raving (:25 kV ms, Continuous) 750 v ms 1.5 kV nus 1.5 kV ms 750 v nus 1.5 kV nnis 2.5 kV nus 2.5 kV ms 1.5 kV rms 3.5 kV rms High CMR 1:104 43,1111 Oondmons) 100 an 1110 dB 95 as 104 as 104 dB [20 dB 121) dB 120 an 73 as LowLeakagnCunmusz MIms,240VIm5,60Hz) ZuArms ZpArms 41mm 21mm: 21:.Arms 2 nArn-ls 2 nAnn-ls 2 1.11m ZpAnns' Speed 20 kHz Full signal BandwldIh 10 kHz Full Signal Bandwidth 5 111-11 Pull 5.an andwidlh 2 kHz 2 kHz 700 Hz FasI Sealing Time (5150 11:) hm hm 150 .15 Im [ms 150 ps 150 ps 150 us Fm Slew 115:: (:IV/ pa) 0 5 v/ n: l V/ 11s 1 V/ n; I v1 [.15 25 mV/ M 011321 Low 01m. Drifl 'I‘el-np. Ca. (:20 nvmy 20 mm 20 pvr'c 55 nvm 20 nvrc 20 nvrc 4o nvm 40 nV/°c 40 nvm I70 nvrc 11am 011nm :10 v Dilfemnlizl Output :5 v :5 v :10 v :5 v :5 v :10 v :10 v :10 v :5 v Low Outpullmpcdance(£l 11> 7m 71:11 0.211 31m 3H1 In In 10. lm Isolated Power [willed an: End Powex (275 mm 5 MW 6 "NV 150 mW 37.5 inw 37.5 mil 150 mW 150 MP 150 niw 115 mw Supply Input PuwerSupply [minor Powcmd byxdc Supply HSVdc +15Vdc +15Vdc 15 Vp-p 15Vpp HSVdc +lSVdc HSVdc +15vilc @ 25 kHz @ 15 kHz Rated Ptrformancc 7551210 ~125°c,11anea Rang: Tempenuu: 700°C to 45°C, Rama Rang: 715°C :0 435°C, Rand Range 0 to +70%; Rawd Range} Packaging Small Size (0.325 in‘ cyp) SIP Pkg. SIP Pkg. I 021 in; SIP Pkg. SIP Pkg. 0.735 in3 0.735 in} 0.7351113 1.395 in‘ SIP Package DIP Package NOTES All penipmam: speafiuuion numben apply [or 6:! WV 2nd 0 1o +71% Quounons for nonlinznrity, gain lempenlulc coefficient. CMv mung md leakage cumni art max numbfls; CMR and nfim [empcmmle codficlml m min, all mm m lypical [solute-11mm uni pm. specifimumls are [or bad: me + and 7 mmunfls. ‘111: 2141 leakzgg applit: {m 115 v Inna. Inn 1113202, 1113204 and 1115210 series will apune in me 40°C inn-1155c mpmm tinge. PRINTED 1N u.s.A. Clml-lo-ms
I
.....
~
SELECTION GUIDE FOR ANALOG DEVICES' FAMILY OF ISOLATION AMPLIFIERS
If
You Need:
~
AD202J AD202K AD203SN AD204J AD204K AD210AN
General Isolator for Multichannel Applications
Lowest Cost Isolator
3-Port Isolation
Rugged, Military Temperature Range Isolator
Medical Isolator
Gain Low Nonlinearity (""±0.01?%) ±0.05% ±0.025% ±0.025% ±0.05% ±0.025% ±0.025%
Low Gain Temp. Co. (""25
ppm/QC)
45
ppm/QC
45
ppm/QC
60
ppm/QC
45
ppm/QC
45
ppm/QC
25
ppm/QC
Isolation High CMV Rating (2:2.5 kV rms, Continuous) 750 V rms 1.5 kV rms
1.5
kV rms
750
V rms
1.5
kV rms 2.5 kV rms
High CMR (2:104 dB, All Conditions)
100
dB
100
dB
96
dB
104
dB
104
dB
120
dB
Low Leakage Current (""2
µArms,
240 V rms,
60
Hz) 2
µArms
2
µArms
4
µArms
2
µArms
2
µArms
2
µArms
Speed
20
kHz
Full Signal Bandwidth
10
kHz
Full Signal Bandwidth
5
kHz
Full Signal Bandwidth 2
kHz
2kHz
Fast Settling Time (""150 µs)
lms lms
150
µs
lms lms
150
µs
Fast Slew Rate (2:1V/ µs) 0.5 V/ µs 1 VI µs
Offset Low Offset Drift Temp. Co. (""20
µV/QC)
20
µV/QC
20 µVl°C
55
µVl°C
20
µVl°C
20
µVl°C
40
µV/QC
Rated Output ±
10
V Differential
Output
±5
v
±5
v
±10
v
±5
v
±5
v
±10
v
Low Output Impedance (""l !1) 7
k.!1
7
k.!1
0.2
!1
3 k
!1
3 k
!1
1
!1
Isolated Power Isolated Front
End
Power (2:75 mW)
6mW 6mW
150mW
37.5
mW
37.5
mW
150mW
Supply
Input
Power Supply Isolator Powered by a de Supply +15 V de +15 V de +
15
V de
15
v p-p
15
v p-p +15 V de
@25
kHz
@
25
kHz
Rated Performance -55QC to +
125QC,
Rated Range
Temperature -40QC
to
+85QC,
Rated Range
-25QC to
+85QC,
Rated Range
0 to +
70QC,
Rated Range2
Packaging Small Size (0.325 in3 typ) SIP Pkg. SIP Pkg. 1.021 in3 SIP Pkg. SIP Pkg. 0.735 in3
SIP Package
DIP
Package
NOTES
All
performance specification numbers apply
for
G=l
VN
and 0
to
+7D°C.
Quotations
for
nonlinearity, gain temperature coefficient,
CMV
rating and
leakage
current
are
max
numbers;
CMR
and offset temperature coefficient
are
min,
all
other
are
typical.
Isolated front end power specifications
are
for
both the + and -terminals.
I The
284J
leakage
applies
for
115
V
rms.
2The AD202,
AD204
and
AD210
series
will
operate in the
-40QC
to+85QC
temperature range.
PRINTED
IN
U.S.A.
AD210BN AD210JN 284J
±0.012% ±0.025% ±0.05%
25
ppm/QC
25
ppm/QC
75
ppm/QC
2.5 kV rms
1.5
kV rms 3.5 kV rms
120
dB
120
dB
78
dB
2
µArms
2
µArms
2 µA rms1
700 Hz
150
µs
150
µs
1 V/ µs 1 V/ µs
25
mV/ µs
40
µV/QC
40
µV/QC
170
µV/QC
±10
v
±10
v
±5
v
1
!1
1
!1
1
k.!1
150mW 150mW
85mW
+
15
V de +
15
V de +15 V de
0.735 in3 0.735 in3 1.395 in3
C1301-10-5/89
UHU
Data Sheet AD203SN
OUTLINE DIMENSIONS
072508-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
18 19
202122
13
2
38 37 36
0.65 (16.50)
MAX
0.15 (3.81)
MIN
1.60 (40.60)
0.215
(5.50)
0.10 (2.50)
TYP
2.23 (56.60) MAX
SIDE VIEW
BOTTOM VIEW
0.60 (15.20)
0.83 (21.10)
MAX
0.018 (0.45)
SQ
Figure 27. AD203 SIP Package
(N-11)
11-Lead Count with 38-Lead Spacing
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD203SN −55°C to +125°C 11-Lead SIP Package N-11
ANALOG DEVICES www.ana|ng.nnm
Data Sheet AD203SN
REVISION HISTORY
8/2016—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Deleted Prices .................................................................................... 3
©2002–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02988-0-8/16(B)