L5987 Datasheet by STMicroelectronics

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This is information on a product in full production.
May 2014 DocID14972 Rev 4 1/40
L5987
3 A step-down switching regulator
Datasheet - production data
Features
3 A DC output current
2.9 V to 18 V input voltage
Output voltage adjustable from 0.6 V
250 kHz switching frequency, programmable
up to 1 MHz
Internal soft-start and inhibit
Low dropout operation: 100% duty cycle
Voltage feedforward
Zero load current operation
Overcurrent and thermal protection
VFQFPN 3 x 3 -8L and HSOP8 package
Applications
Consumer: STB, DVD, DVD recorder, car
audio, LCD TV and monitors
Industrial: PLD, PLA, FPGA, chargers
Networking: XDSL, modems, DC-DC modules
Computer: optical storage, hard disk drive,
printers, audio/graphic cards
LED driving
Description
The L5987 is a step-down switching regulator
with a 3.5 A (minimum) current limited embedded
Power MOSFET, so it is able to deliver an up to
3 A current to the load depending on the
application conditions.
The input voltage can range from 2.9 V to 18 V,
while the output voltage can be set starting from
0.6 V to VIN. Having a minimum input voltage of
2.9 V, the device is suitable also for a 3.3 V bus.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The VFQFPN8 and the HSOP packages with an
exposed pad allow reducing the RthJA down to
60 °C/W and 40 °C/W respectively.
HSOP8 exposed pad
VFQFPN8 3 x 3 mm
Figure 1. Application circuit
www.st.com
Contents L5987
2/40 DocID14972 Rev 4
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7 Maximum DC output current L5987A (HSOP8) . . . . . . . . . . . . . . . . . . . . 24
5.8 Maximum DC output current L5987 (VFQFPN) . . . . . . . . . . . . . . . . . . . . 24
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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L5987 Contents
40
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
our E SYNCH E INHE COMPE :I Vcc :l GND :l st :IFB
Pin settings L5987
4/40 DocID14972 Rev 4
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
OUT
SYNCH
INH
COMP
VCC
GND
FSW
FB
OUT
SYNCH
INH
COMP
VCC
GND
FSW
FB
Table 1. Pin description
No. Type Description
1 OUT Regulator output
2 SYNCH
Master/slave synchronization. When it is left floating, a signal with
a phase shift of half a period with respect to the power turn-on is present
at the pin. When connected to an external signal at a frequency higher
than the internal one, then the device is synchronized by the external
signal, with zero phase shift.
Connecting together the SYNCH pin of two devices, the one with higher
frequency works as a master and the other one as a slave; so the two
powers turn-on have a phase shift of half a period.
3INH
A logical signal (active high) disables the device. With INH higher than
1.9 V the device is OFF and with INH lower than 0.6 V the device is ON.
4 COMP Error amplifier output to be used for loop frequency compensation
5FB
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from the Vout to the FB pin.
6F
SW
The switching frequency can be increased connecting an external
resistor from the FSW pin and ground. If this pin is left floating, the device
works at its free-running frequency of 250 kHz.
7 GND Ground
8V
CC Unregulated DC input voltage
DocID14972 Rev 4 5/40
L5987 Maximum ratings
40
2 Maximum ratings
3 Thermal data
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
Vcc Input voltage 20
V
OUT Output DC voltage -0.3 to VCC
FSW, COMP, SYNCH Analog pin -0.3 to 4
INH Inhibit pin -0.3 to VCC
FB Feedback voltage -0.3 to 1.5
PTOT Power dissipation at TA < 60 °C
VFQFPN 1.5. W
HSOP 2
TJJunction temperature range -40 to 150 °C
Tstg Storage temperature range -55 to 150 °C
Table 3. Thermal data
Symbol Parameter Value Unit
RthJA Maximum thermal resistance junction ambient(1) VFQFPN 60
°C/W
HSOP 40
1. Package mounted on demonstration board.
Electrical characteristics L5987
6/40 DocID14972 Rev 4
4 Electrical characteristics
TJ = 25 °C, VCC = 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test condition
Values
Unit
Min. Typ. Max.
VCC Operating input voltage range (1) 2.9 18
VVCCON Turn-on VCC threshold (1) 2.9
VCCHYS VCC UVLO hysteresis (1) 0.175 0.3
RDS(on) MOSFET on resistance
140 170
m
(1) 140 220
ILIM Maximum limiting current 3.5 4.0 4.4 A
Oscillator
FSW Switching frequency
225 250 275
kHz
(1) 220 265
VFSW FSW pin voltage 1.262 V
D Duty cycle 0 100 %
FADJ Adjustable switching frequency RFSW = 33 k1000 kHz
Dynamic characteristics
VFB Feedback voltage 2.9 V < VCC < 18 V(1) 0.593 0.6 0.607 V
DC characteristics
IQQuiescent current Duty cycle = 0, VFB = 0.8 V 2.4 mA
IQST-BY Total standby quiescent current 20 30 A
Inhibit
INH threshold voltage
Device ON level 0.6
V
Device OFF level 1.9
INH current INH = 0 7.5 10 A
Soft-start
TSS Soft-start duration
FSW pin floating 7.4 8.2 9.1
ms
FSW = 1 MHz, RFSW = 33 k2
DocID14972 Rev 4 7/40
L5987 Electrical characteristics
40
Error amplifier
VCH High level output voltage VFB < 0.6 V 3
V
VCL Low level output voltage VFB > 0.6 V 0.1
IFB Bias source current VFB = 0 V to 0.8 V 1 A
IO SOURCE Source COMP pin VFB = 0.5 V, VCOMP = 1 V 20 mA
IO SINK Sink COMP pin VFB = 0.7 V, VCOMP = 1 V 25 mA
GVOpen loop voltage gain (2) 100 dB
Synchronization function
High input voltage 2 3.3
V
Low input voltage 1
Slave sink current VSYNCH = 2.9 V 0.7 0.9 mA
Master output amplitude ISOURCE = 4.5 mA 2.0 V
Output pulse width SYNCH floating 110
ns
Input pulse width 70
Protection
IFBDISC FB disconnection source current 1 A
TSHDN
Thermal shutdown 150
°C
Hysteresis 30
1. Specification referred to TJ from -40 to +125 °C. Specification in the -40 to +125 °C temperature range are assured by
design, characterization and statistical correlation.
2. Guaranteed by design.
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition
Values
Unit
Min. Typ. Max.
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Functional description L5987
8/40 DocID14972 Rev 4
5 Functional description
The L5987 device is based on a “voltage mode”, constant frequency control. The output
voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V)
providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and
OFF time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feedforward are implemented.
The soft-start circuitry to limit inrush current during the startup phase.
The voltage mode error amplifier.
The pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch.
The high-side driver for an embedded P-channel Power MOSFET switch.
The peak current limit sensing block, to handle overload and short-circuit conditions.
A voltage regulator and internal reference. It supplies internal circuitry and provides
a fixed internal reference.
A voltage monitor circuitry (UVLO) that checks the input and internal voltages.
A thermal shutdown block, to prevent thermal runaway.
Figure 3. Block diagram
—> Clock Synchronization 4% Generamr Ramp W 7 _, Generator
DocID14972 Rev 4 9/40
L5987 Functional description
40
5.1 Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connected to
the FSW pin. In case the FSW pin is left floating, the frequency is 250 kHz; it can be
increased as shown in Figure 6 by an external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feedforward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way a frequency feedforward is implemented (Figure 5.b) in order to
keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 20
for PWM gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with a
higher oscillator frequency works as a master, so the slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor (see the L5988D datasheet).
Figure 4. Oscillator circuit block diagram
The device can be synchronized to work at a higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This changing has to be taken into account when the loop stability is studied.
To minimize the change of the PWM gain, the free-running frequency should be set (with
a resistor on the FSW pin) only slightly lower than the external clock frequency. This pre-
adjusting of the frequency will change the sawtooth slope in order to get negligible the
truncation of sawtooth, due to the external synchronization.
Clock
Generator
Ramp
Generator
FSW
Sawtooth
Clock
Synchronization
SYNCH
Clock
Generator
Ramp
Generator
FSW
Sawtooth
ClockClock
Synchronization
SYNCH
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Functional description L5987
10/40 DocID14972 Rev 4
Figure 5. Sawtooth: voltage and frequency feedforward; external synchronization
Figure 6. Oscillator frequency versus FSW pin resistor
204s / FSW
DocID14972 Rev 4 11/40
L5987 Functional description
40
5.2 Soft-start
The soft-start is essential to assure a correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monotonically.
The soft-start is performed by a staircase ramp on the non-inverting input (VREF) of the error
amplifier. So the output voltage slew rate is:
Equation 1
where SRVREF is the slew rate of the non-inverting input, while R1and R2 is the resistor
divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of
64 steps of 9.5 mV each one, from 0 V to 0.6 V. The time base of one step is of 32 clock
cycles. So the soft-start time and then the output voltage slew rate depend on the switching
frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 2
For example with a switching frequency of 250 kHz the SSTIME is 8 ms.
SROUT SRVREF 1R1
R2
--------+


=
SSTIME
32 64
Fsw
-----------------=
Functional description L5987
12/40 DocID14972 Rev 4
5.3 Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non-inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier so with the high DC gain and low output impedance.
The uncompensated error amplifier characteristics are the following:
In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter, a type II compensation network can be used. Otherwise, a type
III compensation network has to be used (see Section 6.4 on page 20 for details about the
compensation network selection).
Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe
phase margin.
Table 5. Uncompensated error amplifier characteristics
Parameter Value
Low frequency gain 100 dB
GBWP 4.5 MHz
Slew rate 7 V/s
Output voltage swing 0 to 3.3 V
Maximum source/sink current 25 mA/40 mA
DocID14972 Rev 4 13/40
L5987 Functional description
40
5.4 Overcurrent protection
The L5987 device implements the overcurrent protection sensing current flowing through
the Power MOSFET. Due to the noise created by the switching activity of the Power
MOSFET, the current sensing is disabled during the initial phase of the conduction time.
This avoids an erroneous detection of a fault condition. This interval is generally known as
“masking time” or “blanking time”. The masking time is about 200 ns.
When the overcurrent is detected, two different behaviors are possible depending on the
operating condition.
Output voltage in regulation. When the overcurrent is sensed, the Power MOSFET is
switched off and the internal reference (VREF), that biases the non-inverting input of the
error amplifier, is set to zero and kept in this condition for a soft-start time (TSS, 2048
clock cycles). After this time, a new soft-start phase takes place and the internal
reference begins ramping (see Figure 8.a).
Soft-start phase. If the overcurrent limit is reached, the Power MOSFET is turned off
implementing the pulse by pulse overcurrent protection. During the soft-start phase,
under overcurrent condition, the device can skip pulses in order to keep the output
current constant and equal to the current limit. If, at the end of the “masking time”, the
current is higher than the overcurrent threshold, the Power MOSFET is turned off and it
will skip one pulse. If, at the next switching on at the end of the “masking time”, the
current is still higher than the threshold, the device will skip two pulses. This
mechanism is repeated and the device can skip up to seven pulses. While, if at the end
of the “masking time” the current is lower than the overcurrent threshold, the number of
skipped cycles is decreased by one unit. At the end of soft-start phase the output
voltage is in regulation and if the overcurrent persists, the behavior explained above
takes place.(see Figure 8.b).
So the overcurrent protection can be summarized as a “hiccup” intervention when the output
is in regulation and a constant current during the soft-start phase. If the output is shorted to
ground when the output voltage is on regulation, the overcurrent is triggered and the device
starts cycling with a period of 2048 clock cycles between the “hiccup” (Power MOSFET off
and no current to the load) and “constant current” with very short ON time and with reduced
switching frequency (up to one eighth of normal switching frequency). See Figure 33 on
page 357 for short-circuit behavior.
SYNCH 2048 dock Cycles Up to seven pulses are skipped b)
Functional description L5987
14/40 DocID14972 Rev 4
Figure 8. Overcurrent protection strategy
5.5 Inhibit function
The inhibit feature allows to put the device into standby mode . With the INH pin higher than
1.9 V, the device is disabled and the power consumption is reduced to less than 30 A. With
the INH pin lower than 0.6 V, the device is enabled. If the INH pin is left floating, an internal
pull-up ensures that the voltage at the pin reaches the inhibit threshold and the device is
disabled. The pin is also VCC compatible.
5.6 Hysteretic thermal shutdown
The thermal shutdown block generates a signal, that turns off the power stage, if the
junction temperature goes above 150 °C. Once the junction temperature goes back to about
130 °C, the device restarts in normal operation. The sensing element is very close to the
PDMOS area, so ensuring an accurate and fast temperature detection.
Eli:
DocID14972 Rev 4 15/40
L5987 Functional description
40
5.7 Maximum DC output current L5987A (HSOP8)
The L5987A device can manage DC output currents up to 3 A and the rated RMS current of
its internal power switch is 3 A. So the L5987A can deliver 3 A with 100% of duty cycle.
5.8 Maximum DC output current L5987 (VFQFPN)
The L5987 can manage DC output currents up to 3 A. However the rated RMS current of its
internal power switch is 2.5 A.
Since the current flows through the integrated power element only during the on time, the
RMS value is given by:
Equation 3
Where D is the duty cycle (VO / VIN).
Considering IO = 3 A, the maximum duty cycle that can be managed is:
Equation 4
In Figure 9 the maximum DC output current is reported as a function of the duty cycle. For
duty cycles lower than 69% the RMS current does not limit the maximum DC output current
of 3 A. For duty cycles higher than the 69% the maximum DC output current is limited by the
RMS current to:
Equation 5
In order to have a more accurate calculation of the maximum DC output current, the
complete expression for the duty cycle can be adopted, considering the voltage drop across
the Power MOSFET, the series resistance of the inductor and the forward voltage of the
rectification diode. The duty cycle results:
Equation 6
where IO is the desired DC output current.
For example with VIN = 5 V, VOUT = 3.3 V, IO = 2.6 A, RDS(on) = 220 m, VF = 0.35 V and
DCR = 30 m, the duty results D = 78%, so according to Equation 5 the maximum DC
output current is 2.83 A, which is higher than desired current.
With VIN = 3.3 V, VOUT = 1.8 V, IO = 2.7 A, RDS(on) = 220 m, VF = 0.35 V and DCR = 30 m,
the duty is D = 73%, so the maximum DC output current results 2.926 A, higher than the
desired current.
IRMS IOD=
DIRMS
2
IO
2
------------ 69%==
IOMAX2.5
D
--------=A if D 69%
DVOUT VFDCR IO
++
VIN VFRDSON IO
+
----------------------------------------------------------=
3.76. 7.7.7. .2 3 EH $2 8 8 0." Q Du ,
Functional description L5987
16/40 DocID14972 Rev 4
Figure 9. Maximum DC output current for VFQFPN8 package vs. duty cycle
Note: For duty cycles lower than 69%, the RMS current does not limit the maximum DC output
current of 3 A. For duty cycles higher than the 69% the maximum DC output current is
limited by the RMS current (see Equation 5).
DocID14972 Rev 4 17/40
L5987 Application information
40
6 Application information
6.1 Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is a subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 7
Where IO is the maximum DC output current, D is the duty cycle,
is the efficiency.
Considering = 1, this function has a maximum at D = 0.5 and it is equal to IO/2.
In a specific application the range of possible duty cycles has to be considered in order to
find out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 8
and
Equation 9
Where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across
the internal PDMOS.
In Table 6 some multi-layer ceramic capacitors suitable for this device are reported:
Table 6. Input MLCC capacitors
Manufacturer Series Cap value (F) Rated voltage (V)
MURATA
GRM31 10 25
GRM55 10 25
TDK C3225 10 25
IRMS IOD2D
2
---------------D2
2
-------+=
DMAX
VOUT VF
+
VINMIN VSW
-------------------------------------=
DMIN
VOUT VF
+
VINMAX VSW
--------------------------------------=
Application information L5987
18/40 DocID14972 Rev 4
6.2 Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value, in order to have the expected current ripple, has to be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In the continuous current mode (CCM), the inductance value can be calculated by the
following equation:
Equation 10
Where TON is the conduction time of the internal high-side switch and TOFF is the
conduction time of the external diode [in CCM, FSW = 1 / (TON + TOFF)]. The maximum
current ripple, at fixed VOUT
, is obtained at maximum TOFF that is at minimum duty cycle
(see Section 6.1 to calculate minimum duty). So fixing IL = 20% to 30% of the maximum
output current, the minimum inductance value can be calculated:
Equation 11
where FSW is the switching frequency, 1 / (TON + TOFF).
For example for VOUT = 3.3 V, VIN = 12 V, IO = 3 A and FSW = 250 kHz the minimum
inductance value to have IL = 30% of IO is about 10 H.
The peak current through the inductor is given by:
Equation 12
So if the inductor value decreases, the peak current (that has to be lower than the current
limit of the device) increases. The higher is the inductor value, the higher is the average
output current that can be delivered, without reaching the current limit.
In Table 7 some inductor part numbers are listed.
Table 7. Inductors
Manufacturer Series Inductor value (H) Saturation current (A)
Coilcraft
MSS1038 3.8 to 10 3.9 to 6.5
MSS1048 12 to 22 3.84 to 5.34
Wurth
PD Type L 8.2 to 15 3.75 to 6.25
PD Type M 2.2 to 4.7 4 to 6
SUMIDA
CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2
CDR10D48MN 6.6 to 12 4.1 to 5.7
IL
VIN VOUT
L
------------------------------TON
VOUT VF
+
L
----------------------------TOFF
==
LMIN
VOUT VF
+
IMAX
----------------------------1D
MIN
FSW
-----------------------=
ILPKIO
IL
2
--------+=
DocID14972 Rev 4 19/40
L5987 Application information
40
6.3 Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor has to be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 13
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR
value.
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Section 6.4 it will be illustrated how to consider its effect in the
system stability.
For example: with VOUT = 3.3 V, VIN = 12 V, IL = 0.9 A (resulting by the inductor value), in
order to have a VOUT = 0.01·VOUT
, if the multi-layer ceramic capacitors are adopted, 13 F
are needed and the ESR effect on the output voltage ripple can be neglected. In case of not
negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value. So in case of 330 F with ESR = 30 m, the resistive component of
the drop dominates and the voltage ripple is 27 mV
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application the output capacitor and system bandwidth
have to be chosen in order to sustain the load transient.
In Table 8 some capacitor series are listed.
Table 8. Output capacitors
Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)
MURATA
GRM32 22 to 100 6.3 to 25 < 5
GRM31 10 to 47 6.3 to 25 < 5
Panasonic
ECJ 10 to 22 6.3 < 5
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 < 5
VOUT ESR IMAX
IMAX
8C
OUT fSW

-------------------------------------+=
m u
Application information L5987
20/40 DocID14972 Rev 4
6.4 Compensation network
The compensation network has to assure stability and a good dynamic performance. The
loop of the L5987 is based on the voltage mode control. The error amplifier is a voltage
operational amplifier with high bandwidth. So selecting the compensation network the E/A
will be considered as ideal, that is, its bandwidth is much larger than the system one.
The transfer functions of the PWM modulator and the output LC filter are studied (see
Figure 10). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:
Equation 14
where VS is the sawtooth amplitude. As seen in Section 5.1 on page 9, the voltage
feedforward generates a sawtooth amplitude directly proportional to the input voltage, that
is:
Equation 15
In this way the PWM modulator gain results constant and equals to:
Equation 16
The synchronization of the device with an external clock provided trough the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 to understand how this gain changes
and how to keep it constant in spite of the external synchronization).
Figure 10. The error amplifier, the PWM modulation and the LC output filter
GPW0
VIN
Vs
---------=
VSKV
IN
=
GPW0
VIN
Vs
---------1
K
----9===
FB COMP
V
REF
E/A
PWM
V
S
OUT
V
CC
C
OUT
ESR
L
G
PW0
G
LC
FB COMP
V
REF
E/A
PWM
V
S
OUT
V
CC
C
OUT
ESR
L
G
PW0
G
LC
W LC (R ESR ‘ ESR)
DocID14972 Rev 4 21/40
L5987 Application information
40
The transfer function on the LC filter is given by:
Equation 17
where:
Equation 18
Equation 19
As seen in Section 5.3 on page 12 two different kinds of network can compensate the loop.
In the two following paragraph the guidelines to select the type II and type III compensation
network are illustrated.
6.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the DC error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency higher than the desired bandwidth (that is: 2ESR COUT < 1 / BW), the type
III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (< 1 m), with very high frequency zero, so type III network is adopted to compensate
the loop.
In Figure 11 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:
Equation 20
Equation 21
GLC s
1s
2fzESR
--------------------------+
1s
2QfLC
---------------------------- s
2fLC
-------------------


2
++
-------------------------------------------------------------------------=
QROUT LC
OUT ROUT ESR+
LC
OUT ROUT ESR+
------------------------------------------------------------------------------------------ ROUT
VOUT
IOUT
--------------=,=
fZ1
1
2C3R1R3
+
------------------------------------------------=fZ2
1
2R4C4

------------------------------=
fP0 0=fP1
1
2R3C3

------------------------------= fP2
1
2R4
C4C5
C4C5
+
--------------------
--------------------------------------------=
COMP CA GLooPm = eru ' Gm“) ' 61mm \ fp1 fp2
Application information L5987
22/40 DocID14972 Rev 4
Figure 11. Type III compensation network
In Figure 12 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)] are drawn.
Figure 12. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1. Choose a value for R1, usually between 1 k and 5 k.
2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 22
where K is the feedforward constant and 1 / K is equal to 9.
R4
BW K
fLC
------------------ R1
=
DocID14972 Rev 4 23/40
L5987 Application information
40
3. Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):
Equation 23
4. Calculate C5 by placing the second pole at four times the system bandwidth (BW):
Equation 24
5. Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 25
The suggested maximum system bandwidth is equal to the switching frequency divided by
3.5 (FSW/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz.
For example: with VOUT = 3.3 V, VIN = 12 V, IO = 3 A, L = 10 H, COUT = 22 F, ESR < 1 m,
the type III compensation network is:
C4
1
R4fLC

---------------------------=
C5
C4
2R4C44BW1
--------------------------------------------------------------=
R3
R1
4BW
fLC
----------------- 1
---------------------------= C3
1
2R34BW
-----------------------------------------=
R14.99k=R21.1k=R3220=R43.3k=C33.3nF=C410nF=C5180pF=
1m 100 60 4U Mm le [dB] n 10 100 Freq“ 110 1.10 10 mo L in} L -LO4 Flequenc) [Hz] 1 105 1-106 1-107 1 10x
Application information L5987
24/40 DocID14972 Rev 4
In Figure 13 is shown the module and phase of the open loop gain. The bandwidth is about
71 kHz and the phase margin is 46°.
Figure 13. Open loop gain Bode diagram with ceramic output capacitor
DocID14972 Rev 4 25/40
L5987 Application information
40
6.4.2 Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency lower than the desired bandwidth (that is: 2ESR COUT > 1 / BW), this zero
helps stabilize the loop. Electrolytic capacitors show not negligible ESR (> 30 m), so with
this kind of the output capacitor, the type II network combined with the zero of the ESR
allows stabilizing the loop.
In Figure 14 the type II network is shown.
Figure 14. Type II compensation network
The singularities of the network are:
Equation 26
fZ1
1
2R4C4

------------------------------= fP0 0=fP1
1
2R4
C4C5
C4C5
+
--------------------
--------------------------------------------=
GLoovm = Gpwn ' Gm“) ' GTypeIIm rm
Application information L5987
26/40 DocID14972 Rev 4
In Figure 15 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)] are drawn.
Figure 15. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1. Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 27
Where fESR is the ESR zero:
Equation 28
and VS is the saw-tooth amplitude. The voltage feedforward keeps the ratio VS/VIN constant.
3. Calculate C4 by placing the zero one decade below the output filter double pole:
Equation 29
R4
fESR
fLC
------------


2BW
fESR
------------VS
VIN
---------R1
=
fESR
1
2ESR COUT

--------------------------------------------=
C4
10
2R4fLC

-------------------------------=
DocID14972 Rev 4 27/40
L5987 Application information
40
4. Then calculate C3 in order to place the second pole at four times the system bandwidth
(BW):
Equation 30
For example: with VOUT = 3.3 V, VIN = 12 V, IO = 3 A, L = 10 H, COUT = 330 F,
ESR = 35 m the type II compensation network is:
C5
C4
2R4C44BW1
--------------------------------------------------------------=
R11.5k=R2330=R410k=C447nF=C582pF=
lex‘c 110 100 Module [11B] 10 ‘40 mo 10 1-103 1 -1o Frequmz)‘ [H1] ‘lK 1x -<(» 1;="" mm="" -111="" i="" 140="" m="">< ‘a="" 1%="" xx="" 10="" 100="" 1="" 103="" 1="" 104="" frequency="" [hz]="" 1="" 1o5="" 1="" 106="" 1="" 107="" 1="" 10k="">
Application information L5987
28/40 DocID14972 Rev 4
In Figure 16 is shown the module and phase of the open loop gain. The bandwidth is about
32 kHz and the phase margin is 45°.
Figure 16. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
DocID14972 Rev 4 29/40
L5987 Application information
40
6.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a) Conduction losses due to the not negligible RDS(on) of the power switch; these are
equal to:
Equation 31
Where D is the duty cycle of the application and the maximum RDS(on) overtemperature is
220 m. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN,
but actually it is quite higher to compensate the losses of the regulator. So the conduction
losses increase compared with the ideal case.
b) Switching losses due to Power MOSFET turn ON and OFF; these can be
calculated as:
Equation 32
Where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn ON and turn OFF phases, as shown in Figure 17.
TSW is the equivalent switching time. For this device the typical value for the equivalent
switching time is 50 ns.
c) Quiescent current losses, calculated as:
Equation 33
where IQ is the quiescent current (IQ = 2.4 mA).
The junction temperature TJ can be calculated as:
Equation 34
Where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
RthJA is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The RthJA measured on the demonstration board described in Section 6.6: Layout
considerations is about 60 °C/W for the VFQFPN package and about 40 °C/W for the HSOP
package.
PON RDSON IOUT

2D=
PSW VIN IOUT
TRISE TFALL
+
2
-------------------------------------------Fsw VIN IOUT TSW FSW
==
PQVIN IQ
=
TJTARthJA PTOT
+=
‘SW‘TCH
Application information L5987
30/40 DocID14972 Rev 4
Figure 17. Switching losses
6.6 Layout considerations
The PC board layout of switching DC/DC regulator is very important to minimize the noise
injected in high impedance nodes and interferences generated by the high switching current
loops.
In a step-down converter the input loop (including the input capacitor, the Power MOSFET
and the free wheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current are flowing through it. In order to minimize the EMI, this loop has to be
as short as possible.
The feedback pin (FB) connection to external resistor divider is a high impedance node, so
the interferences can be minimized placing the routing of the feedback node as far as
possible from the high current paths. To reduce the pick up noise the resistor divider has to
be placed very close to the device.
To filter the high frequency noise, a small capacitor (220 nF) can be added as close as
possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
OUTRUT CARACTTOR DTRECTLV CONNECTED TO HEAW COUND GND vERv SMALL HTCH CURRENT VOUT CTRCULATTNG RATH TO MWMZE RADTATTON AND HTCH FREOUENCV RESONANCE RRODLEMS GND syNCH MWMUM FEEDBACK PW Ea ROUTTNC TO AMOTD RTCKUR W E GND COMRENsATTON NETWORK FAR’ CROUND RLANE CONNECTED FROM HTCH CURRENT RATHs TD EXPOSED RAD TO ENHANCE THERMAL RERFORMANCE
DocID14972 Rev 4 31/40
L5987 Application information
40
In Figure 18 a layout example is shown.
Figure 18. Layout example
Application information L5987
32/40 DocID14972 Rev 4
6.7 Application circuit
In Figure 19 the demonstration board application circuit is shown.
Figure 19. Demonstration board application circuit
Table 9. Component list
Reference Part number Description Manufacturer
C1 GRM32ER61E226KE15 22 F, 25 V MURATA
C2 GRM32ER61E226KE15 22 F, 25 V MURATA
C3 2.2 nF, 50 V
C4 10 nF, 50 V
C5 330 pF, 50 V
C6 220 nF, 25 V
R1 4.99 k, 1%, 0.1 W 0603
R2 2.49 k, 1%, 0.1 W 0603
R3 330 , 1%, 0.1 W 0603
R4 2 k, 1%, 0.1 W 0603
R5 100 k
D1 STPS2L25V 2 A DC, 2 5V STMicroelectronics
L1 MSS1038-522NL 5.2 H, 30%, 5.28 A,
DCRMAX = 22 mCoilcraft
L5987/A
R3
330
L1 5.2uH MSS1038
C2
22u
25V
R4
2K
R1 4.99K
C3 2.2nF
C4 10hF
C5 330pF
1
5
4
32
6
7
8
D1
STPS2L25
R2
2.49k
Vout=1.8V
C1
22u
25V
C6
220n
25V
R5
150k
Vin=2.9V - 18V VCC
INH
GND FB
SYNCH
OUT
COMPFSW
vouT v10 EVAL5936/7 Mww sv cow [VALSQBBA/7A WevZ
DocID14972 Rev 4 33/40
L5987 Application information
40
Figure 20. PCB layout: L5987 and L5987A (component side)
Figure 21. PCB layout: L5987 and L5987A (bottom side)
Figure 22. PCB layout: L5987 and L5987A (front side)
u l ,x 1 mm mm IN IN u” m. m; mm ‘— y[
Application information L5987
34/40 DocID14972 Rev 4
Figure 23. Junction temperature
vs. output current - VIN = 12 V
Figure 24. Junction temperature
vs. output current - VIN = 5 V
Figure 25. Junction temperature
vs. output current - VIN = 3.3 V
Figure 26. Efficiency vs. output current
- VIN = 12 V
Figure 27. Efficiency vs. output current
- VIN = 5 V
Figure 28. Efficiency vs. output current
- VIN = 3.3 V
76
78
80
82
84
86
88
90
92
0.3 0.8 1.3 1.8 2.3 2.8
Io [A]
Efficienc
y
[
%
]
V
IN
=12V
V
O
=2.5V
V
O
=3.3V
V
O
=5V
F
SW
=250kHz
76
78
80
82
84
86
88
90
92
0.3 0.8 1.3 1.8 2.3 2.8
Io [A]
Efficienc
y
[
%
]
V
IN
=12V
V
O
=2.5V
V
O
=3.3V
V
O
=5V
F
SW
=250kHz
70
75
80
85
90
95
0.3 0.8 1.3 1.8 2.3 2.8
Io [A]
Efficienc
y
[
%
]
V
O
=1.8V
V
O
=2.5V
V
O
=3.3V
V
IN
=5V
F
SW
=250kHz
70
75
80
85
90
95
0.3 0.8 1.3 1.8 2.3 2.8
Io [A]
Efficienc
y
[
%
]
V
O
=1.8V
V
O
=2.5V
V
O
=3.3V
V
IN
=5V
F
SW
=250kHz
65
70
75
80
85
90
95
0.3 0.8 1.3 1.8 2.3 2.8
Io [A]
Efficienc
y
[% ]
V
O
=1.2V
V
O
=1.8V
V
O
=2.5V
V
IN
=3.3V
DocID14972 Rev 4 35/40
L5987 Application information
40
Figure 29. Load regulation Figure 30. Line regulation
Figure 31. Load transient:
from 0.4 A to 3 A
Figure 32. Soft-start
Figure 33. Short-circuit behavior
0
0.2
0.4
0.6
0.8
1
1.2
00.511.522.53
I
O
[A]
V
FB
/V
FB
[%]
V
CC
=12V
V
CC
=5V
0
0.2
0.4
0.6
0.8
1
2 4 6 8 10 12 14 16 18
VCC [V]
VFB/VFB [%]
IO=1A
IO=2A
IO=3A
V
OUT
100mV/div
AC coupled
I
L
1A/div
Time base 100us/div
C
OUT
=47uF
L=3.8uH
F
SW
=520k
V
OUT
100mV/div
AC coupled
I
L
1A/div
Time base 100us/div
C
OUT
=47uF
L=3.8uH
F
SW
=520k
I
L
1A/div
V
OUT
1V/div
Time base 1ms/div
I
L
1A/div
V
OUT
0.5V/div
Time base 1ms/div
I
L
1A/div
V
OUT
1V/div
Time base 1ms/div
I
L
1A/div
V
OUT
0.5V/div
Time base 1ms/div
I
L
1A/div
OUT 10V/div
V
OUT
1V/div SHORTED OUTPUT
Time base 5ms/div
I
L
1A/div
OUT 10V/div
V
OUT
0.5V/div SHORTED OUTPUT
Time base 5ms/div
I
L
1A/div
OUT 10V/div
V
OUT
1V/div SHORTED OUTPUT
Time base 5ms/div
I
L
1A/div
OUT 10V/div
V
OUT
0.5V/div SHORTED OUTPUT
Time base 5ms/div
SEA‘HNC PLANE ZCI [2 I A: \ ,,, a ‘ A1 A2 E A [Ea-(2% «mom VFW HQ W ‘0‘ 7426334 B
Package information L5987
36/40 DocID14972 Rev 4
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 34. VFQFPN8 (3 x 3 x 1.08 mm) package outline
DocID14972 Rev 4 37/40
L5987 Package information
40
Table 10. VFQFPN8 (3 x 3 x 1.08 mm) package mechanical data
Symbol
Dimensions
mm inch
Min. Typ. Max. Min. Typ. Max.
A 0.80 0.90 1.00 0.0315 0.0354 0.0394
A1 0.02 0.05 0.0008 0.0020
A2 0.70 0.0276
A3 0.20 0.0079
b 0.18 0.23 0.30 0.0071 0.0091 0.0118
D 2.95 3.00 3.05 0.1161 0.1181 0.1200
D2 2.23 2.38 2.48 0.0878 0.0937 0.0976
E 2.95 3.00 3.05 0.1161 0.1181 0.1200
E2 1.65 1.70 1.75 0.0649 0.0669 0.0689
e 0.50 0.0197
L 0.35 0.40 0.45 0.0137 0.0157 0.0177
ddd 0.08 0.0031
Exposed Pad: _ ‘ _ _ _ D1 3.1mm E2 2.41mm 7135mm:
Package information L5987
38/40 DocID14972 Rev 4
Figure 35. HSOP8 package outline
Table 11. HSOP8 package mechanical data
Symbol
Dimensions
mm inch
Min. Typ. Max. Min. Typ. Max.
A 1.70 0.0669
A1 0.00 0.15 0.00 0.0059
A2 1.25 0.0492
b 0.31 0.51 0.0122 0.0201
c 0.17 0.25 0.0067 0.0098
D 4.80 4.90 5.00 0.1890 0.1929 0.1969
E 5.80 6.00 6.20 0.2283 0.2441
E1 3.80 3.90 4.00 0.1496 0.1575
e1.27
h 0.25 0.50 0.0098 0.0197
L 0.40 1.27 0.0157 0.0500
k 0 8 0.3150
ccc 0.10 0.0039
DocID14972 Rev 4 39/40
L5987 Order codes
40
8 Order codes
9 Revision history
Table 12. Order codes
Order codes Package Packaging
L5987A HSOP8 Tube
L5987TR VFQFPN8
Tape and reel
L5987ATR HSOP8
Table 13. Document revision history
Date Revision Changes
29-Aug-2008 1Initial release
29-Jan-2009 2 Updated: Equation 22
19-Jun-2009 3 Updated Table 4 on page 6 and Figure 6 on page 10
13-May-2014 4
Numbered Equation 26 on page 25.
Updated Section 7: Package information on page 36 (updated titles,
reversed order of Figure 34 and Table 10, Figure 35 and Table 11,
minor modifications).
Updated Table 12: Order codes (removed the L5987 order code
related to the VFQFPN8 in tube).
Updated cross-references throughout document.
Minor modifications throughout document.
L5987
40/40 DocID14972 Rev 4
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IC REG BUCK ADJUSTABLE 3A 8HSOP
IC REG BUCK ADJUSTABLE 3A 8HSOP
IC REG BUCK ADJUSTABLE 3A 8HSOP
EVAL BOARD FOR L5987
BOARD EVALUATION FOR L5987
BOARD EVALUATION FOR L5987A
IC REG BUCK ADJ 3A 8VFQFPN
IC REG BUCK ADJ 3A 8VFQFPN
IC REG BUCK ADJUSTABLE 3A 8HSOP
IC REG BUCK ADJ 3A 8VFQFPN
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