NUP4114, SZNUP4114 Series Datasheet by ON Semiconductor

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NUP41 1 4 Series L 0N Semiconducior® www.0nsemi.com nnn m 0 uuu nnn m 0 nun @ mm M LILILI AN D83U8/D
© Semiconductor Components Industries, LLC, 2014
July, 2019 Rev. 7
1Publication Order Number:
NUP4114/D
NUP4114 Series
ESD Protection Diode
Low Clamping Voltage
The NUP4114 ESD protection diode array is designed to protect
high speed data lines from ESD. Ultralow capacitance and high level
of ESD protection make these devices well suited for use in USB 2.0
high speed applications.
Features
Low Clamping Voltage
Low Capacitance (<0.6 pF Typical, I/O to GND)
Low Leakage
Response Time is Typically < 1.0 ns
IEC6100042 Level 4 ESD Protection
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AECQ101 Qualified and
PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
LVDS
USB 2.0 High Speed Data Line and Power Line Protection
Digital Video Interface (DVI) and HDMI
Gigabit Ethernet
Monitors and Flat Panel Displays
Notebook Computers
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Operating Junction Temperature Range TJ40 to +125 °C
Storage Temperature Range Tstg 55 to +150 °C
Lead Solder Temperature
Maximum (10 Seconds)
TL260 °C
IEC 6100042 Contact
IEC 6100042 Air
ISO 10605 330 pF / 330 W Contact
ISO 10605 330 pF / 2 kW Contact
ISO 10605 150 pF / 2 kW Contact
ESD ±8
±15
±10
±21
±30
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
See Application Note AND8308/D for further description of
survivability specs.
www.onsemi.com
MARKING
DIAGRAMS
X2 MG
G
XXX = Specific Device Code
M = Date Code
G= PbFree Package
1
6
1
SC88
W1 SUFFIX
CASE 419B
(Note: Microdot may be in either location)
5
3
6
2
14
X4 MG
G
1
6
1
SC88
W1 SUFFIX
CASE 419B
P4H MG
G
1
6
TSOP6
CASE 318G
STYLE 12
1
SOT563
CASE 463A
P4MG
G
1
1
6
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
TekRun:2.SDGS/s Sample m TekRun:2.SDGS/s Sample m [T l [T l W + + M20.ons Chl .r 31.2v Em mom M20.ons Chl x 739.2v www onsem' com
NUP4114 Series
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2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
IFForward Current
VFForward Voltage @ IF
Ppk Peak Power Dissipation
CCapacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
UniDirectional
IPP
IF
V
I
IR
IT
VRWM
VCVBR
VF
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM 5.5 V
Breakdown Voltage VBR IT = 1 mA, (Note 1) 5.5 6.5 V
Reverse Leakage Current IRVRWM = 5.5 V 1.0 mA
Clamping Voltage VCIPP = 1 A (Note 2) 8.3 10 V
IPP = 5 A (Note 3) 8.5 9.0 V
IPP = 8 A (Note 3) 9.2 10 V
ESD Clamping Voltage VCPer IEC6100042 (Note 4) See Figures 1 & 2
Maximum Peak Pulse Current IPP 8/20 ms Waveform (Note 3) 12 A
Junction Capacitance CJVR = 0 V, f = 1 MHz between I/O Pins and GND 0.6 pF
VR = 0 V, f = 1 MHz between I/O Pins 0.3 pF
1. VBR is measured at pulse test current IT
.
2. Nonrepetitive current pulse (I/O to GND).
3. Nonrepetitive current pulse (Pin 5 to Pin 2)
4. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC6100042
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC6100042
NUP4114 Series
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3
IEC 6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC6100042 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 3. IEC6100042 Spec
Figure 4. Diagram of ESD Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8308/D Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8/20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
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NUP4114 Series
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4
Figure 6. 500 MHz Data Pattern
ORDERING INFORMATION
Device Marking Package Shipping
NUP4114UCLW1T1G X2
SC88
(PbFree) 3000 / Tape & Reel
NUP4114UCLW1T2G X2
SZNUP4114UCLW1T2G X2
NUP4114UCW1T2G X4
NUP4114UPXV6T1G
P4 SOT563
(PbFree) 4000 / Tape & Reel
NUP4114UPXV6T2G
NUP4114HMR6T1G P4H TSOP6
(PbFree) 3000 / Tape & Reel
SZNUP4114HMR6T1G P4H
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
diodes and an ESD diode integrated in a sing1e package (TSOP—o). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. This device protects the power 1ine against overvo1tage conditions to avoid damage to the power supply and any downstream components. NUP4114 Configuration Options The NUP4114 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for c1arnping purposes. The steering diodes will be forward biased whenever the voltage on the protected 1ine exceeds the reterence vo1tage (v[ or Vcc + VI). The diodes will force the transient current to bypass the sensitive circuit. Data lines are connected at pins 1, 3, 4 and (r. The negative reference is connected at pin 2. This pin roast be connected directly to ground by u ing a ground plane to minimize the PCB's ground inductance. It is very important to reduce the PCB trace 1engths as much as possib1e to minimize parasitic inductances. Option 1 Protection of four d a lines and the power supply rising vcc as ret‘erence. I/O 1 I/O 2 I/O (3 I/O 4 For this configuration, connect pin 5 directly to the positive sappIy rai1 (vcc), the data lines are referenced to the supply voltage. The internal EsD diode prevents overvo1tage on the snppiy rai1. Biasing nfihe steering diodes reduces their capacitance. www.cnsemi.com 5
NUP4114 Series
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5
APPLICATIONS INFORMATION
The new NUP4114 is a low capacitance ESD diode array
designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used in high speed I/O data lines. The integrated
design of the NUP4114 offers low capacitance steering
diodes and an ESD diode integrated in a single package
(TSOP6). If a transient condition occurs, the steering
diodes will drive the transient to the positive rail of the
power supply or to ground. This device protects the power
line against overvoltage conditions to avoid damage to the
power supply and any downstream components.
NUP4114 Configuration Options
The NUP4114 is able to protect up to four data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or
VCC + Vf). The diodes will force the transient current to
bypass the sensitive circuit.
Data lines are connected at pins 1, 3, 4 and 6. The negative
reference is connected at pin 2. This pin must be connected
directly to ground by using a ground plane to minimize the
PCB’s ground inductance. It is very important to reduce the
PCB trace lengths as much as possible to minimize parasitic
inductances.
Option 1
Protection of four data lines and the power supply using
VCC as reference.
I/O 1
I/O 2
I/O 3
I/O 4
VCC
6
5
4
1
2
3
For this configuration, connect pin 5 directly to the
positive supply rail (VCC), the data lines are referenced to
the supply voltage. The internal ESD diode prevents
overvoltage on the supply rail. Biasing of the steering diodes
reduces their capacitance.
Option 2
Protection of four data lines with bias and power supply
isolation resistor.
VCC
10 k
I/O 1
I/O 2
I/O 3
I/O 4
6
5
4
1
2
3
The NUP4114 can be isolated from the power supply by
connecting a series resistor between pin 5 and VCC. A 10 kW
resistor is recommended for this application. This will
maintain a bias on the internal ESD and steering diodes,
reducing their capacitance.
Option 3
Protection of four data lines using the internal ESD diode
as reference.
I/O 1
I/O 2
I/O 3
I/O 4
NC
6
5
4
1
2
3
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal ESD can be used as the reference. For
these applications, pin 5 is not connected. In this
configuration, the steering diodes will conduct whenever the
voltage on the protected line exceeds the working voltage of
the ESD plus one diode drop (VC = Vf + VESD).
ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
NUP4114 Series
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6
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
VCC
D1
D2
Data Line
IESDpos
IESDneg
VF + VCC
VF
IESDpos
IESDneg
Power
Supply
Protected
Device
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:
For positive pulse conditions:
Vc = VCC + VfD1
For negative pulse conditions:
Vc = VfD2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.
VCC
D1
D2
Data Line
IESDpos
IESDneg
VC = VCC + Vf + (L diESD/dt)
IESDpos
IESDneg
Power
Supply
Protected
Device
VC = Vf (L diESD/dt)
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = VCC + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
L diESD/dt factor. A relatively small trace inductance can
result in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board
layout. Taking care to minimize the effects of parasitic
inductance will provide significant benefits in transient
immunity.
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD
events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
therefore higher capacitance. This capacitance becomes
problematic as transmission frequencies increase. Reducing
capacitance generally requires reducing die size. These
small die will have higher forward voltage characteristics at
typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.
The ON Semiconductor NUP4114 was developed to
overcome the disadvantages encountered when using
discrete diodes for ESD protection. This device integrates an
ESD diode within a network of steering diodes.
Figure 7. NUP4114 Equivalent Circuit
5
3
6
2
14
During an ESD condition, the ESD current will be driven
to ground through the ESD diode as shown below.
VCC
D1
D2
Data Line
IESDpos
Power
Supply
Protected
Device
The resulting clamping voltage on the protected IC will
be:
Vc = VF + VESD.
The clamping voltage of the ESD diode depends on the
magnitude of the ESD current. The steering diodes are fast
switching devices with unique forward voltage and low
capacitance characteristics.
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TSOP6
CASE 318G02
ISSUE V
DATE 12 JUN 2012
SCALE 2:1
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
23
456
D
1
e
b
E1
A1
A
0.05
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
c
STYLE 2:
PIN 1. EMITTER 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. BASE 2
6. COLLECTOR 2
STYLE 3:
PIN 1. ENABLE
2. N/C
3. R BOOST
4. Vz
5. V in
6. V out
STYLE 4:
PIN 1. N/C
2. V in
3. NOT USED
4. GROUND
5. ENABLE
6. LOAD
XXX MG
G
XXX = Specific Device Code
A =Assembly Location
Y = Year
W = Work Week
G= PbFree Package
STYLE 5:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 6:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 7:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. N/C
5. COLLECTOR
6. EMITTER
STYLE 8:
PIN 1. Vbus
2. D(in)
3. D(in)+
4. D(out)+
5. D(out)
6. GND
GENERIC
MARKING DIAGRAM*
STYLE 9:
PIN 1. LOW VOLTAGE GATE
2. DRAIN
3. SOURCE
4. DRAIN
5. DRAIN
6. HIGH VOLTAGE GATE
STYLE 10:
PIN 1. D(OUT)+
2. GND
3. D(OUT)
4. D(IN)
5. VBUS
6. D(IN)+
1
1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 11:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1/GATE 2
STYLE 12:
PIN 1. I/O
2. GROUND
3. I/O
4. I/O
5. VCC
6. I/O
*This information is generic. Please refer to device data sheet
for actual part marking. PbFree indicator, “G” or microdot “
G”, may or may not be present.
XXXAYWG
G
1
STANDARDIC
XXX = Specific Device Code
M = Date Code
G= PbFree Package
DIM
A
MIN NOM MAX
MILLIMETERS
0.90 1.00 1.10
A1 0.01 0.06 0.10
b0.25 0.38 0.50
c0.10 0.18 0.26
D2.90 3.00 3.10
E2.50 2.75 3.00
e0.85 0.95 1.05
L0.20 0.40 0.60
0.25 BSC
L2
0°10°
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
STYLE 14:
PIN 1. ANODE
2. SOURCE
3. GATE
4. CATHODE/DRAIN
5. CATHODE/DRAIN
6. CATHODE/DRAIN
STYLE 15:
PIN 1. ANODE
2. SOURCE
3. GATE
4. DRAIN
5. N/C
6. CATHODE
1.30 1.50 1.70
E1
E
RECOMMENDED
NOTE 5
L
C
M
H
L2
SEATING
PLANE
GAUGE
PLANE
DETAIL Z
DETAIL Z
0.60
6X
3.20 0.95
6X
0.95
PITCH
DIMENSIONS: MILLIMETERS
M
STYLE 16:
PIN 1. ANODE/CATHODE
2. BASE
3. EMITTER
4. COLLECTOR
5. ANODE
6. CATHODE
STYLE 17:
PIN 1. EMITTER
2. BASE
3. ANODE/CATHODE
4. ANODE
5. CATHODE
6. COLLECTOR
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
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DOCUMENT NUMBER:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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TSOP6
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SC88/SC706/SOT363
CASE 419B02
ISSUE Y
DATE 11 DEC 2012
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
Cddd M
123
A1
A
c
654
E
b
6X
XXXMG
G
XXX = Specific Device Code
M = Date Code*
G= PbFree Package
GENERIC
MARKING DIAGRAM*
1
6
STYLES ON PAGE 2
1
DIM MIN NOM MAX
MILLIMETERS
A−−− −−− 1.10
A1 0.00 −−− 0.10
ddd
b0.15 0.20 0.25
C0.08 0.15 0.22
D1.80 2.00 2.20
−−− −−− 0.043
0.000 −−− 0.004
0.006 0.008 0.010
0.003 0.006 0.009
0.070 0.078 0.086
MIN NOM MAX
INCHES
0.10 0.004
E1 1.15 1.25 1.35
e0.65 BSC
L0.26 0.36 0.46
2.00 2.10 2.20
0.045 0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.078 0.082 0.086
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.65
0.66
6X
DIMENSIONS: MILLIMETERS
0.30
PITCH
2.50
6X
RECOMMENDED
TOP VIEW
SIDE VIEW END VIEW
bbb H
B
SEATING
PLANE
DETAIL A E
A2 0.70 0.90 1.00 0.027 0.035 0.039
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
ccc 0.10 0.004
A-B D
aaa C
2X 3 TIPS
D
E1
D
e
A
2X
aaa H D
2X
D
L
PLANE
DETAIL A
H
GAGE
L2
C
ccc C
A2
6X
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42985B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SC88/SC706/SOT363
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
ON Semxcunduclm and are hademavks av Semxcanduclur Campunenls lnduslnes. uc dha ON Samanaucxar ar us suhsxdxanes m xna Umled sxaxas andJm mhev cmm‘nes ON Semxcunduclar vesewes me “gm to make changes wuhum mnna. mouse to any pruduns necem ON Semanduc‘m makes nu wanamy. represenlalmn m guarantee regardmg ma sumahmly at W; manual: can any pamcu‘av purpase nnv dues ON Semumnduclm assume any Mammy snsmg mm xna aapncauan m use M any pmduclnv mum and specmcsl‘y dwsc‘axms any and an Mammy mc‘udmg wxlham hmma‘mn spema‘ cansequemm m \nmdeula‘ damages ON Semxmnduclar dues nn| away any hcense under Ms pa|EM nghls Ivar xna ngms av n|hers
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 3:
CANCELLED
STYLE 2:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
SC88/SC706/SOT363
CASE 419B02
ISSUE Y
DATE 11 DEC 2012
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ASB42985B
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SC88/SC706/SOT363
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOT563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
SCALE 4:1
1
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON11126D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
SOT563, 6 LEAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOTrSGG, 6 LEAD CASE 463A 1SSUE H DATE 26 JAN 2021 STYLE 11 STYLE 21 STVLE 31 PIN l. EMITTER 1 FIN 11 EMITTER 1 FIN 11 CATHDDE l 2. EASE 1 2. EMITTER 2 2. CATHDDE 1 3. CEILLECTEIR 2 3. EASE 2 31 ANEIDE/ANEIDE 2 GENERIC 4. EMITTER 2 4. 1211151:qu 2 4. CATHDDE 2 MARKING DIAGRAM‘ 5. EASE E 5. BASE 1 5 CATHDDE 2 s. CEILLECTEIR 1 s. CEILLECTEIR 1 s. ANDDE/ANDDE 1 n n n xx M- 51111: 41 STYLE 51 STYLE 51 1 ‘L U U FIN 1. CEILLECTDR FIN 1 CATHDDE PIN 1 CATHDDE 2. CEILLECTEIR 2. CATHDDE 2. ANDDE xx :Specmc meme Code 3. EASE 3. ANDDE 3 CATHDDE 4. EMITTER 4. ANDDE 4. CATHDDE M Mm“ 0°“ 5. CEILLECTEIR 5. CATHDDE 5. CATHDDE - an-Fvee Package 5. CEILLECTEIR S. CATHDDE S1 CATHDDE > > "rms mmmamn 1s genenc. Please vefer 1o device aa1a sheel Io! ac1ua1 pan markmg. £11112 7‘ STYLE 9‘ STVLE 9‘ Pb—Free1nd1ca1or,“G"ermcmaew may FIN 1. CATHDDE FIN 1. DRAIN FIN 1. SDURCE 1 Oman/"Owe Dresem-Some Dreams may 2. ANEIDE E. DRAIN E1 GATE 1 “0| 'OI‘OW Ihe Genenc Markmg 3. 12111111111: :. GATE 3. DRAIN 2 4. CATHDDE 4. SEIURCE 4 SEIURCE 2 5. ANDDE 5. 11mm 5. GATE 2 s. CATHDDE s. DRAIN s DRAIN 1 311115 1111 STYLE 111 PIN 1. CATHDDE 1 PIN 1. 51111152 2 2. WC 2. EASE a 3. can-1mm 2 3. CEILLECTEIR 1 4. ANDDE 2 4. EMITTER 1 5. NI!) 5. EASE 1 s. ANDDE 1 e. CEILLECTEIR 2 011 5111111111111 111 J 1111111111 11S1111111111111¢111111111111.111.111.111 111 011 11.111111111111111 11.111111111111111 111111 S1111 111111.1111111111111 011 S11111111111111111111.1111111111 .1111 1111111 1111111111111111111111 1111 11111111 111111 01 51111111111111 11111 11 w1.111111.11111111111111 11111111111111111111 111 111111111111 11111 11111111111111 1111111111111111 1111 011 11111111111111 1111111 111111111111 11111 11111111 111111111 1. 11111 111111111 11111 111 11111111111y 1111111111 111 1111 111 11111111 111111111 w111111 1111111111 1111111 1111111111111. 1111111111 11111111 011 5111m111111111111 111111111 111111111 111111111 111111111111 111 11111 11111111
SOT563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
XX = Specific Device Code
M = Month Code
G= PbFree Package
XX MG
GENERIC
MARKING DIAGRAM*
1
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON11126D
DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
SOT563, 6 LEAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
a a e lrademavks av Semxcunduclm Cnmvnnems In "sine \ghlsmanumhernlpalems \rademavks Dav www menu cumrsuerguwaxem Mavkmg gm 9 www nnserm cum
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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