PIC18F2X/4XQ10 Brief Datasheet by Microchip Technology

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6‘ MICRDCHIP
PIC18F2X/4XQ10
PIC18F2X/4XQ10 Product Brief
Description
PIC18F2x/4xQ10 microcontrollers feature analog, core independent, and communication peripherals for a
wide range of general purpose and low-power applications. These 28/40/44-pin devices are equipped
with a 10-bit ADC with Computation (ADC2) automating Capacitive Voltage Divider (CVD) techniques for
advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold
comparisons. They also offer a set of core independent peripherals such as Complementary Waveform
Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory
Scan, Zero-Cross Detect (ZCD), Configurable Logic Cell (CLC), and Peripheral Pin Select (PPS),
providing increased design flexibility and lower system cost.
Core Features
C Compiler Optimized RISC Architecture
Operating Speed:
DC – 64 MHz clock input over the full VDD range
62.5 ns minimum instruction cycle
Programmable 2-Level Interrupt Priority
31-Level Deep Hardware Stack
Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Four 16-Bit Timers (TMR0/1/3/5)
Low-Current Power-on Reset (POR)
Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
Watchdog Reset on too long or too short interval between watchdog clear events
Variable prescaler selection
Variable window size selection
All sources configurable in hardware or software
Memory
Up to 128K Bytes Program Flash Memory
Up to 3615 Bytes Data SRAM Memory
Up to 1024 Bytes Data EEPROM
Programmable Code Protection
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 1
Direct, Indirect and Relative Addressing modes
Operating Characteristics
Operating Voltage Range:
1.8V to 5.5V
Temperature Range:
Industrial: -40°C to 85°C
Extended: -40°C to 125°C
Power-Saving Operation Modes
Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)
Idle: CPU Halted While Peripherals Operate
Sleep: Lowest Power Consumption
Peripheral Module Disable (PMD):
Ability to selectively disable hardware module to minimize active power consumption of unused
peripherals
Extreme Low-Power mode (XLP)
Sleep: 500 nA typical @ 1.8V
Sleep and Watchdog Timer: 900 nA typical @ 1.8V
Digital Peripherals
Configurable Logic Cell (CLC):
Integrated combinational and sequential logic
Complementary Waveform Generator (CWG):
Rising and falling edge dead-band control
Full-bridge, half-bridge, 1-channel drive
Multiple signal sources
Capture/Compare/PWM (CCP) modules:
Two CCPs
16-bit resolution for Capture/Compare modes
10-bit resolution for PWM mode
10-Bit Pulse-Width Modulators (PWM):
Two 10-bit PWMs
Serial Communications:
Up to Two Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start,
RS-232, RS-485, LIN compatible
– SPI
– I2C, SMBus and PMBus compatible
Up to 35 I/O Pins and One Input Pin:
Individually programmable pull-ups
Slew rate control
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 2
Interrupt-on-change on all pins
Input level selection control
Programmable CRC with Memory Scan:
Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)
Calculate CRC over any portion of Flash or EEPROM
High-speed or background operation
Hardware Limit Timer (TMR2/4/6+HLT):
Hardware monitoring and Fault detection
Peripheral Pin Select (PPS):
Enables pin mapping of digital I/O
Data Signal Modulator (DSM)
Analog Peripherals
10-Bit Analog-to-Digital Converter with Computation (ADC2):
Up to 35 external channels
Conversion available during Sleep
Four internal analog channels
Internal and external trigger options
Automated math functions on input signals:
Averaging, filter calculations, oversampling and threshold comparison
8-bit hardware acquisition timer
Hardware Capacitive Voltage Divider (CVD) Support:
8-bit precharge timer
Adjustable Sample-and-Hold capacitor array
Guard ring digital output drive
Zero-Cross Detect (ZCD):
Detect when AC signal on pin crosses ground
5-Bit Digital-to-Analog Converter (DAC):
Output available externally
Programmable 5-bit voltage (% of VDD,[VREF+ - VREF-], FVR)
Internal connections to comparators and ADC
Two Comparators (CMP):
Four external inputs
External output via PPS
Fixed Voltage Reference (FVR) Module:
1.024V, 2.048V and 4.096V output levels
Two buffered outputs: One for DAC/CMP and one for ADC
Clocking Structure
High-Precision Internal Oscillator Block (HFINTOSC):
Selectable frequencies up to 64 MHz
±1% at calibration
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 3
32 kHz Low-Power Internal Oscillator (LFINTOSC)
External 32 kHz Crystal Oscillator (SOSC)
External High-frequency Oscillator Block:
Three crystal/resonator modes
Digital Clock Input mode
4x PLL with external sources
Fail-Safe Clock Monitor:
Allows for safe shutdown if external clock stops
Oscillator Start-up Timer (OST)
Programming/Debug Features
In-Circuit Serial Programming (ICSP) via Two Pins
In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
Debug Integrated On-Chip
PIC18F2x/4xQ10 Family Types
Table 1.  Devices included in this family
Device
Program Memory Flash
(bytes)
Data SRAM
(bytes)(2)
Data EEPROM
(bytes)
I/O Pins
16-bit Timers
Comparators
10-bit ADC2 with
Computation (ch)
5-bit DAC
Zero-Cross Detect
CCP/10-bit PWM
CWG
CLC
Low Voltage Detect (LVD)
8-bit TMR with HLT
Windowed Watchdog
Timer
CRC with Memory Scan
EUSART
I2C/SPI
PPS
Peripheral Module Disable
Temperature Indicator
Debug(1)
PIC18F24Q10 16k 1280 256 25 4 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I
PIC18F25Q10 32k 2304 256 25 4 2 24 1 1 2/2 1 0 1 3 Y Y 1 1 Y Y Y I
PIC18F26Q10 64k 3615 1024 25 4 2 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I
PIC18F27Q10 128k 3615 1024 25 4 2 24 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I
PIC18F45Q10 32k 2304 256 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I
PIC18F46Q10 64k 3615 1024 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I
PIC18F47Q10 128k 3615 1024 36 4 2 35 1 1 2/2 1 8 1 3 Y Y 2 2 Y Y Y I
Note: 
1. Debugging Methods: (I) – Integrated on-chip.
2. SRAM includes 256 bytes of SECTOR space which is not included in the data size displayed by MPLAB X.
Packages
Important:  For other small form-factor package availability and marking information, visit
http://www.microchip.com/packaging or contact your local Microchip sales office.
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 4
11111111111111 EEEEEEEEEEEEEE
Packages SPDIP
(SP)
SOIC
(SO)
SSOP
(SS)
QFN
(ML)
(6x6x0.9)
VQFN
(STX)
(4x4x1)
TQFP
(PT)
PDIP
(P)
QFN
(MP)
(5x5x0.9)
PIC18F24Q10 ● ●
PIC18F25Q10 ● ●
PIC18F26Q10 ● ●
PIC18F27Q10 ● ●
PIC18F45Q10 ● ●
PIC18F46Q10 ● ●
PIC18F47Q10 ● ●
Important:  Pin details are subject to change.
Pin Diagrams
Figure 1. 28-pin SPDIP, SSOP, SOIC
Filename: 00-000028A.vsd
Title: 28-pin DIP
Last Edit: 10/3/2018
First Used: N/A
Notes: Generic 28-pin dual in-line diagram
Rev. 00-000028A
10/3/2018
MCLR/VPP/RE3 28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC0
RC1
RC2
RC3 RC4
RC5
RC6
RC7
VSS
VDD
RB0
RB1
RB2
RB3
RB4
RB5
RB6/ICSPCLK
RB7/ICSPDAT
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 5
jjjjjjjjjjjjjjjjjjjj EEEEEEEEEEEEEEEEEEEE
Figure 2. 28-pin QFN VQFN
Rev. 00-000028B
6/23/2017
28 27
RB3
RB2
RC7
RB5
RB4
VSS
RB1
RB0
VDD
RB6/ICSPCLK
RB7/ICSPDAT
RE3/MCLR/VPP
RA0
RA1
26 25 24 23 22
8 9 10 11 12 13 14
15
16
17
18
19
20
21
7
6
5
4
3
2
1
RC5
RC6
RC4
RC3
RC2
RC1
RC0
RA2
RA3
RA6
RA7
RA4
RA5
VSS
Note:  It is recommended that the exposed bottom pad be connected to VSS, however it must not be the
only VSS connection to the device.
Figure 3. 40-pin PDIP
Filename: 00-000040A.vsd
Title: 40-pin DIP
Last Edit: 10/3/2018
First Used: N/A
Notes: Generic 40-pin dual in-line diagram
Rev. 00-000040A
10/3/2018
MCLR/VPP/RE3 40
39
38
37
36
35
34
33
32
31
30
29
28
27
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
RB4
RB5
RB6/ICSPCLK
RB7/ICSPDAT
15
16
17
18
19
20
26
25
24
23
22
21
RD0
RD1
VDD
RE0
RE1
RE2
RD2
RD3
RC4
RC5
RC6
RC7
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 6
Eds.
Figure 4. 40-pin QFN
Filename: 00-000040B.vsd
Title: 40-pin QFN
Last Edit: 11/6/2017
First Used: N/A
Notes: Generic 40-pin QFN diagram
Rev. 00-000040B
11/6/2017
40 39
RC0
RA6
RE1
RE0
RA5
RA4
RC1
RC2
RC3
RD1
RD0
RE2
RA7
VSS
VDD
RD2
RD3
RC4
RC5
RC6
38 37 36 35 34 33 32 31
11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
10
9
8
7
6
5
4
3
2
1
RA3
RA2
RA1
VPP/MCLR/RE3
RA0
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
RB3
RC7
RD4
VDD
RB0
RB1
RB2
VSS
RD5
RD6
RD7
Note:  It is recommended that the exposed bottom pad be connected to VSS, however it must not be the
only VSS connection to the device.
Figure 5. 44-pin TQFP
Filename: 00-000044A.vsd
Title: 44-pin TQFP
Last Edit: 11/6/2017
First Used: N/A
Notes: Generic 44-pin TQFP diagram
Rev. 00-000044A
11/6/2017
40 39
RA6
RA7
RE1
RE0
RA5
RA4
RC1
RC2
RC3
RD1
RD0
RE2
NC
VSS
VDD
RD2
RD3
RC4
RC5
RC6
38 37 36 35 34
33
32
31
12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
10
9
8
7
6
5
4
3
2
1
RA3
RA2
RA1
VPP/MCLR/RE3
RA0
ICSPDAT/RB7
ICSPCLK/RB6
RB5
RB4
RB3
RC7
RD4
VDD
RB0
RB1
RB2
VSS
RD5
RD6
RD7
11
44 43 42 41
NC
NC
NC
RC0
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 7
m m m (1) 7m m i“, m m m (1) m m m m m m m m m (‘3)
Pin Allocation Tables
Table 2. 28-Pin Allocation Table
I/O(2)
28-Pin
SPDIP,
SOIC,
SSOP
28-Pin
VQFN A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-
up Basic
RA0 2 27 ANA0 C1IN0-
C2IN0-
— IOCA0 Y
RA1 3 28 ANA1 C1IN1-
C2IN1-
— IOCA1 Y
RA2 4 1 ANA2 DAC1OUT1
VREF- (DAC)
VREF- (ADC)
C1IN0+
C2IN0+
— IOCA2 Y
RA3 5 2 ANA3 VREF+ (DAC)
VREF+ (ADC)
C1IN1+ — IOCA3 MDCARL(1) — Y
RA4 6 3 ANA4 — T0CKI(1) — IOCA4 MDCARH(1) — Y
RA5 7 4 ANA5 — IOCA5 MDSRC(1) SS1(1) Y —
RA6 10 7 ANA6 — IOCA6 Y CLKOUT
OSC2
RA7 9 6 ANA7 — IOCA7 Y OSC1
CLKIN
RB0 21 18 ANB0 C2IN1+ — CWG1(1) ZCDIN IOCB0
INT0(1)
— SS2(1) Y —
RB1 22 19 ANB1 C1IN3-
C2IN3-
— IOCB1
INT1(1)
— SCK2(1)
SCL2(3,4)
Y —
RB2 23 20 ANB2 — IOCB2
INT2(1)
— SDI2(1)
SDA2(3,4)
Y —
RB3 24 21 ANB3 C1IN2-
C2IN2-
— IOCB3 Y
RB4 25 22 ANB4 T5G(1) — IOCB4 Y
RB5 26 23 ANB5 T1G(1) — IOCB5 Y
RB6 27 24 ANB6 — IOCB6 Y ICSPCLK
RB7 28 25 ANB7 DAC1OUT2 T6IN(1) — IOCB7 Y ICSPDAT
RC0 11 8 ANC0 — T1CKI(1)
T3CKI(1)
T3G(1)
— IOCC0 Y SOSCO
RC1 12 9 ANC1 — CCP2(1) — IOCC1 Y SOSCIN
SOSCI
RC2 13 10 ANC2 T5CKI(1) CCP1(1) — IOCC2 Y
RC3 14 11 ANC3 T2IN(1) — IOCC3 SCK1(1)
SCL1(3,4)
Y —
RC4 15 12 ANC4 — IOCC4 SDI1(1)
SDA1(3,4)
Y —
RC5 16 13 ANC5 T4IN(1) — IOCC5 Y
RC6 17 14 ANC6 IOCC6 CK1(1,3) — Y
RC7 18 15 ANC7 — IOCC7 RX1/
DT1(1,3)
— Y
RE3 1 26 IOCE3 Y Vpp/MCLR
VSS 19 16 — — VSS
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 8
(5) (2) (3) N W N i“) U) i”) (1) N
...........continued
I/O(2)
28-Pin
SPDIP,
SOIC,
SSOP
28-Pin
VQFN A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-
up Basic
VDD(5) 20 17 — VDD
VSS 8 5 — — VSS
OUT(2) — ADGRDA
ADGRDB
— C1OUT
C2OUT
TMR0 CCP1
CCP2
PWM3
PWM4
CWG1A
CWG1B
CWG1C
CWG1D
— TX1/CK1(3)
DT1(3)
DSM SDO1
SCK1
— —
Note: 
1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the
peripheral input selection table for details on which port pins may be used for this signal.
2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the
peripheral output selection table.
3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will
operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
5. A 0.1 uF bypass capacitor to VSS is required on the VDD pin.
Table 3.  40/44-Pin Allocation Table
I/O(2) 40-Pin
PDIP
40-
Pin
QFN
44-Pin
TQFP A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-
up Basic
RA0 2 17 19 ANA0 C1INO-
C2IN0-
— IOCA0 Y
RA1 3 18 20 ANA1 C1IN1-
C2IN1-
— IOCA1 Y
RA2 4 19 21 ANA2 DAC1OUT1
VREF-
(DAC5)
VREF-
(ADC)
C1IN0+
C2IN0+
— IOCA2 Y
RA3 5 20 22 ANA3 VREF+
(DAC5)
VREF+
(ADC)
C1IN1+ — IOCA3 MDCARL(1) — Y
RA4 6 21 23 ANA4 T0CKI(1) — IOCA4 MDCARH(1) — Y
RA5 7 22 24 ANA5 — IOCA5 MDSRC(1) SS1(1) Y —
RA6 14 29 31 ANA6 IOCA6 Y CLKOUT
OSC2
RA7 13 28 30 ANA7 — IOCA7 Y OSC1
CLKIN
RB0 33 8 8 ANB0 C2IN1+ — CWG1(1) ZCDIN IOCB0
INT0(1)
— SS2(1) Y —
RB1 34 9 9 ANB1 C1IN3-
C2IN3-
— IOCB1
INT1(1)
— SCK2(1)
SCL2(3,4)
Y —
RB2 35 10 10 ANB2 — IOCB2
INT2(1)
— SDI2(1)
SDA2(3,4)
Y —
RB3 36 11 11 ANB3 C1IN2-
C2IN2-
— IOCB3 Y
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 9
(1) (1) (5) (5) (2) N (1) N (1) W N N (13’ N (13’
...........continued
I/O(2) 40-Pin
PDIP
40-
Pin
QFN
44-Pin
TQFP A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-
up Basic
RB4 37 12 14 ANB4 T5G(1) — IOCB4 Y
RB5 38 13 15 ANB5 T1G(1) — IOCB5 Y
RB6 39 14 16 ANB6 IOCB6 CK2(1,3) Y ICSPCLK
RB7 40 15 17 ANB7 DAC1OUT2 T6IN(1) — IOCB7 RX2/
DT2(1,3)
Y ICSPDAT
RC0 15 30 32 ANC0 T1CKI(1)
T3CKI(1)
T3G(1)
— IOCC0 Y SOSCO
RC1 16 31 35 ANC1 — CCP2(1) — IOCC1 Y SOSCIN
SOSCI
RC2 17 32 36 ANC2 T5CKI(1) CCP1(1) — IOCC2 Y
RC3 18 33 37 ANC3 T2IN(1) — IOCC3 SCK1(1)
SCL1(3,4)
Y —
RC4 23 38 42 ANC4 — IOCC4 SDI1(1)
SDA1(3,4)
— —
RC5 24 39 43 ANC5 T4IN(1) — IOCC5 Y
RC6 25 40 44 ANC6 IOCC6 CK1(1,3) — Y
RC7 26 1 1 ANC7 — IOCC7 RX1/
DT1(1,3)
— Y
RD0 19 34 38 AND0 Y
RD1 20 35 39 AND1 Y
RD2 21 36 40 AND2 Y
RD3 22 37 41 AND3 Y
RD4 27 2 2 AND4 Y
RD5 28 3 3 AND5 Y
RD6 29 4 4 AND6 Y
RD7 30 5 5 AND7 Y
RE0 8 23 25 ANE0 Y
RE1 9 24 26 ANE1 Y
RE2 10 25 27 ANE2 Y
RE3 1 16 18 IOCE3 Y Vpp/MCLR
VSS 12 6 6 VSS
VDD(5) 11 7 7 VDD
VDD(5) 32 26 28 VSS
VSS 31 27 29 VSS
OUT(2) — ADGRDA
ADGRDB
— C1OUT
C2OUT
TMR0 CCP1
CCP2
PWM3
PWM4
CWG1A
CWG1B
CWG1C
CWG1D
— — TX1/
CK1(3)
DT1(3)
TX2/
CK2(3)
DT2(3)
DSM SDO1
SCK1
SDO2
SCK2
— —
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 10
Note: 
1. This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the
peripheral input selection table for details on which port pins may be used for this signal.
2. All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the
peripheral output selection table.
3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will
operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
5. A 0.1 uF bypass capacitor to VSS is required on all VDD pins.
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 11
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Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the
operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 12
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the
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Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud,
chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST,
SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight
Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming,
ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 13
© 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-4338-4
Quality Management System Certified by DNV
ISO/TS 16949
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer
fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC®
DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design and manufacture of development
systems is ISO 9001:2000 certified.
PIC18F2X/4XQ10
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 14
’8‘ MICFIDCHIP
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Worldwide Sales and Service
© 2019 Microchip Technology Inc. Product Brief DS40001920C-page 15

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