LTC3564 Datasheet by Analog Devices Inc.

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L7 I [Mp LTC3564 TECHNOLOGY HE L7 LIES/Q .n—
1
LTC3564
3564f
High Efficiency: Up to 96%
Very Low Quiescent Current: Only 20
μ
A
1.25A Output Current
2.5V to 5.5V Input Voltage Range
2.25MHz Constant Frequency Operation
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
0.6V Reference Allows Low Output Voltages
Shutdown Mode Draws 1μA Supply Current
Current Mode Operation for Excellent Line and
Load Transient Response
Overtemperature Protected
Low Profile (1mm) ThinSOT
TM
and
6-Lead (2mm × 3mm) DFN Packages
The LTC
®
3564 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 20μA, dropping to 1μA in shutdown. The 2.5V to
5.5V input voltage range makes the LTC3564 ideally suited
for single Li-Ion battery-powered or 3.3V to 5V input
voltage applications. 100% duty cycle provides low drop-
out operation, extending battery life in portable systems.
Automatic Burst Mode
®
operation increases efficiency at
light loads, further extending battery runtime.
Switching frequency is internally set at 2.25MHz, allowing
the use of small surface mount inductors and capacitors.
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.6V feed-
back reference voltage. The LTC3564 is available in low
profile (1mm) ThinSOT and 6-Lead (2mm × 3mm) DFN
packages.
Cellular Telephones
Wireless and DSL Modems
Digital Still Cameras
Media Players
Portable Instruments
Point of Load Regulation
2.25MHz, 1.25A
Synchronous
Step-Down Regulator
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5481178, 6580258, 6304066, 6498466, 6611131.
VIN
CIN
22μF
CER
VIN
LTC3564
RUN
1.1μH
22pF
634k
316k
3564 TA01a
SW
VFB
GND
COUT
22μF
CER
VOUT
1.8V
OUTPUT CURRENT (mA)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
1 10 100 1000 10000
3564 TA01b
30
20
10
0
90
100
0.0001
0.001
0.01
0.1
0.00001
1
10
VOUT = 1.8V
VIN = 2.7V
VIN = 3.6V
VIN = 4.2V
: : :z: swam» L L7
2
LTC3564
3564f
Input Supply Voltage ..................................0.3V to 6V
RUN, V
FB
Voltages ..................................... 0.3V to V
IN
SW Voltage (DC) ......................... 0.3V to (V
IN
+ 0.3V)
(Note 1)
Operating Junction Temperature Range
(Notes 2, 3, 6) ...................................... 40°C to 125°C
Storage Temperature Range ................ 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
VFB
Feedback Current ±30 nA
V
FB
Regulated Feedback Voltage (Note 4) 0.5880 0.6 0.6120 V
ΔV
FB
Reference Voltage Line Regulation V
IN
= 2.5V to 5.5V (Note 4) 0.04 0.4 %/V
I
PK
Peak Inductor Current V
IN
= 3V, V
FB
= 0.5V, Duty Cycle < 35% 1.5 2.0 2.5 A
V
LOADREG
Output Voltage Load Regulation 0.5 %
V
IN
Input Voltage Range 2.5 5.5 V
The denotes specifications which apply over the full operating junction temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.
ELECTRICAL CHARACTERISTICS
T
JMAX
= 125°C, θ
JA
= 215°C/ W, θ
JC
= 50°C/ W
V
FB
1
GND 2
V
IN
3
5 RUN
4 SW
TOP VIEW
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
TOP VIEW
RUN
SGND
VFB
SW
PGND
VIN
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
4
5
7
6
3
2
1
T
JMAX
= 125°C, θ
JA
= 64°C/ W, θ
JC
= 10.6°C/ W
EXPOSED PAD (PIN 7) IS SGND, MUST BE SOLDERED TO PCB
PI CO FIGURATIO
UUU
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3564ES5#PBF LTC3564ES5#TRPBF LTCYJ 5-Lead Plastic TSOT-23 40°C to 125°C
LTC3564IS5#PBF LTC3564IS5#TRPBF LTCYJ 5-Lead Plastic TSOT-23 40°C to 125°C
LTC3564EDCB#PBF LTC3564EDCB#TRPBF LDTQ 6-Lead (2mm × 3mm) Plastic DFN 40°C to 125°C
LTC3564IDCB#PBF LTC3564IDCB#TRPBF LDTQ 6-Lead (2mm × 3mm) Plastic DFN 40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ORDER I FOR ATIO
UUW
L7 LIES/Q
3
LTC3564
3564f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
S
Input DC Bias Current (Note 5)
Active Mode V
FB
= 0.5V or V
OUT
= 90%, I
LOAD
= 0A 300 400 μA
Sleep Mode V
FB
= 0.62V or V
OUT
= 103%, I
LOAD
= 0A 20 35 μA
Shutdown V
RUN
= 0V, V
IN
= 4.2V 0.1 1 μA
f
OSC
Oscillator Frequency V
FB
= 0.6V or V
OUT
= 100% 1.8 2.25 2.7 MHz
R
PFET
R
DS(ON)
of P-Channel FET S5 Package 0.15 0.2 Ω
DCB Package 0.15 Ω
R
NFET
R
DS(ON)
of N-Channel FET S5 Package 0.15 0.2 Ω
DCB Package 0.15 Ω
I
LSW
SW Leakage V
RUN
= 0V, V
SW
= 0V or 5V, V
IN
= 5V ±0.01 ±1μA
V
RUN
RUN Threshold 0.3 1 1.5 V
I
RUN
RUN Leakage Current ±0.01 ±1μA
t
SOFTSTART
Soft-Start Time V
FB
from 10% to 90% Full Scale 0.6 0.9 1.2 ms
The denotes specifications which apply over the full operating junction temperature range, otherwise specifications are TA = 25°C.
VIN = 3.6V unless otherwise specified.
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: The LTC3564E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction termperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3564I is guaranteed over the full –40°C to 125°C operating junction
temperature range. High junction temperatures degrade operating
lifetimes. Operating lifetime is derated at junction temperatures greater
than 125°C.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC3564ES5: T
J
= T
A
+ (P
D
)(215°C/W)
LTC3564EDCB: T
J
= T
A
+ (P
D
)(64°C/W)
Note 4: The LTC3564 is tested in a proprietary test mode.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
// \ \ A/ /\/ L7LJUEAR
4
LTC3564
3564f
Efficiency vs Input Voltage Efficiency vs Output Current Efficiency vs Output Current
Reference Voltage vs
Temperature
Oscillator Frequency vs
Temperature
TA = 25°C, VIN = 3.6V, unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Frequency Variation vs VIN
Load Regulation Line Regulation RDS(ON) vs Input Voltage
INPUT VOLTAGE (V)
2.5
40
EFFICIENCY (%)
50
60
70
80
100
3.0 3.5 4.0 4.5
3564 G01
5.0 5.5
90
I
OUT
= 100mA
V
OUT
= 1.8V
I
OUT
= 1.25A
I
OUT
= 10mA I
OUT
= 1mA
I
OUT
= 0.1mA
OUTPUT CURRENT (mA)
0.1
40
EFFICIENCY (%)
50
60
70
80
1 10 100 1000 10000
3564 G02
30
20
10
0
90
100 V
OUT
= 1.2V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
OUTPUT CURRENT (mA)
0.1
40
EFFICIENCY (%)
50
60
70
80
1 10 100 1000 10000
3564 G04
30
20
10
0
90
100 V
OUT
= 1.5V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
TEMPERATURE (°C)
–50
REFERENCE VOLTAGE (mV)
605
610
615
25 75
3564 G04
600
595
–25 0 50 100 125
590
585
TEMPERATURE (°C)
–50
OSCILLATOR FREQUENCY (MHz)
2.35
25
3564 G05
2.20
2.10
–25 0 50
2.05
2.00
2.40
2.30
2.25
2.15
75 100 125
V
IN
(V)
2.5
6
4
2
0
–2
–4
–6
8
4.0 5.0
3564 G06
3.0 3.5 4.5 5.5
FREQUENCY VARIATION (%)
OUTPUT CURRENT (mA)
0
V
OUT
ERROR (%)
0.50
0.75
1.00
600 1000
3564 G07
0.25
0
200 400 800 1200 1400
–0.25
–0.50
V
OUT
= 1.8V
INPUT VOLTAGE (V)
2.5
–0.6
V
OUT
ERROR (%)
–0.4
–0.2
0
0.2
0.6
3.0 3.5 4.0 4.5
3564 G08
5.0 5.5
0.4
V
OUT
= 1.8V
I
LOAD
= 400mA
INPUT VOLTAGE (V)
2.5
0
R
DS(ON)
(Ω)
0.05
0.10
0.15
0.20
0.25
3.0 3.5 4.0 4.5
3564 G09
5.0 5.5
MAIN SWITCH
SYNCHRONOUS SWITCH
\\ \ L \ L7 LIES/Q
5
LTC3564
3564f
Supply Current vs Supply Voltage Supply Current vs Temperature
Switch Leakage vs Temperature Switch Leakage vs Input Voltage
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
SWITCH LEAKAGE (nA)
400
500
600
25 75
3564 G13
300
200
–25 0 50 100 125
100
0
SYNCHRONOUS SWITCH
MAIN SWITCH
TEMPERATURE (°C)
–50
SUPPLY CURRENT (μA)
30
35
40
25 75
3564 G12
25
20
–25 0 50 100 125
15
10
V
IN
= 3.6V
RUN = V
IN
I
LOAD
= 0A
INPUT VOLTAGE (V)
0
0
SWITCH LEAKAGE (pA)
500
1000
1500
2000
2500
1234
3564 G14
56
RUN = 0V
SYNCHRONOUS
SWITCH
MAIN
SWITCH
TA = 25°C, VIN = 3.6V, unless otherwise specified.
RDS(ON) vs Temperature
TEMPERATURE (°C)
–50
R
DS(ON)
(Ω)
0.20
0.25
0.30
25 75
3564 G10
0.15
0.10
–25 0 50 100 125
0.05
0
MAIN SWITCH
SYNCHRONOUS SWITCH
SUPPLY VOLTAGE (V)
2.5
10
SUPPLY CURRENT (μA)
15
20
25
30
35
3.0 3.5 4.0 4.5
3564 G11
5.0 5.5
77777 WWW» J" “ \Wfi/‘A‘ / / MM hwmmv w... -/"""‘ i’an—fi— M NW V ‘,F'_— , ___-L flm‘ Mun—q L_n_-_n L.— f“ 7‘“ L. _ L7LJUEAR
6
LTC3564
3564f
Load Step Load Step
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ILOAD
1A/DIV
IL
1A/DIV
VOUT
100mV/DIV
AC COUPLED
20μs/DIVVIN = 3.6V
VOUT = 1.8V
ILOAD = 50mA TO 1.25A
3564 G19
IL
1A/DIV
ILOAD
1A/DIV
VOUT
100mV/DIV
AC COUPLED
20μs/DIVVIN = 3.6V
VOUT = 1.8V
ILOAD = 0.25A TO 1.25A
3564 G20
Start-Up from Shutdown Start-Up from Shutdown
Load Step
RUN
2V/DIV
IL
500mA/DIV
VOUT
1V/DIV
400μs/DIVVIN = 3.6V
VOUT = 1.8V
ILOAD = 0mA
3564 G16
V
OUT
1V/DIV
I
L
1A/DIV
RUN
2V/DIV
400μs/DIVV
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 1.25A
3564 G17
ILOAD
1A/DIV
IL
1A/DIV
VOUT
100mV/DIV
AC COUPLED
20μs/DIVVIN = 3.6V
VOUT = 1.8V
ILOAD = 0A TO 1.25A
3564 G18
Burst Mode Operation
SW
2V/DIV
IL
200mA/DIV
VOUT
50mV/DIV
AC COUPLED
2.5μs/DIVVIN = 3.6V
VOUT = 1.8V
ILOAD = 40mA
3564 G15
TA = 25°C, VIN = 3.6V, unless otherwise specified.
-IH|I ITT L7 LIES/Q
7
LTC3564
3564f
V
FB
(Pin 1/Pin 4) : Feedback Pin. Receives the feedback
voltage from an external resistive divider across the out-
put.
GND (Pin 2/NA): Ground Pin.
V
IN
(Pin 3/Pin 3): Main Supply Pin. Must be closely
decoupled to GND, Pin 2, with a 10μF or greater ceramic
capacitor.
SW (Pin 4/Pin 1): Switch Node Connection to Inductor.
This pin connects to the drains of the internal main and
synchronous power MOSFET switches.
RUN (Pin 5/Pin 6): Run Control Input. Forcing this pin
above 1.5V enables the part. Forcing this pin below 0.3V
shuts down the device. In shutdown, all functions are
disabled drawing <1μA supply current. Do not leave RUN
floating.
PGND (NA/Pin 2): Main Power Ground Pin. Connect to the
(–) terminal of C
OUT
, and (–) terminal of C
IN
.
SGND (NA/Pins 5, 7): The Signal Ground Pin. All small
signal components and compensation components should
be connected to this ground (see Board Layout Consider-
ations.)
PI FU CTIO S
UUU
(S5/DCB)
FU CTIO AL DIAGRA
UU
W
+
+
+
EA
+
I
RCMP
+
I
COMP
RUN
OSC
SLOPE
COMP
OSC
FREQ
SHIFT
0.6V
0.6V REF
SHUTDOWN
0.52V
0.65V
SLEEP
V
IN
V
FB
BURST
V
IN
S
R
RS LATCH SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
ANTI-
SHOOT-
THRU
Q
Q
R
SENSE
SW
GND
3564 FD
L7LJUEAR
8
LTC3564
3564f
(Refer to Functional Diagram)
Main Control Loop
The LTC3564 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET) and synchronous (N-channel MOSFET) switches
are internal. During normal operation, the internal top
power MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the current com-
parator, I
COMP
, resets the RS latch. The peak inductor
current at which I
COMP
resets the RS latch, is controlled by
the output of error amplifier EA. When the load current
increases, it causes a slight decrease in the feedback
voltage, FB, relative to the 0.6V reference, which in turn,
causes the EA amplifier’s output voltage to increase until
the average inductor current matches the new load cur-
rent. While the top MOSFET is off, the bottom MOSFET is
turned on until either the inductor current starts to reverse,
as indicated by the current reversal comparator I
RCMP
, or
the beginning of the next clock cycle.
Burst Mode Operation
The LTC3564 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand.
In Burst Mode operation, the peak current of the inductor
is set to approximately 180mA regardless of the output
load. Each burst event can last from a few cycles at light
loads to almost continuously cycling with short sleep
intervals at moderate loads. In between these burst events,
the power MOSFETs and any unneeded circuitry are turned
off, reducing the quiescent current to 20μA. In this sleep
state, the load current is being supplied solely from the
output capacitor. As the output voltage droops, the EA
amplifier’s output rises above the sleep threshold signal-
ing the BURST comparator to trip and turn the top MOSFET
on. This process repeats at a rate that is dependent on the
load demand.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
may exceed the maximum inductor peak current if not
allowed enough time to decay. To prevent the inductor
current from running away, the bottom N-channel MOSFET
is allowed to stay on for more than one cycle, thereby
allowing the inductor current time to decay.
Dropout Operation
As the input supply voltage decreases to a value approach-
ing the output voltage, the duty cycle increases toward the
maximum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one cycle
until it reaches 100% duty cycle. The output voltage will then
be determined by the input voltage minus the voltage drop
across the P-channel MOSFET and the inductor.
An important detail to remember is that at low input supply
voltages, the R
DS(ON)
of the P-channel switch increases
(see Typical Performance Characteristics). Therefore, the
user should calculate the power dissipation when the
LTC3564 is used at 100% duty cycle with low input voltage
(See Thermal Considerations in the Applications Informa-
tion section).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles >40%. However, the LTC3564 uses a
patented scheme that counteracts this compensating ramp,
which allows the maximum inductor peak current to
remain unaffected throughout all duty cycles.
OPERATIO
U
L7 LIES/Q
9
LTC3564
3564f
The basic LTC3564 application circuit is shown in Figure 1.
External component selection is driven by the load require-
ment and begins with the selection of L followed by C
IN
and
C
OUT
.
Inductor Selection
For most applications, the value of the inductor will fall in
the range of 0.47μH to 2.2μH. Its value is chosen based on
the desired ripple current. Large value inductors lower
ripple current and small value inductors result in higher
ripple currents. Higher V
IN
or V
OUT
also increases the ripple
current as shown in equation 1. A reasonable starting point
for setting ripple current is ΔI
L
= 500mA (40% of 1.25A).
Δ=
()( )
IfL
VV
V
L OUT OUT
IN
11
(1)
The DC current rating of the inductor should be at least
equal to the maximum load current plus half the ripple
current to prevent core saturation. Thus, a 1.5A rated
inductor should be enough for most applications (1.25A
+ 250mA). For better efficiency, choose a low DC-resis-
tance inductor.
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
300mA. Lower inductor values (higher ΔI
L
) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar electrical characteristics. The choice of which style
inductor to use often depends more on the price vs size
requirements and any radiated field/EMI requirements
than on what the LTC3564 requires to operate. Table 1
shows some typical surface mount inductors that work
well in LTC3564 applications.
APPLICATIO S I FOR ATIO
WUUU
Table 1. Representative Surface Mount Inductors
MANUFATURER PART NUMBER VALUE (μH) MAX DC CURRENT (A) DCR (mΩ) HEIGHT (mm)
Toko A915AY-1R1M-DC53LC 1.1 3.25 16 3
1070AS-1R0N-DB3020C 1 1.9 47 2
Sumida CDRH4D18C/LD-1R1 1.1 2.1 24 2
CDRH3D14-1R2 1.2 2.2 36 1.5
CR5D11-1R0 1 2.2 40 1.2
CDRH2D18/HP-2R2 2.2 1.6 48 2
FDK MIPW3226D0R9M 0.9 1.4 70 1
Coilcraft LPO6610-122ML 1.2 2.1 80 1
LPS4018-222ML 2.2 2.5 70 1.8
Vishay IHLP1616ABERR47M01 0.47 5 20 1.2
IHLP1616ABER1R0M01 1 4 45 1.2
V
IN
LTC3564
RUN
R1
3564 F01
R2
C
F
L
C
IN
C
OUT
SW
V
IN
V
OUT
V
FB
GND
Figure 1. LTC3564 General Schematic
L7LJUEAR
10
LTC3564
3564f
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
CI
VVV
V
IN OMAX
OUT IN OUT
IN
required IRMS
()
[]
12/
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Always consult the manufac-
turer if there is any question.
The selection of C
OUT
is driven by the required effective
series resistance (ESR).
Typically, once the ESR requirement for C
OUT
has been
met, the RMS current rating generally far exceeds the
I
RIPPLE(P-P)
requirement. The output ripple ΔV
OUT
is deter-
mined by:
Δ≅Δ +
V I ESR fC
OUT L OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and ΔI
L
= ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since ΔI
L
increases with input voltage.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount configurations. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalum capacitors.
These are specially constructed and tested for low ESR so
they give the lowest ESR for a given volume. Other
capacitor types include Sanyo POSCAP, Kemet T510 and
T495 series, and Sprague 593D and 595D series. Consult
the manufacturer for other specific recommendations.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. Because the
LTC3564’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
However, care must be taken when ceramic capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V
IN
. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at V
IN
, large enough
to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
APPLICATIO S I FOR ATIO
WUUU
L7 LIES/Q
11
LTC3564
3564f
Output Voltage Programming
In the adjustable version, the output voltage is set by a
resistive divider according to the following formula:
VV
R
R
OUT
=+
06 1 2
1
.
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 2.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger than
the DC bias current. In continuous mode, I
GATECHG
=
f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3564 circuits: V
IN
quiescent current and I
2
R
losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 3.
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Power Lost vs Load Current
Figure 2. Setting the LTC3564 Output Voltage
LOAD CURRENT (A)
0.1
0.0001
POWER LOSS (W)
0.01
1
1 10 100 1000 10000
3564 F03
0.001
0.1
V
OUT
= 1.2V
V
OUT
= 1.5V
V
OUT
= 1.8V
V
IN
= 3.6V
VFB
GND
LTC3564
0.6V VOUT 5.5V
R2
R1
3564 F02
L7LJUEAR
12
LTC3564
3564f
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses which generally account
for less than 2% total additional loss.
Thermal Considerations
In most applications the LTC3564 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3564 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3564 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3564 in dropout at an
input voltage of 2.7V, a load current of 1.2A and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately ~0.2Ω. There-
fore, power dissipated by the part is:
P
D
= I
LOAD2
• R
DS(ON)
= 288mW
For the SOT-23 package, the θ
JA
is 215°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.288)(215) = 131.9°C
which is above the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (ΔI
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady-
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C
LOAD
).
Thus, a 10μF capacitor charging to 3.3V would require a
250μs rise time, limiting the charging current to about
130mA.
APPLICATIO S I FOR ATIO
WUUU
é L7 LIES/Q
13
LTC3564
3564f
Figure 4a. LTC3564 TSOT-23 Layout Diagram
APPLICATIO S I FOR ATIO
WUUU
Figure 4b. LTC3564 DFN Layout Diagram
VFB
LTC3564
GND
VIN
L1
R2
R1
CFWD
BOLD LINES INDICATE HIGH CURRENT PATH
VOUT
VIN
3564 F04a
4
5
1
3
+
2
RUN
SW
COUT
CIN
SW
LTC3564
PGND
V
IN
R1
C
FWD
BOLD LINES INDICATE HIGH CURRENT PATH
V
IN
V
OUT
3564 F04b
4
6
5
1
3
+
2
RUN
SGND
V
FB
C
OUT
C
IN
R2
L1
\\,EE: J :| E ] E ] L7LJUEAR
14
LTC3564
3564f
APPLICATIO S I FOR ATIO
WUUU
Figure 5a. LTC3564 TSOT-23 Suggested Layout
Figure 5b. LTC3564 DFN Suggested Layout
LTC3564
GND
3564 F05a
PIN 1
V
OUT
V
IN
VIA TO V
OUT
SW
VIA TO V
IN
VIA TO GND
C
OUT
C
IN
L1
R2
C
FWD
R1
3564 F05b
VOUT
PGND
VIN
VFB
VIA TO VOUT
SW VIA TO VIN
CIN
COUT L1
R2 CFWD
R1
4
5
7
6
3
2
1SGND
3E ; .||— L7 LIES/Q
15
LTC3564
3564f
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3564. These items are also illustrated graphically in
Figures 4 and 5. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V
IN
trace should be kept short, direct and
wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C
OUT
and ground.
3. Does the (+) plate of C
IN
connect to V
IN
as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V
FB
node.
5. Keep the (–) plates of C
IN
and C
OUT
as close as possible.
Design Example
As a design example, assume the LTC3564 is used in a
single lithium-ion battery-powered cellular phone
application. The V
IN
will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 1.25A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
Figure 6a. Typical Application Figure 6b. Efficiency vs Output Current
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
LfI
VV
V
LOUT OUT
IN
=
()
Δ
()
11
(3)
Substituting V
OUT
= 2.5V, V
IN
= 4.2V, ΔI
L
= 500mA and
f = 2.25MHz in equation (3) gives:
L= 2.5V
2.25MHz(500mA) 125
42 09
=
.
..
V
VμHH
A 1μH or 1.1μH inductor works well for this application.
For best efficiency choose a 1.5A or greater inductor with
less than 0.1Ω series resistance.
C
IN
will require an RMS current rating of at least 0.6A
I
LOAD(MAX)
/2 at temperature and C
OUT
will require an ESR
of less than 0.125Ω. In most cases, a ceramic capacitor
will satisfy this requirement.
For the feedback resistors, choose R1 = 316k. R2 can
then be calculated from equation (2) to be:
RVRk
OUT
206 1 1 1000=
=
.
Figure 6 shows the complete circuit along with its effi-
ciency curve.
APPLICATIO S I FOR ATIO
WUUU
V
IN
C
IN
**
22μF
CER
V
IN
2.7V
TO 4.2V
LTC3564
RUN
41.1μH*
22pF
1M
316k
3564 F06a
1
3
5
2
SW
V
FB
GND
C
OUT
**
22μF
CER
V
OUT
2.5V
*TOKO A915AY-1R1M (D53LC SERIES)
** TAIYO YUDEN JMK316BJ226ML
OUTPUT CURRENT (mA)
70
EFFICIENCY (%)
80
85
95
100
0.1 10 100 1000
3564 F06b
60
1
90
75
65
V
OUT
= 2.5V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
.n— L7LJUEAR
16
LTC3564
3564f
VIN
CIN**
10μF
CER
VIN
2.7V
TO 5.5V
LTC3564
RUN
31μH*
22pF
806k
402k
3564 TA02a
5
4
1
2
SW
VFB
GND
COUT
22μF
CER
VOUT
1.8V
*MURATA LQH32CN2R2M33
** TAIYO YUDEN JMK316BJ106ML
TAIYO YUDEN JMK316BJ226ML-BR
Single Li-Ion 1.8V/1.25A Regulator for High Efficiency and Small Footprint
OUTPUT CURRENT (mA)
0.1
40
EFFICIENCY (%)
50
60
70
80
1001 10 1000 10000
3564 TA02b
30
20
10
0
90
100
V
OUT
= 1.8V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
I
L
1A/DIV
I
LOAD
1A/DIV
V
OUT
100mV/DIV
AC COUPLED
20μs/DIVV
IN
= 3.6V
V
OUT
= 1.8V
I
LOAD
= 100mA TO 1.25A
3564 TA02c
TYPICAL APPLICATIO S
U
L7 LIES/Q .||—
17
LTC3564
3564f
Single Li-Ion 1.5V/1.25A Regulator for High Efficiency and Low Profile, <1mm Height
VIN
CIN**
10μF
CER
VIN
2.7V
TO 5.5V
LTC3564
RUN
30.9μH*
22pF
604k
402k *FDK MIPW3226D0R9M
**TAIYO YUDEN JMK107BJ106M
A
3564 TA03a
5
4
1
2
SW
VFB
GND
COUT**
10μF×2
CER
VOUT
1.5V
OUTPUT CURRENT (mA)
0.1
40
EFFICIENCY (%)
50
60
70
80
1001 10 1000 10000
3564 TA03b
30
20
10
0
90
100
V
OUT
= 1.5V
V
IN
= 2.7V
V
IN
= 3.6V
V
IN
= 4.2V
I
L
1A/DIV
I
LOAD
1A/DIV
V
OUT
100mV/DIV
AC COUPLED
20μs/DIVV
IN
= 3.6V
V
OUT
= 1.5V
I
LOAD
= 0.3A TO 1.25A
3564 TA04c
TYPICAL APPLICATIO S
U
L7LJUEAR
18
LTC3564
3564f
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
PACKAGE DESCRIPTIO
U
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S5 TSOT-23 0302 REV B
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
L7 LIES/Q
19
LTC3564
3564f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 ±0.10
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB6) DFN 0405
0.25 ± 0.05
0.50 BSC
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
0.25 ± 0.05
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)
2.15 ±0.05
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.50 BSC
L7LJUEAR
20
LTC3564
3564f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
LT 0608 • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2008
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: 2.5V to 5.5V, V
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= 0.8V, I
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= 60μA,
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= <1μA, TSSOP-16E Package
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: 2V to 5V, I
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= 16μA,
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OUT
), 2MHz, Synchronous Buck-Boost 95% Efficiency, V
IN
: 2.4V to 5.5V, V
OUT(MIN)
: 2.4V to 5.25V,
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Q
= 35μA, I
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= <1μA, MS10, DFN Packages
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), 2.25MHz, Synchronous 95% Efficiency, V
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), 2.25MHz, Synchronous Step-Down 95% Efficiency, V
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: 2.5V to 5.5V, V
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= 0.6V, I
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= 16μA,
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= <1μA, ThinSOT Package
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OUT
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= <1μA, DFN Package

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