IAM-20680 Datasheet by TDK InvenSense

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@TDK InvenSense |:| |:| |:| |:| |:| |:| High Performance A [AM-20680 PART AXES TEMP RANGE PACKAGE MSL' \AMVZDBSU sz V4U”C to +85“C 167Pm LGA I U vumo 5mm
IAM-20680
High Performance Automotive 6-Axis MotionTracking Device
InvenSense reserves the right to change the detail
specifications as may be required to permit
improvements in the design of its products.
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 9887339
www.invensense.com
Document Number: DS-000196
Revision: 1.1
Rev. Date: 01/30/2018
GENERAL DESCRIPTION
The IAM-20680 is a 6-axis MotionTracking device for
Automotive applications that combines a 3-axis
gyroscope and a 3-axis accelerometer in a small
3x3x0.75mm (16-pin LGA) package. It also features a 512-
byte FIFO that can lower the traffic on the serial bus
interface and reduce power consumption by allowing the
system processor to burst read sensor data and then go
into a low-power mode. IAM-20680, with its 6-axis
integration, enables manufacturers to eliminate the
costly and complex selection, qualification, and system
level integration of discrete devices, guaranteeing
optimal motion performance.
The gyroscope has a programmable full-scale range of
±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The
accelerometer has a user-programmable accelerometer
full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-
calibrated initial sensitivity of both sensors reduces
production-line calibration requirements.
Other industry-leading features include on-chip 16-bit
ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The
device features I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate digital
IO supply, VDDIO from 1.71V to 3.6V.
BLOCK DIAGRAM
IAM-20680
Charge
Pump
NCS
SDO
SCLK
SDI
Temp Sensor ADC
ADC
Z Gyro
ADCY Gyro
FSYNC
Slave I2C and
SPI Serial
Interface
Interrupt
Status
Register
VDD
Bias & LDOs
GND REGOUT
Z Accel
Y Accel
X Accel ADC
ADC
ADC
ADC
X Gyro
Signal Conditioning
FIFO
User & Config
Registers
Sensor
Registers
Self
test
Self
test
Self
test
Self
test
Self
test
Self
test
INT
APPLICATIONS
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detections
Accurate Location for Vehicle to Vehicle and
Infrastructure
360º View Camera Stabilization
Car Alarm
Telematics
Insurance Vehicle Tracking
ORDERING INFORMATION
PART
AXES
TEMP RANGE
MSL*
IAM-20680
X,Y,Z
-40°C to +85°C
3
†Denotes RoHS and Green-compliant package
* Moisture sensitivity level of the package
FEATURES
Digital-output X-, Y-, and Z-axis angular rate
sensors (gyroscopes) with a user-programmable
full-scale range of ±250 dps, ±500 dps,
±1000 dps, and ±2000 dps and integrated 16-bit
ADCs
Digital-output X-, Y-, and Z-axis accelerometer
with a programmable full scale range of ±2g,
±4g, ±8g, and ±16g and integrated 16-bit ADCs
User-programmable digital filters for gyroscope,
accelerometer, and temperature sensor
Self-test
Wake-on-motion interrupt for low power
operation of applications processor
Reliability testing performed according to
AEC–Q100
o PPAP and qualification data available
upon request
TYPICAL OPERATING CIRCUIT
6 7 8
9
1
4
16 15 14
IAM-20680
2
3
12
11
10
13
5
VDDIO
SA0/SDO
SCL/SPC
CS
SDA/SDI
C3, 10 nF SCL
VDDIO
SDA
AD0
1.8 – 3.3 VDC
VDD
1.8 – 3.3VDC
C2, 0.1 µFREGOUT
GND
RESV
RESV
C1, 0.47 µF
RESV
RESV
INT
FSYNC
RESV
RESV
C4, 2.2 µF
@TDK InvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 2 of 52
Revision: 1.1
TABLE OF CONTENTS
General Description ............................................................................................................................................. 1
Block Diagram ...................................................................................................................................................... 1
Applications ......................................................................................................................................................... 1
Ordering Information ........................................................................................................................................... 1
Features ............................................................................................................................................................... 1
Typical Operating Circuit ...................................................................................................................................... 1
1 Introduction ......................................................................................................................................................... 7
1.1 Purpose and Scope .................................................................................................................................... 7
1.2 Product Overview...................................................................................................................................... 7
1.3 Applications ............................................................................................................................................... 7
2 Features ............................................................................................................................................................... 8
2.1 Gyroscope Features .................................................................................................................................. 8
2.2 Accelerometer Features ............................................................................................................................ 8
2.3 Additional Features ................................................................................................................................... 8
3 Electrical Characteristics ...................................................................................................................................... 9
3.1 Gyroscope Specifications .......................................................................................................................... 9
3.2 Accelerometer Specifications .................................................................................................................. 10
3.3 Electrical Specifications ........................................................................................................................... 11
3.4 I2C Timing Characterization ..................................................................................................................... 14
3.5 SPI Timing Characterization .................................................................................................................... 15
3.6 Absolute Maximum Ratings .................................................................................................................... 16
3.7 Thermal Information ............................................................................................................................... 16
4 Applications Information ................................................................................................................................... 17
4.1 Pin Out Diagram and Signal Description ................................................................................................. 17
4.2 Typical Operating Circuit ......................................................................................................................... 18
4.3 Bill of Materials for External Components .............................................................................................. 18
4.4 Block Diagram ......................................................................................................................................... 19
4.5 Overview ................................................................................................................................................. 19
4.6 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 20
4.7 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ......................................... 20
4.8 I2C and SPI Serial Communications Interfaces ........................................................................................ 20
4.9 Self-Test................................................................................................................................................... 21
4.10 Clocking ............................................................................................................................................... 21
4.11 Sensor Data Registers ......................................................................................................................... 21
4.12 FIFO ..................................................................................................................................................... 22
4.13 Interrupts ............................................................................................................................................ 22
4.14 Digital-Output Temperature Sensor ................................................................................................... 22
4.15 Bias and LDOs ..................................................................................................................................... 22
4.16 Charge Pump ...................................................................................................................................... 22
@TDK InvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 3 of 52
Revision: 1.1
4.17 Standard Power Modes ...................................................................................................................... 22
4.18 Sensor Initialization and Basic Configuration ..................................................................................... 22
5 Programmable Interrupts .................................................................................................................................. 24
5.1 Wake-on-Motion Interrupt ..................................................................................................................... 24
6 Digital Interface ................................................................................................................................................. 25
6.1 I2C and SPI Serial Interfaces .................................................................................................................... 25
6.2 I2C Interface ............................................................................................................................................. 25
6.3 IC Communications Protocol ................................................................................................................... 25
6.4 I2C Terms ................................................................................................................................................. 27
6.5 SPI Interface ............................................................................................................................................ 27
7 Serial Interface Considerations .......................................................................................................................... 29
7.1 IAM-20680 Supported Interfaces ............................................................................................................ 29
8 Register Map ...................................................................................................................................................... 30
9 Register Descriptions ......................................................................................................................................... 32
9.1 Registers 0 to 2 Gyroscope Self-Test Registers .................................................................................... 32
9.2 Registers 13 to 15 Accelerometer Self-Test Registers .......................................................................... 32
9.3 Register 19 Gyro Offset Adjustment Register ...................................................................................... 33
9.4 Register 20 Gyro Offset Adjustment Register ...................................................................................... 33
9.5 Register 21 Gyro Offset Adjustment Register ...................................................................................... 33
9.6 Register 22 Gyro Offset Adjustment Register ...................................................................................... 33
9.7 Register 23 Gyro Offset Adjustment Register ...................................................................................... 33
9.8 Register 24 Gyro Offset Adjustment Register ...................................................................................... 34
9.9 Register 25 Sample Rate Divider .......................................................................................................... 34
9.10 Register 26 Configuration ................................................................................................................ 34
9.11 Register 27 Gyroscope Configuration .............................................................................................. 35
9.12 Register 28 Accelerometer Configuration ....................................................................................... 35
9.13 Register 29 Accelerometer Configuration 2..................................................................................... 36
9.14 Register 30 Low Power Mode Configuration ................................................................................... 37
9.15 Register 31 Wake-on Motion Threshold (Accelerometer) ............................................................... 37
9.16 Register 35 FIFO Enable ................................................................................................................... 38
9.17 Register 54 FSYNC Interrupt Status.................................................................................................. 38
9.18 Register 55 INT/DRDY Pin / Bypass Enable Configuration ............................................................... 38
9.19 Register 56 Interrupt Enable ............................................................................................................ 39
9.20 Register 58 Interrupt Status ............................................................................................................. 39
9.21 Registers 59 to 64 Accelerometer Measurements .......................................................................... 39
9.22 Registers 65 and 66 Temperature Measurement ............................................................................ 40
9.23 Registers 67 to 72 Gyroscope Measurements ................................................................................. 40
9.24 Register 104 Signal Path Reset ......................................................................................................... 41
9.25 Register 105 Accelerometer Intelligence Control ............................................................................ 41
9.26 Register 106 User Control ................................................................................................................ 42
@TDK InvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 4 of 52
Revision: 1.1
9.27 Register 107 Power Management 1 ................................................................................................ 42
9.28 Register 108 Power Management 2 ................................................................................................ 43
9.29 Registers 114 and 115 FIFO Count Registers ................................................................................... 43
9.30 Register 116 FIFO Read Write .......................................................................................................... 44
9.31 Register 117 Who Am I .................................................................................................................... 44
9.32 Registers 119, 120, 122, 123, 125, 126 Accelerometer Offset Registers ............................................ 44
10 Assembly ............................................................................................................................................................ 46
10.1 Orientation of Axes ............................................................................................................................. 46
10.2 Package Dimensions ........................................................................................................................... 47
11 Part Number Package Marking .......................................................................................................................... 49
12 Reference ........................................................................................................................................................... 50
13 Revision History ................................................................................................................................................. 51
@TDK InvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 5 of 52
Revision: 1.1
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram ............................................................................................................................................................. 14
Figure 2. SPI Bus Timing Diagram ............................................................................................................................................................. 15
Figure 3. Pin out Diagram for IAM-20680 3.0x3.0x0.75mm LGA ............................................................................................................. 17
Figure 4. IAM-20680 LGA Application Schematic .................................................................................................................................... 18
Figure 5. IAM-20680 Block Diagram ........................................................................................................................................................ 19
Figure 6. IAM-20680 Solution Using I2C Interface .................................................................................................................................... 20
Figure 7. IAM-20680 Solution Using SPI Interface ................................................................................................................................... 21
Figure 8. START and STOP Conditions ...................................................................................................................................................... 25
Figure 9. Acknowledge on the I2C Bus ..................................................................................................................................................... 26
Figure 10. Complete I2C Data Transfer ..................................................................................................................................................... 26
Figure 11. Typical SPI Master/Slave Configuration .................................................................................................................................. 28
Figure 12. I/O Levels and Connections ..................................................................................................................................................... 29
Figure 14. Orientation of Axes of Sensitivity and Polarity of Rotation .................................................................................................... 46
Figure 15. Package Dimensions................................................................................................................................................................ 47
Figure 16. Part Number Package Marking ............................................................................................................................................... 49
@TDK InvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 6 of 52
Revision: 1.1
LIST OF TABLES
Table 1. Gyroscope Specifications ............................................................................................................................................................. 9
Table 2. Accelerometer Specifications ..................................................................................................................................................... 10
Table 3. D.C. Electrical Characteristics ..................................................................................................................................................... 11
Table 4. A.C. Electrical Characteristics ..................................................................................................................................................... 13
Table 5. Other Electrical Specifications .................................................................................................................................................... 13
Table 6. I2C Timing Characteristics ........................................................................................................................................................... 14
Table 7. SPI Timing Characteristics (8 MHz Operation) ........................................................................................................................... 15
Table 8. Absolute Maximum Ratings ....................................................................................................................................................... 16
Table 9. Thermal Information .................................................................................................................................................................. 16
Table 10. Signal Descriptions ................................................................................................................................................................... 17
Table 11. Bill of Materials ........................................................................................................................................................................ 18
Table 12. Standard Power Modes for IAM-20680 ................................................................................................................................... 22
Table 13. Table of Interrupt Sources ........................................................................................................................................................ 24
Table 14. Serial Interface ......................................................................................................................................................................... 25
Table 15. I2C Terms .................................................................................................................................................................................. 27
Table 16. Configuration............................................................................................................................................................................ 35
Table 17. Accelerometer Data Rates and Bandwidths (Low-noise mode) ............................................................................................... 36
Table 18. Accelerometer Filter Bandwidths, Noise, and Current Consumption ...................................................................................... 36
Table 19. Example Configurations of Gyroscope Low Power Mode ........................................................................................................ 37
Table 20. Package Dimensions ................................................................................................................................................................. 48
Table 21. Part Number Package Marking ................................................................................................................................................ 49
@TDK InvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 7 of 52
Revision: 1.1
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing description, specifications, and design related information on the IAM-20680
Automotive MotionTracking device. The device is housed in a small 3x3x0.75 mm 16-pin LGA package.
1.2 PRODUCT OVERVIEW
The IAM-20680 is a 6-axis MotionTracking device for Automotive applications, that combines a 3-axis gyroscope and a 3-axis
accelerometer in a small 3x3x0.75 mm (16-pin LGA) package. It also features a 512-byte FIFO that can lower the traffic on the serial
bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-
power mode. IAM-20680, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection,
qualification, and system level integration of discrete devices, guaranteeing optimal motion performance.
The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The accelerometer has a user-
programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated initial sensitivity of both sensors
reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate
digital IO supply, VDDIO from 1.71V to 3.6V.
Communication with all registers of the device is performed using either I2C at 40 0kHz or SPI at 8 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
3x3x0.75 mm (16-pin LGA), to provide a very small yet high-performance, low-cost package. The device provides high robustness by
supporting 10,000g shock reliability.
1.3 APPLICATIONS
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detections
Accurate Location for Vehicle to Vehicle and Infrastructure
360º View Camera Stabilization
Car Alarm
Telematics
Insurance Vehicle Tracking
@TDK InvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 8 of 52
Revision: 1.1
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the IAM-20680 includes a wide range of features:
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±250 dps,
±500 dps, ±1000 dps, and ±2000 dps and integrated 16-bit ADCs
Digitally-programmable low-pass filter
Low-power gyroscope operation
Factory calibrated sensitivity scale factor
Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in IAM-20680 includes a wide range of features:
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g and ±16g and
integrated 16-bit ADCs
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 ADDITIONAL FEATURES
The IAM-20680 includes the following additional features:
Smallest and thinnest LGA package for portable devices: 3x3x0.75 mm (16-pin LGA)
Minimal cross-axis sensitivity between the accelerometer and gyroscope axes
512-byte FIFO buffer enables the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
10,000g shock tolerant
400 kHz Fast Mode I2C for communicating with all registers
8 MHz SPI serial interface for communicating with all registers
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
@TDK InvenSense [AM-20680 PARAMETER CONDITIONS MIN 1w MAx uNrrs NOTES GVROSCOPE SENSITIVITV FulirScaie Range F5755 :250 dps 3 F5755 :500 dps 3 F5755 :1000 dps 3 F5755 :2000 dps 3 Gyroscope ADC Word Length 15 bits 3 5ens‘it‘iwty scaie Factor FS7SEL:O 131 LSE/tdps} 3 F5755 55 5 LSB/tdps) 3 FS7SEL:2 32 8 LSB/tdps} 3 FS7SEL: 15 4 LSB/tdps) 3 Nonlinearity Best Fit straight iine, 25‘c 10.1 % 1 CFOSSVAxis sensitivity 25“c :5 % 1 ZERO-RATE OUTPUT (1R0) Initiei ZRO Toierance 25“c 70 a dps z ZRO variation OverTemoerature 740"c to +85“C :1 dps 1 GVROSCOPE NOISE PERFORMANCE (FS_SEL=O) 740"c to +85“C 0.005 dps/VHZ 1,4 740"c to +85“C, induding lifetime drift Gyroscope Mechanical Frequencies 25 27 29 KHz 2 Low Pass Filter Response Progremmabie Range 5 250 Hz 3 Gyroscope Start Up Time From 5Ieep mode 35 ms 1 Programmabie, Normi 1Filtereoi mode
IAM-20680
Document Number: DS-000196 Page 9 of 52
Revision: 1.1
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
All Zero-rate output, sensitivity, and noise specifications include board soldering effects.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
Full-Scale Range
FS_SEL=0
±250
dps
3
FS_SEL=1
±500
dps
3
FS_SEL=2
±1000
dps
3
FS_SEL=3
±2000
dps
3
Gyroscope ADC Word Length
16
bits
3
Sensitivity Scale Factor
FS_SEL=0
131
LSB/(dps)
3
FS_SEL=1
65.5
LSB/(dps)
3
FS_SEL=2
32.8
LSB/(dps)
3
FS_SEL=3
16.4
LSB/(dps)
3
Nonlinearity
Best fit straight line; 25°C
±0.1
%
1
Cross-Axis Sensitivity
25°C
±5
%
1
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C
-0.8
dps
2
ZRO Variation Over Temperature
-40°C to +85°C
±1
dps
1
GYROSCOPE NOISE PERFORMANCE (FS_SEL=0)
Rate Noise Spectral Density
-40°C to +85°C
0.005
dps/√Hz
1,4
-40°C to +85°C, including
lifetime drift
0.010 dps/√Hz 1,4
Gyroscope Mechanical Frequencies
25
27
29
KHz
2
Low Pass Filter Response
Programmable Range
5
250
Hz
3
Gyroscope Start Up Time
From Sleep mode
35
ms
1
Output Data Rate
Programmable, Normal
(Filtered) mode
4 8000 Hz 1
Table 1. Gyroscope Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Tested in production.
3. Guaranteed by design.
4. Calculated from Total RMS Noise.
@TDK InvenSense IA M '2 068 0 PARAMETER CONDITIONS MIN TVP MAX \ uNlTs \ NOTES ACCELEROMETER SENSme AFS,SEL:0 :2 g 3 AFS§E :4 g 3 AFS§E :8 g 3 AFS,SEL:3 :15 g 3 ADC Word Length Output in two's complement format 16 bits 3 AFS,5EL:0 16,384 LSB/g 3 AFS,5EL:1 8,192 LSB/g 3 AF575E 4,096 LSB/g 3 AFS,5EL:3 2,048 LSB/g 3 Nonlinearity Best Fit Straight Line for 2g, zs‘c 70.25 +0.25 % 1 CFOSSVAXlS Sensitivity 25“c :5 % 1 IERO-G OUTPUT lnitial Tolerance All axes, 25“c :50 mg 1 zeroes Level Change vs Temperature r40"c to +85“C :50 mg 1 NOISE PERFORMANCE Low noise mode, r40“c to +85‘C 135 W/VHZ 1,4 Low noise mode, r40“c to +ss‘c, including lifetime drift Low Pass Filter Response Programmable Range 5 218 Hz 3 From Sleep mode 20 ms 1 From Cold Start, 1ms Vim ramp 30 ms 1 Low power (dutyrcycled) 0.24 500 Hz Low noise (active) 4 4000 Hz
IAM-20680
Document Number: DS-000196 Page 10 of 52
Revision: 1.1
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
All Zero-g output, sensitivity, and noise specifications include board soldering effects.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
ACCELEROMETER SENSITIVITY
Full-Scale Range
AFS_SEL=0
±2
g
3
AFS_SEL=1
±4
g
3
AFS_SEL=2
±8
g
3
AFS_SEL=3
±16
g
3
ADC Word Length
Output in twos complement format
16
bits
3
Sensitivity Scale Factor
AFS_SEL=0
16,384
LSB/g
3
AFS_SEL=1
8,192
LSB/g
3
AFS_SEL=2
4,096
LSB/g
3
AFS_SEL=3
2,048
LSB/g
3
Nonlinearity
Best Fit Straight Line for 2g, 25°C
-0.25
+0.25
%
1
Cross-Axis Sensitivity
25°C
±5
%
1
ZERO-G OUTPUT
Initial Tolerance
All axes, 25°C
±50
mg
1
Zero-G Level Change vs. Temperature
-40°C to +85°C
±50
mg
1
NOISE PERFORMANCE
Power Spectral Density
Low noise mode, -40°C to +85°C
135
µg/√Hz
1,4
Low noise mode, -40°C to +85°C, including
lifetime drift
190 µg/√Hz 1,4
Low Pass Filter Response
Programmable Range
5
218
Hz
3
Accelerometer Startup Time
From Sleep mode
20
ms
1
From Cold Start, 1ms VDD ramp
30
ms
1
Output Data Rate
Low power (duty-cycled)
0.24
500
Hz
1
Low noise (active)
4
4000
Hz
Table 2. Accelerometer Specifications
Please contact TDK-InvenSense for a datasheet with maximum and minimum performance values over temperature and lifetime.
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Tested in production.
3. Guaranteed by design.
4. Calculated from Total RMS Noise.
@TDK InvenSense [AM-20680 3.3.1 PARAMETER commons MIN TVP MAX UNITS NOTES supm VOLTAGES VDD 1.71 1.8 3 6 V 1 VDDIO 1.71 1.8 3 6 V 1 SUPPlV CURRENTS & BOOT TIME Normal Mode firaxis Gyroscope + Acce‘emmeter 3 mA 1 Sraxis Gyroscope 2.6 mA 1 Sraxis Acce‘erometer, 4 kHz ODR 390 M 1 Acce‘erometer Low rPower Mode Gyroscope LowVPower Mode 100 Hz ODR, 1x averaging 1.6 mA 2 firAx‘ws LowVPower Mode [Gyroscope LowVPower Mode, Acce‘erometer LowVNmse Model FuHrChip Sleep Mode 6 M 1 TEMPERATURE RANGE Specified Temperature Range Performance paramerers are mm applicame beyond Specified Temperature Range
IAM-20680
Document Number: DS-000196 Page 11 of 52
Revision: 1.1
3.3 ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLY VOLTAGES
VDD
1.71
1.8
3.6
V
1
VDDIO
1.71
1.8
3.6
V
1
SUPPLY CURRENTS & BOOT TIME
Normal Mode
6-axis Gyroscope + Accelerometer
3
mA
1
3-axis Gyroscope
2.6
mA
1
3-axis Accelerometer, 4 kHz ODR
390
µA
1
Accelerometer Low -Power Mode
100 Hz ODR, 1x averaging 57 µA 2
Gyroscope Low-Power Mode
100 Hz ODR, 1x averaging
1.6
mA
2
6-Axis Low-Power Mode
(Gyroscope Low-Power Mode;
Accelerometer Low-Noise Mode)
100 Hz ODR, 1x averaging
1.92 mA 2
Full-Chip Sleep Mode
6
µA
1
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40 +85 °C 1
Table 3. D.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Based on simulation.
@TDK InvenSense [AM-20680 3.3.2 PARAMETER CONDITIONS MIN TVP MAx uNITs NOTES SUPPLIES Supply RampTime (T I Monotonic ramp Ramp 0.01 100 ms 1 rate is 10% final value TEMPERATURE SENSOR Operating Range Ambient 4:0 85 “c Room Temperature Offset 25“c 0 “c Sens‘it‘iuity untrimmeo 326.8 LSB/‘C POWER-0N RESET Supply Ramp Time (TWP! Valid powerron RESET 0.01 100 ms 1 From powerrup 11 100 mS 1 From sleep 5 mS 1 SAD : 0 1101000 SAD : 1 1101001 DIGITAL INPUTS (FSVNC. SAn. SPc, SDI. cs) VIN, ngh Level Input Voltage 0.7*VODI0 V Vii, Low Level Input Voltage 0.3*VODI0 V 0, Input Capacitance < 10="" pf="" digital="" output="" (soo,="" int)="" vd",="" i-i‘igh="" level="" output="" voltage="" mama="" mq;="" 0.9*vodi0="" v="" van,="" lowrlevel="" output="" voltage="" mama="" mq;="" 0.1*vodi0="" v="" v="" m,="" int="" lowvlevel="" output="" voltage="" open:1,="" 0="" 3ma="" sink="" 0="" 1="" v="" current="" output="" leakage="" current="" open:1="" 100="" na="" (rm,="" int="" pulse="" width="" latci-linlen:0="" 50="" us="" i="" c="" i/o="" (scl="" sda)="" vii,="" low="" level="" input="" voltage="" 0.5v="" 0.3*vodi0="" v="" v="" h,="" highrlevei="" input="" voltage="" 0.7*vodi0="" vddio="" +="" 0.5="" v="" v="" vm,="" hysteres‘is="" 0.1*vddi0="" v="" vm,="" lowrlevel="" output="" voltage="" 3="" ma="" sink="" current="" 0="" 0="" 4="" v="" i="" ,="" lowrlevel="" output="" current="" v="" :0.4v="" 3="" ma="" vol:d.6v="" 5="" ma="" output="" leakage="" current="" 100="" na="" tor,0utputfalltime="" fromv="" to="" vilmax="">
IAM-20680
Document Number: DS-000196 Page 12 of 52
Revision: 1.1
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLIES
Supply Ramp Time (T
RAMP
)
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
0.01
100
ms
1
TEMPERATURE SENSOR
Operating Range
Ambient
-40
85
°C
1
Room Temperature Offset
25°C
0
°C
1
Sensitivity
Untrimmed
326.8
LSB/°C
1
POWER-ON RESET
Supply Ramp Time (TRAMP)
Valid power-on RESET
0.01
100
ms
1
Start-up time for register read/write
From power-up
11
100
ms
1
From sleep
5
ms
1
I2C ADDRESS
SA0 = 0
SA0 = 1
1101000
1101001
DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)
VIH, High Level Input Voltage
0.7*VDDIO
V
1
VIL, Low Level Input Voltage
0.3*VDDIO
V
CI, Input Capacitance
< 10
pF
DIGITAL OUTPUT (SDO, INT)
VOH, High Level Output Voltage
RLOAD=1 MΩ;
0.9*VDDIO
V
1
VOL1, LOW-Level Output Voltage
RLOAD=1 MΩ;
0.1*VDDIO
V
V
OL.INT
, INT Low-Level Output Voltage
OPEN=1, 0.3mA sink
Current
0.1
V
Output Leakage Current
OPEN=1
100
nA
tINT, INT Pulse Width
LATCH_INT_EN=0
50
µs
I2C I/O (SCL, SDA)
VIL, LOW Level Input Voltage
-0.5V
0.3*VDDIO
V
1
V
IH
, HIGH-Level Input Voltage
0.7*VDDIO
VDDIO + 0.5
V
V
Vhys, Hysteresis
0.1*VDDIO
V
VOL, LOW-Level Output Voltage
3 mA sink current
0
0.4
V
I
OL
, LOW-Level Output Current
V
OL
=0.4V
VOL=0.6V
3
6
mA
mA
Output Leakage Current
100
nA
t
of
, Output Fall Time from V
IHmax
to
VILmax
Cb bus capacitance in pf 20+0.1Cb 300 ns
@TDK InvenSense [AM-20680 INTERNAL CLOCK SOURCE FCHOICE,B:1,Z,3 SMPLRTiDI FCHOICEiB DLPFCFG or 7 SMPLRTiDI : FCHOICEiB DLPFCFG SMPLRTiDI cu
IAM-20680
Document Number: DS-000196 Page 13 of 52
Revision: 1.1
INTERNAL CLOCK SOURCE
Sample Rate
FCHOICE_B=1,2,3
SMPLRT_DIV=0
32 kHz 2
FCHOICE_B=0;
DLPFCFG=0 or 7
SMPLRT_DIV=0
8 kHz 2
FCHOICE_B=0;
DLPFCFG=1,2,3,4,5,6;
SMPLRT_DIV=0
1 kHz 2
Clock Frequency Initial Tolerance
CLK_SEL=0, 6 or gyro
inactive; 25°C
-5 +5 % 1
CLK_SEL=1,2,3,4,5 and gyro
active; 25°C
-1 +1 % 1
Frequency Variation over
Temperature
CLK_SEL=0,6 or gyro
inactive
-10 +10 % 1
CLK_SEL=1,2,3,4,5 and gyro
active
-1 +1 % 1
Table 4. A.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Guaranteed by design.
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SERIAL INTERFACE
SPI Operating Frequency, All
Registers Read/Write
Low Speed Characterization
100
±10%
kHz 1
High Speed Characterization
1
8
MHz
1, 2
SPI Modes
Modes 0
and 3
I2C Operating Frequency
All registers, Fast-mode
400
kHz
1
All registers, Standard-mode
100
kHz
1
Table 5. Other Electrical Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. SPI clock duty cycle between 45% and 55% should be used for 8 MHz operation.
@TDK InvenSense IA M '2 068 0 PARAMETERS CONDITIONS MIN 11? MAX UNITS NOTES IZC TIMING I’C FAST-MODE Tm, SCL Ciock Frequency 400 kHz 1 t ,[Repeatedi START Condition Hoid Time 0.6 us 1 new, SCL Low Period 1.3 us 1 tum, SCL High Period 0.6 us 1 t , Repeated START Condition Setup Time 0.6 us 1 tun W, SDA Data Hold Time 0 us 1 Igu W, SDA Data Setup Time 100 ns 1 t,, SDA and SCL Rise Time Cb bus cap. from 10 to 400 pF 20+0.1ci 300 ns 1 ti, SDA and SCL Fall Time Cb bus cap. from 10 to 400 pF 20+0.1ci 300 ns 1 t m, STOP Condition Setup Time 0.6 us 1 twp, Bus Free Time Between STOP and START 1.3 us 1 Condition ch, Capacitive Load for each Bus Line < 400="" pf="" 1="" m="" w,="" data="" vaiid="" time="" 0="" 9="" us="" 1="" m="" m,="" data="" valid="" acknowiedge="" time="" 0="" 9="" us="">
IAM-20680
Document Number: DS-000196 Page 14 of 52
Revision: 1.1
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
I2C TIMING
I2C FAST-MODE
fSCL, SCL Clock Frequency
400
kHz
1
t
HD.STA
, (Repeated) START Condition Hold Time
0.6
µs
1
tLOW, SCL Low Period
1.3
µs
1
tHIGH, SCL High Period
0.6
µs
1
t
SU.STA
, Repeated START Condition Setup Time
0.6
µs
1
tHD.DAT, SDA Data Hold Time
0
µs
1
tSU.DAT, SDA Data Setup Time
100
ns
1
tr, SDA and SCL Rise Time
Cb bus cap. from 10 to 400 pF
20+0.1Cb
300
ns
1
tf, SDA and SCL Fall Time
Cb bus cap. from 10 to 400 pF
20+0.1Cb
300
ns
1
t
SU.STO
, STOP Condition Setup Time
0.6
µs
1
t
BUF
, Bus Free Time Between STOP and START
Condition
1.3
µs
1
Cb, Capacitive Load for each Bus Line
< 400
pF
1
tVD.DAT, Data Valid Time
0.9
µs
1
tVD.ACK, Data Valid Acknowledge Time
0.9
µs
1
Table 6. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
SDA
SCL
SDA
SCL
70%
30%
t
f
S
70%
30%
t
r
t
SU.DAT
t
r
t
HD.DAT
70%
30%
t
HD.STA
1/f
SCL
1
st
clock cycle
70%
30%
t
LOW
t
HIGH
t
VD.DAT
9
th
clock cycle
continued below at A
A
Sr PS
70%
30%
t
SU.STA
t
HD.STA
t
VD.ACK
t
SU.STO
t
BUF
70%
30%
9
th
clock cycle
t
f
Figure 1. I2C Bus Timing Diagram
@TDK InvenSense [AM-20680 aI *1 L; E/alw \ Jl‘ 1 r—’ <—l>1 ' ‘ X 5X EX X i
IAM-20680
Document Number: DS-000196 Page 15 of 52
Revision: 1.1
3.5 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SPI TIMING
fSPC, SPC Clock Frequency
8 MHz 1
tLOW, SPC Low Period
56
ns 1
tHIGH, SPC High Period
56
ns 1
tSU.CS, CS Setup Time
2
ns 1
tHD.CS, CS Hold Time
63
ns
1
tSU.SDI, SDI Setup Time
3
ns 1
tHD.SDI, SDI Hold Time
7
ns 1
tVD.SDO, SDO Valid Time Cload = 20 pF
40 ns 1
tHD.SDO, SDO Hold Time Cload = 20 pF 6 ns 1
tDIS.SDO, SDO Output Disable Time 20 ns 1
tFall, SCLK Fall Time 6.5 ns 2
tRise, SCLK Rise Time
6.5
ns
2
Table 7. SPI Timing Characteristics (8 MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
t
HIGH
70%
30%
1/f
CLK
t
HD;CS
CS
SCLK
SDI
SDO MSB OUT
MSB IN LSB IN
LSB OUT
t
DIS;SDO
70%
30%
t
SU;CS
t
SU;SDI
t
HD;SDI
70%
30%
t
HD;SDO
70%
30%
t
VD;SDO
t
LOW
tFall tRise
Figure 2. SPI Bus Timing Diagram
@TDK InvenSense IA M '2 0680 PARAMETER RATING SuppIy Voltage, VDD 70.5v to 4V SuppIy Voltage, VDDIO 70.5v to 4V REGOUT 70.5v m 2v Input VoItage LeveI (SAG, FSVNC, SCL, SDA) 70.5v to VDDIO + 0.5v Acce‘eraucn (Any Axe, unpeweredp 10,0009 for 0.2 ms Operating Temperature Range 740% to +85“C Storage Temperature Range Amt m +125"c 2 kV IHBMI; 250v IMM) JEDEC Class H Izp,125“c :100 mA THERMAL METRIC DESCRIPTION VALUE an Junctmnrmrambient thermal resmance 84.58 ”C/w II)” Junclmnrmrtop characterizatmn parameter 7 “CM
IAM-20680
Document Number: DS-000196 Page 16 of 52
Revision: 1.1
3.6 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
PARAMETER
RATING
Supply Voltage, VDD
-0.5V to 4V
Supply Voltage, VDDIO
-0.5V to 4V
REGOUT
-0.5V to 2V
Input Voltage Level (SA0, FSYNC, SCL, SDA)
-0.5V to VDDIO + 0.5V
Acceleration (Any Axis, unpowered)
10,000g for 0.2 ms
Operating Temperature Range
-40°C to +85°C
Storage Temperature Range
-40°C to +125°C
Electrostatic Discharge (ESD) Protection
2 kV (HBM);
250V (MM)
Latch-up
JEDEC Class II (2),125°C
±100 mA
Table 8. Absolute Maximum Ratings
3.7 THERMAL INFORMATION
THERMAL METRIC
DESCRIPTION
VALUE
θJA
Junction-to-ambient thermal resistance
84.58 °C/W
ψJT
Junction-to-top characterization parameter
7 °C/W
Table 9. Thermal Information
@TDK InvenSense IA M '2 0680 PIN NUMBER PIN NAME PIN DESCRIPTION 1 VDDIO Digital |/0 supply voltage. 2 SCL/SPC | c serial clock (scu, SPI serial clock (spcl. 3 SDA/SDl | c serial data (SDA); SPI serial data input ism). 4 SAD/SDO | c slave address LSB [SI-\O); SPI serial data output (500). 5 cs cnip select to : SPI mode; 1 :l c model. 5 WT lnterrupt digital output (totem pole or openrdrain). 7 RESV Reserved Do not connect a FSVNC syncnronization digital input ioptionall. Connect to GND it unused. 9 RESV Reserved Connect to GND 10 RESV Reserved Connect to GND 11 RESV Reserved Connect to GND 12 RESV Reserved Connect to GND 13 GND Connect to GND. 14 REGOUT Regulator filter capacitor connection. .UUU j E j E j E j E j E WWW
IAM-20680
Document Number: DS-000196 Page 17 of 52
Revision: 1.1
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
VDDIO
Digital I/O supply voltage.
2
SCL/SPC
I2C serial clock (SCL); SPI serial clock (SPC).
3
SDA/SDI
I2C serial data (SDA); SPI serial data input (SDI).
4
SA0/SDO
I2C slave address LSB (SA0); SPI serial data output (SDO).
5
CS
Chip select (0 = SPI mode; 1 = I2C mode).
6
INT
Interrupt digital output (totem pole or open-drain).
7
RESV
Reserved. Do not connect.
8
FSYNC
Synchronization digital input (optional). Connect to GND if unused.
9
RESV
Reserved. Connect to GND.
10
RESV
Reserved. Connect to GND.
11
RESV
Reserved. Connect to GND.
12
RESV
Reserved. Connect to GND.
13
GND
Connect to GND.
14
REGOUT
Regulator filter capacitor connection.
15
RESV
Reserved. Connect to GND.
16 VDD Power Supply.
Table 10. Signal Descriptions
Note: Power up with SCL/SPC and CS pins held low is not a supported use case. In case this power up approach is used, software reset is required using the
PWR_MGMT_1 register, prior to initialization.
6 7 8
INT
RESV
FSYNC
9
1
4
CS
SA0/SDO
16 15 14
REGOUT
RESV
VDD
IAM-20680
LGA Package (Top View)
16-pin, 3mm x 3mm x 0.75mm
Typical Footprint and thickness
2
3
VDDIO
12
11
10
RESV
Orientation of Axes of Sensitivity and Polarity of Rotation
IAM-20680
+Z
+X+Y
13
5
SCL/SPC
SDA/SDI RESV
RESV
RESV
GND
Figure 3. Pin out Diagram for IAM-20680 3.0x3.0x0.75mm LGA
@TDK InvenSense IA M '2 068 0 M VDD‘O I SBA/SDI SAO/SDO
IAM-20680
Document Number: DS-000196 Page 18 of 52
Revision: 1.1
4.2 TYPICAL OPERATING CIRCUIT
6 7 8
9
1
4
16 15 14
IAM-20680
2
3
12
11
10
13
5
VDDIO
SA0/SDO
SCL/SPC
CS
SDA/SDI
C3, 10 nF SCL
VDDIO
SDA
AD0
1.8 – 3.3 VDC
VDD
1.8 – 3.3VDC
C2, 0.1 µFREGOUT
GND
RESV
RESV
C1, 0.47 µF
RESV
RESV
INT
FSYNC
RESV
RESV
C4, 2.2 µF
Figure 4. IAM-20680 LGA Application Schematic
Note: I2C lines are open drain and pullup resistors (e.g. 10kΩ) are required.
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT LABEL SPECIFICATION QUANTITY
REGOUT Capacitor C1 X7R, 0.47 µF ±10% 1
VDD Bypass Capacitors C2 X7R, 0.1 µF ±10% 1
C4 X7R, 2.2 µF ±10% 1
VDDIO Bypass Capacitor C3 X7R, 10 nF ±10% 1
Table 11. Bill of Materials
@TDK InvenSense IA M '2 068 0 E E E E E E
IAM-20680
Document Number: DS-000196 Page 19 of 52
Revision: 1.1
4.4 BLOCK DIAGRAM
IAM-20680
Charge
Pump
CS
SA0 / SDO
SCL / SPC
SDA / SDI
Temp Sensor ADC
ADC
Z Gyro
ADCY Gyro
FSYNC
Slave I2C and
SPI Serial
Interface
Interrupt
Status
Register
VDD
Bias & LDOs
GND REGOUT
Z Accel
Y Accel
X Accel ADC
ADC
ADC
ADC
X Gyro
Signal Conditioning
FIFO
User & Config
Registers
Sensor
Registers
Self
test
Self
test
Self
test
Self
test
Self
test
Self
test
INT
Figure 5. IAM-20680 Block Diagram
4.5 OVERVIEW
The IAM-20680 is comprised of the following key blocks and functions:
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Primary I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
@TDK InvenSense IA M '2 068 0 4.8.1
IAM-20680
Document Number: DS-000196 Page 20 of 52
Revision: 1.1
4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IAM-20680 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes.
When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff.
The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage
is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro
sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is
programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters enable a wide
range of cut-off frequencies.
4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IAM-20680’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces
displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The IAM-20680s
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed
on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the
factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs.
The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
4.8 I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The IAM-20680 communicates to a system processor using either a SPI or an I2C serial interface. The IAM-20680 always acts as a
slave when communicating to the system processor. The LSB of the I2C slave address is set by pin 4 (SA0).
IAM-20680 Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the IAM-20680.
IAM-20680
SA0
SCL
SDA
Interrupt
Status
Register
INT
VDD
Bias & LDOs
GND REGOUT
FIFO
User & Config
Registers
Sensor
Register
Factory
Calibration
Slave I
2
C
or SPI
Serial
Interface
System
Processor
SCL
SDA
VDDIO or GND
I
2
C Processor Bus: for reading all
sensor data from MPU
Figure 6. IAM-20680 Solution Using I2C Interface
@TDK InvenSense IA M '2 068 0 4.8,2
IAM-20680
Document Number: DS-000196 Page 21 of 52
Revision: 1.1
IAM-20680 Solution Using SPI Interface
In Figure 7, the system processor is an SPI master to the IAM-20680. Pins 2, 3, 4, and 5 are used to support the SPC, SDI, SDO, and CS
signals for SPI communications.
IAM-20680
SDO
SPC
SDI
Interrupt
Status
Register INT
FIFO
Config
Register
Sensor
Register
Factory
Calibration
CS
Slave I
2
C
or SPI
Serial
Interface
System
Processor
SDI
SPC
SDO
nCS
Processor SPI Bus: for reading all
data from MPU and for configuring
MPU
VDD
Bias & LDOs
GND REGOUT
Figure 7. IAM-20680 Solution Using SPI Interface
4.9 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers (registers 27 and 28).
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-
test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
4.10 CLOCKING
The IAM-20680 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers. An on-chip
PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be used.
4.11 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only
registers, and are accessed via the serial interface. Data from these registers may be read anytime.
@TDK InvenSense [AM-20680 MODE NAME svno ACCEL 1 Sleep Mode all all z Standby Mode Drive On all 3 Accelerometer LowVPcwer Mode cm Dulervcled 4 Accelerometer LowVNo‘lse Mode all 0n 5 Gyroscope LowVPower Mode Dulervcled cm 5 Gyroscope LowVNo‘lse Mode On all 7 GrAx‘ls LowVNc‘lse Mode On 0n 3 GrAx‘ls LowVPcwer Mode Dulervcled 0n 418.1
IAM-20680
Document Number: DS-000196 Page 22 of 52
Revision: 1.1
4.12 FIFO
The IAM-20680 contains a 512-byte FIFO register that is accessible via the Serial Interface. The FIFO configuration register
determines which data are written into the FIFO. Possible choices include gyro data, accelerometer data, temperature readings, and
FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst
reads. The interrupt function may be used to determine when new data are available.
The IAM-20680 allows FIFO read in low-power accelerometer mode.
4.13 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1)
Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data are available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO overflow. The interrupt status can be read from the
Interrupt Status register.
4.14 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the IAM-20680 die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
4.15 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the IAM-20680. Its two
inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT.
For further details on the capacitor, please refer to the Bill of Materials for External Components.
4.16 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
4.17 STANDARD POWER MODES
Table 12 lists the user-accessible power modes for IAM-20680.
MODE
NAME
GYRO
ACCEL
1
Sleep Mode
Off
Off
2
Standby Mode
Drive On
Off
3
Accelerometer Low-Power Mode
Off
Duty-Cycled
4
Accelerometer Low-Noise Mode
Off
On
5
Gyroscope Low-Power Mode
Duty-Cycled
Off
6
Gyroscope Low-Noise Mode
On
Off
7
6-Axis Low-Noise Mode
On
On
8
6-Axis Low-Power Mode
Duty-Cycled
On
Table 12. Standard Power Modes for IAM-20680
Notes:
1. Power consumption for individual modes can be found in section 3.3.1.
4.18 SENSOR INITIALIZATION AND BASIC CONFIGURATION
The basic configuration of the IAM-20680 includes the following steps:
Sensor initialization and clock source selection
Output data rate (i.e. sampling frequency) selection
Full scale range selection
Filter frequency selection
Power mode selection
Sensor Initialization and Clock Source Selection
To initialize the sensor, perform a reset and let the IAM-20680 select the best clock source by setting the register PWR_MGMT1
(address 0x6B) to 0x81 (see section 9.27).
@TDK InvenSense [AM-20680 4.18.2 4.18.3 4.18.4
IAM-20680
Document Number: DS-000196 Page 23 of 52
Revision: 1.1
Output Data Rate Selection
To set the output data rate (ODR) to the desired frequency, select the sample rate divider by setting the register
SMPLRT_DIV(address 0x19) to the desired value (see section 9.9). For instance, to set the output data rate to 100 Hz, write 0x09 into
SMPLRT_DIV.
Full Scale Range Selection
To set the full-scale range (FSR) of the accelerometer, set the register ACCEL_CONFIG (address 0x1C) to the desired value (see
section 9.12). For instance, to set the FSR of the accelerometer to 2g, write 0x00 into ACCEL_CONFIG.
To set the FSR of the gyroscope, set the register GYRO_CONFIG (address 0x1B) to the desired value (see section 9.11). For instance,
to set the FSR of the gyroscope to 250 dps, write 0x00 into GYRO_CONFIG.
Filter Selection
To set the corner frequency of the digital low-pass filter (DLPF) of the accelerometer, set the register ACCEL_CONFIG2 (address
0x1D) to the desired value (see section 9.13). For instance, to set the corner frequency of the DLPF of the accelerometer to 10.2 Hz,
write 0x05 into ACCEL_CONFIG2.
To set the corner frequency of the DLPF of the gyroscope, set the register CONFIG (address 0x1A) to the desired value (see section
9.10). For instance, to set the corner frequency of the DLPF of the gyroscope to 10 Hz, write 0x05 into CONFIG.
@TDK InvenSense [AM-20680 Motion Detection Motion FIFO Overflow FIFO Data Ready Sensnr Registers
IAM-20680
Document Number: DS-000196 Page 24 of 52
Revision: 1.1
5 PROGRAMMABLE INTERRUPTS
The IAM-20680 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status flags indicate the
source of an interrupt. Interrupt sources may be enabled and disabled individually.
INTERRUPT NAME
MODULE
Motion Detection
Motion
FIFO Overflow
FIFO
Data Ready
Sensor Registers
Table 13. Table of Interrupt Sources
5.1 WAKE-ON-MOTION INTERRUPT
The IAM-20680 provides motion detection capability. A qualifying motion sample is one where the high passed sample from any axis
has an absolute value exceeding a user-programmable threshold. The following steps explain how to configure the Wake-on-Motion
Interrupt.
Step 1: Ensure that Accelerometer is running
In PWR_MGMT_1 register (0x6B) set CYCLE = 0, SLEEP = 0, and GYRO_STANDBY = 0
In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0, and STBY_XG = STBY_YG = STBY_ZG = 1
Step 2: Accelerometer Configuration
In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 0 and A_DLPF_CFG[2:0] = 1 (b001)
Step 3: Enable Motion Interrupt
In INT_ENABLE register (0x38) set WOM_INT_EN = 111 to enable motion interrupt
Step 4: Set Motion Threshold
Set the motion threshold in ACCEL_WOM_THR register (0x1F)
Step 5: Enable Accelerometer Hardware Intelligence
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = ACCEL_INTEL_MODE = 1; Ensure that bit 0 is set to 0
Step 6: Set Frequency of Wake-Up
In SMPLRT_DIV register (0x19) set SMPLRT_DIV[7:0] = 3.9 Hz 500 Hz
Step 7: Enable Cycle Mode (Accelerometer Low-Power Mode)
In PWR_MGMT_1 register (0x6B) set CYCLE = 1
@TDK InvenSense [AM-20680 pm NUMBER pm NAME PIN oascmmuu z SCL/ spc \ c seria‘ dock 15cm; sm serm clock 15m. 3 SDA / 5m x c seria‘ data (SDAD, sm serm data mpm 15m).
IAM-20680
Document Number: DS-000196 Page 25 of 52
Revision: 1.1
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the IAM-20680 can be accessed using either I2C at 400 kHz or SPI at 8 MHz. SPI operates in
four-wire mode.
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1 VDDIO Digital I/O supply voltage.
4 SA0 / SDO I2C Slave Address LSB (SA0); SPI serial data output (SDO).
2
SCL / SPC
I2C serial clock (SCL); SPI serial clock (SPC).
3
SDA / SDI
I2C serial data (SDA); SPI serial data input (SDI).
Table 14. Serial Interface
Note: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit. Setting this bit should be
performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in section 3.3.2.
For further information regarding the I2C_IF_DIS bit, please refer to sections 8 and 9 of this document.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The IAM-20680 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the IAM-20680 is b110100X which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level
on pin SA0. This allows two IAM-20680s to be connected to the same I2C bus. When used in this configuration, the address of one of
the devices should be b1101000 (pin SA0 is logic low) and the address of the other should be b1101001 (pin SA0 is logic high).
6.3 IC COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see Figure 8).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
START condition STOP condition
P
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
@TDK InvenSense IA M '2 068 0
IAM-20680
Document Number: DS-000196 Page 26 of 52
Revision: 1.1
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
DATA OUTPUT BY
RECEIVER (SDA)
SCL FROM
MASTER
START
condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
1 2 8 9
Figure 9. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
SDA
START
condition
SCL
ADDRESS R/W ACK DATA ACK DATA ACK STOP
condition
S P
1 – 7 8 9 1 – 7 8 9 1 – 7 8 9
Figure 10. Complete I2C Data Transfer
To write the internal IAM-20680 registers, the master transmits the start condition (S), followed by the I2C address and the write bit
(0). At the 9th clock cycle (when the clock is high), the IAM-20680 acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the IAM-20680 acknowledges the reception of the register address, the master puts the register data
onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the IAM-
20680 automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master S AD+W RA DATA P
Slave ACK ACK ACK
@TDK InvenSense [AM-20680 SIGNAL DESCRIPTION 5 sun Condition: SDA goes from high to iow while su is high AD Sieve PC address w Write b‘it (c) R Read bit up ACK Acknowiedge SDA line is low whiie the SCL hne is high at the s h cidck cycle NACK NobAcknow‘edge: SDA line stays high at the s h cioch cycie RA IAMVZDGBO internal regisier address DATA Transmii or received data P sum condition: SDA gomg from iow to high while SCL is high
IAM-20680
Document Number: DS-000196 Page 27 of 52
Revision: 1.1
Burst Write Sequence
To read the internal IAM-20680 registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the IAM-20680, the master transmits a start signal
followed by the slave address and read bit. As a result, the IAM-20680 sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Burst Read Sequence
6.4 I2C TERMS
SIGNAL
DESCRIPTION
S
Start Condition: SDA goes from high to low while SCL is high
AD
Slave I2C address
W
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the 9
th
clock cycle
NACK
Not-Acknowledge: SDA line stays high at the 9th clock cycle
RA
IAM-20680 internal register address
DATA
Transmit or received data
P
Stop condition: SDA going from low to high while SCL is high
Table 15. I2C Terms
6.5 SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The IAM-20680 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared
among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data are delivered MSB first and LSB last
2. Data are latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 8 MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiple-
byte Read/Writes, data are two or more bytes:
Master
S
AD+W
RA
DATA
DATA
P
Slave
ACK
ACK
ACK
ACK
Master
S
AD+W
RA
S
AD+R
NACK
P
Slave ACK ACK ACK DATA
Master S AD+W RA S AD+R ACK NACK P
Slave ACK ACK ACK DATA DATA
@TDK InvenSense IA M '2 068 0 MSB ISB R/W A6 A5 A4 A3 AZ A1 A0 MSB lSB D7 D6 D5 D4 D3 D2 D1 D0
IAM-20680
Document Number: DS-000196 Page 28 of 52
Revision: 1.1
SPI Address format
MSB
LSB
R/W
A6
A5
A4
A3
A2
A1
A0
SPI Data format
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
6. Supports Single or Burst Read/Writes.
SPI Master SPI Slave 1
SPI Slave 2
CS1
CS2
SPC
SDI
SDO
CS
SPC
SDI
SDO
CS
Figure 11. Typical SPI Master/Slave Configuration
@TDK .nvenSense [AM-20680
IAM-20680
Document Number: DS-000196 Page 29 of 52
Revision: 1.1
7 SERIAL INTERFACE CONSIDERATIONS
7.1 IAM-20680 SUPPORTED INTERFACES
The IAM-20680 supports I2C communications on its serial interface.
The IAM-20680’s I/O logic levels are set to be VDDIO.
Figure 12 depicts a sample circuit of IAM-20680. It shows the relevant logic levels and voltage connections.
IAM-20680
VDD
System
Processor IO
SYSTEM BUS
VDDIO
VDDIO
VDD
VDDIO
SCL
SDA
INT
SYNC
VDDIO
SA0
(0V - VDDIO)
(0V - VDDIO)
(0V - VDDIO)
(0V - VDDIO)
(0V, VDDIO)
VDD_IO
(0V - VDDIO)
Figure 12. I/O Levels and Connections
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IAM-20680
Document Number: DS-000196 Page 30 of 52
Revision: 1.1
8 REGISTER MAP
The following table lists the register map for the IAM-20680.
Addr
(Hex)
Addr
(Dec.) Register Name Serial I/F
Accessible
(writable) in
Sleep Mode
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00
00
SELF_TEST_X_GYRO
R/W
N
XG_ST_DATA[7:0]
01
01
SELF_TEST_Y_GYRO
R/W
N
YG_ST_DATA[7:0]
02
02
SELF_TEST_Z_GYRO
R/W
N
ZG_ST_DATA[7:0]
0D
13
SELF_TEST_X_ACCEL
R/W
N
XA_ST_DATA[7:0]
0E
14
SELF_TEST_Y_ACCEL
R/W
N
YA_ST_DATA[7:0]
0F
15
SELF_TEST_Z_ACCEL
R/W
N
ZA_ST_DATA[7:0]
13
19
XG_OFFS_USRH
R/W
N
X_OFFS_USR [15:8]
14
20
XG_OFFS_USRL
R/W
N
X_OFFS_USR [7:0]
15
21
YG_OFFS_USRH
R/W
N
Y_OFFS_USR [15:8]
16
22
YG_OFFS_USRL
R/W
N
Y_OFFS_USR [7:0]
17
23
ZG_OFFS_USRH
R/W
N
Z_OFFS_USR [15:8]
18
24
ZG_OFFS_USRL
R/W
N
Z_OFFS_USR [7:0]
19
25
SMPLRT_DIV
R/W
N
SMPLRT_DIV[7:0]
1A 26 CONFIG R/W
N
-
FIFO_
MODE
EXT_SYNC_SET[2:0] DLPF_CFG[2:0]
1B
27
GYRO_CONFIG
R/W
N
XG_ST
YG_ST
ZG_ST
FS_SEL [1:0]
-
FCHOICE_B[1:0]
1C
28
ACCEL_CONFIG
R/W
N
XA_ST
YA_ST
ZA_ST
ACCEL_FS_SEL[1:0]
-
1D 29 ACCEL_CONFIG 2 R/W N - DEC2_CFG
ACCEL_FCHOI
CE_B
A_DLPF_CFG
1E 30 LP_MODE_CFG R/W N
GYRO_CYCL
E
G_AVGCFG[2:0] -
1F
31
ACCEL_WOM_THR
R/W
N
WOM_THR[7:0]
23 35 FIFO_EN R/W N
TEMP
_FIFO_EN
XG_FIFO_EN YG_FIFO_EN ZG_FIFO_EN
ACCEL_FIFO_
EN
- - -
36
54
FSYNC_INT
R/C
N
FSYNC_INT
-
-
-
-
-
-
-
37 55 INT_PIN_CFG R/W Y INT_LEVEL INT_OPEN LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_INT_L
EVEL
FSYNC
_INT_MODE_
EN
- -
38 56 INT_ENABLE R/W Y WOM_INT_EN[7:5]
FIFO
_OFLOW
_EN
- GDRIVE_INT_
EN - DATA_RDY_I
NT_EN
3A 58 INT_STATUS R/C N WOM_INT[7:5]
FIFO
_OFLOW
_INT
- GDRIVE_INT - DATA
_RDY_INT
3B
59
ACCEL_XOUT_H
R
N
ACCEL_XOUT_H[15:8]
3C
60
ACCEL_XOUT_L
R
N
ACCEL_XOUT_L[7:0]
3D
61
ACCEL_YOUT_H
R
N
ACCEL_YOUT_H[15:8]
3E
62
ACCEL_YOUT_L
R
N
ACCEL_YOUT_L[7:0]
3F
63
ACCEL_ZOUT_H
R
N
ACCEL_ZOUT_H[15:8]
40
64
ACCEL_ZOUT_L
R
N
ACCEL_ZOUT_L[7:0]
41
65
TEMP_OUT_H
R
N
TEMP_OUT[15:8]
42
66
TEMP_OUT_L
R
N
TEMP_OUT[7:0]
43
67
GYRO_XOUT_H
R
N
GYRO_XOUT[15:8]
44
68
GYRO_XOUT_L
R
N
GYRO_XOUT[7:0]
45
69
GYRO_YOUT_H
R
N
GYRO_YOUT[15:8]
46
70
GYRO_YOUT_L
R
N
GYRO_YOUT[7:0]
47
71
GYRO_ZOUT_H
R
N
GYRO_ZOUT[15:8]
48
72
GYRO_ZOUT_L
R
N
GYRO_ZOUT[7:0]
68 104 SIGNAL_PATH_RESET R/W N - - - - - -
ACCEL
_RST
TEMP
_RST
69 105 ACCEL_INTEL_CTRL R/W N
ACCEL_INTE
L_EN
ACCEL_INTEL
_MODE
-
6A 106 USER_CTRL R/W N - FIFO_EN -
I2C_IF
_DIS
-
FIFO
_RST
-
SIG_COND
_RST
6B 107 PWR_MGMT_1 R/W Y
DEVICE_RES
ET
SLEEP ACCEL_CYCLE
GYRO_
STANDBY
TEMP_DIS CLKSEL[2:0]
@TDK InvenSense [AM-20680 m- um 5:17: W n W NN N NW, N W NN N MW, 71 W NN N MW,
IAM-20680
Document Number: DS-000196 Page 31 of 52
Revision: 1.1
Addr
(Hex)
Addr
(Dec.) Register Name Serial I/F
Accessible
(writable) in
Sleep Mode
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
6C
108
PWR_MGMT_2
R/W
Y
FIFO_LP_EN
-
STBY_XA
STBY_YA
STBY_ZA
STBY_XG
STBY_YG
STBY_ZG
72
114
FIFO_COUNTH
R
N
-
FIFO_COUNT[12:8]
73
115
FIFO_COUNTL
R
N
FIFO_COUNT[7:0]
74
116
FIFO_R_W
R/W
N
FIFO_DATA[7:0]
75
117
WHO_AM_I
R
N
WHOAMI[7:0]
77
119
XA_OFFSET_H
R/W
N
XA_OFFS [14:7]
78
120
XA_OFFSET_L
R/W
N
XA_OFFS [6:0]
-
7A
122
YA_OFFSET_H
R/W
N
YA_OFFS [14:7]
7B
123
YA_OFFSET_L
R/W
N
YA_OFFS [6:0]
-
7D
125
ZA_OFFSET_H
R/W
N
ZA_OFFS [14:7]
7E
126
ZA_OFFSET_L
R/W
N
ZA_OFFS [6:0]
-
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
In the detailed register tables that follow, register names are in capital letters, while register values are in capital letters and
italicized. For example, the ACCEL_XOUT_H register (Register 59) contains the 8 most significant bits, ACCEL_XOUT[15:8], of the 16-
bit X-Axis accelerometer measurement, ACCEL_XOUT.
The reset value is 0x00 for all registers other than the registers below, also the self-test registers contain pre-programmed values
and will not be 0x00 after reset.
Register 107 (0x40) Power Management 1
Register 117 (0xA9) WHO_AM_I
@TDK InvenSense IA M '2 0680 REGISTER BIT NAME FUNCTION The value in this reglster indicates the selHest output generated durlng manufacturing tests This value is to be used to check oga subsequent selHest outputs performed by the end user. The value in this reglster indicates the selHest output generated durlng manufacturing tests This value is to be used to check oga subsequent selHest outputs performed by the end user. The value in this reglster indicates the selHest output generated durlng manufacturing tests This value is to be used to check oga subsequent selHest outputs performed by the end user. REGISTER BITS NAME FUNCTION The value in this register indicates the selfrtest output generated durlng manufacturing tests This value is to be used to che subsequent selfrtest outputs performed by the end user. The value in this register indicates the selfrtest output generated durlng manufacturing tests This value is to be used to che subsequent selfrtest outputs performed by the end user. The value in this register indicates the selfrtest output generated durlng manufacturing tests This value is to be used to che subsequent selfrtest outputs performed by the end user.
IAM-20680
Document Number: DS-000196 Page 32 of 52
Revision: 1.1
9 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the IAM-20680.
Note: The device will come up in sleep mode upon power-up.
9.1 REGISTERS 0 TO 2 GYROSCOPE SELF-TEST REGISTERS
Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO
Type: READ/WRITE
Register Address: 00, 01, 02 (Decimal); 00, 01, 02 (Hex)
REGISTER
BIT
NAME
FUNCTION
SELF_TEST_X_GYRO [7:0] XG_ST_DATA[7:0]
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
SELF_TEST_Y_GYRO [7:0] YG_ST_DATA[7:0]
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
SELF_TEST_Z_GYRO [7:0] ZG_ST_DATA[7:0]
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The equation to convert self-test codes in OTP to factory self-test measurement is:
(lsb) 01.1*)2/2620(_
)1_(
=
codeSTFS
OTPST
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
1)
)01.1log(
))2/2620/(_log(
(_ +=
FS
FACST
roundcodeST
9.2 REGISTERS 13 TO 15 ACCELEROMETER SELF-TEST REGISTERS
Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL
Type: READ/WRITE
Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex)
REGISTER
BITS
NAME
FUNCTION
SELF_TEST_X_ACCEL [7:0] XA_ST_DATA[7:0]
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
SELF_TEST_Y_ACCEL [7:0] YA_ST_DATA[7:0]
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
SELF_TEST_Z_ACCEL [7:0] ZA_ST_DATA[7:0]
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The equation to convert self-test codes in OTP to factory self-test measurement is:
(lsb) 01
.1*
)2/2620
(_ )1_(
=codeST
FS
OTPST
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSenses factory final test and calculated based on the following equation:
1)
)01.1log(
))2/2620/(_log(
(_ +=
FS
FACST
roundcodeST
@TDK InvenSense IA M '2 0680 BIT NAME FUNCTION Bits 15 to a of the 16bit offset of x gyroscope (2’s complement). This register is used to remove DC bias from the sensor output. The value in this register is added to the gyroscope sensorvalue before going into the sensor register. BIT NAME FUNCTION Bits 7 to u ofthe 16bit offset of x gyroscope (2’s complement). This register is used to remove DC bias from the sensor output. The value in this register is added to the gyroscope sensorvalue before going into the sensor register. BIT NAME FUNCTION Bits 15 to a of the 16bit offset of v gyroscope [Z’s complementl. This register is used to remove DC bias from the sensor output. The value in this register is added to the gyroscope sensorvalue before going into the sensor register. BIT NAME FUNCTION Bits 7 to u ofthe 16bit offset of v gyroscope (2’s complementl. This register is used to remove DC bias from the sensor output. The value in this register is added to the gyroscope sensorvalue before going into the sensor register. BIT NAME FUNCTION Bits 15 to a of the 16bit offset of z gyroscope (2’s complement). This register is used to remove DC bias from the sensor output. The value in this register is added to the gyroscope sensorvalue before going into the sensor register.
IAM-20680
Document Number: DS-000196 Page 33 of 52
Revision: 1.1
9.3 REGISTER 19 GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 19 (Decimal); 13 (Hex)
BIT
NAME
FUNCTION
[7:0] X_OFFS_USR[15:8]
Bits 15 to 8 of the 16-bit offset of X gyroscope (2s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.4 REGISTER 20GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 20 (Decimal); 14 (Hex)
BIT
NAME
FUNCTION
[7:0] X_OFFS_USR[7:0]
Bits 7 to 0 of the 16-bit offset of X gyroscope (2s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.5 REGISTER 21 GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 21 (Decimal); 15 (Hex)
BIT
NAME
FUNCTION
[7:0] Y_OFFS_USR[15:8]
Bits 15 to 8 of the 16-bit offset of Y gyroscope (2s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.6 REGISTER 22GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 22 (Decimal); 16 (Hex)
BIT
NAME
FUNCTION
[7:0] Y_OFFS_USR[7:0]
Bits 7 to 0 of the 16-bit offset of Y gyroscope (2s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.7 REGISTER 23 GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 23 (Decimal); 17 (Hex)
BIT
NAME
FUNCTION
[7:0] Z_OFFS_USR[15:8]
Bits 15 to 8 of the 16-bit offset of Z gyroscope (2s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
@TDK InvenSense IA M '2 0680 BIT NAME FUNCTION Bits 7 to u ofthe 167bit offset of z gyroscope (2’s complement). This register is used to remove DC bias from the sensor output. The value in this register is added to the gyroscope sensorvalue before going into the sensor register. BIT NAME FUNCTION [7:0] swmnmvlml Divides the internal sample rate isee register CONFIGI to generate the sample rate that controls sensor data outpuI fate, FIFO sam Note: This register is only effective when FCHOl This is the update rate ofthe sensor regist SAMPLEiRATE : lNTERNALfiSAMPLEiRAT Where lNTERNALfiSAMPLEiRATE : 1 kHz BIT NAME FUNCTION [7] , Always set to o. [5] FlFoiMODE when set to '1', when the FIFO is full, additional writes will not be written to FIFO. when set to ’D’, the oldest data [5:3] EXT7$VNC7$ET[Z:D] Enables the FSVNC pin data to be sampled. EXT_SVNC_SET rsvuc bit location function disabled TEMP,OUT7L[U] GVRoixouTiLw] GVROivouTiLlu] GVROJOULHU] ACCELXOUTiLlO] ACCEL7VOUT7L[U] ACCELZOULHD] Nmmwab—to FSVNC will be latched to the latched value toggle the sample rate strobe. [2:0] DLPF7CFG[Z:U] forthe DLPF to he used, fChOchaum is root). see Table 1a
IAM-20680
Document Number: DS-000196 Page 34 of 52
Revision: 1.1
9.8 REGISTER 24GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 24 (Decimal); 18 (Hex)
BIT
NAME
FUNCTION
[7:0] Z_OFFS_USR[7:0]
Bits 7 to 0 of the 16-bit offset of Z gyroscope (2s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.9 REGISTER 25 SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
NAME
FUNCTION
[7:0]
SMPLRT_DIV[7:0]
Divides the internal sample rate (see register CONFIG) to generate the sample rate that
controls sensor data output rate, FIFO sample rate.
Note: This register is only effective when FCHOICE_B register bits are 2’b00, and (0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1 kHz
9.10 REGISTER 26 CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
NAME
FUNCTION
[7]
-
Always set to 0.
[6]
FIFO_MODE
When set to1, when the FIFO is full, additional writes will not be written to FIFO.
When set to0, when the FIFO is full, additional writes will be written to the FIFO, replacing
the oldest data.
[5:3]
EXT_SYNC_SET[2:0]
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET
FSYNC bit location
0
function disabled
1
TEMP_OUT_L[0]
2
GYRO_XOUT_L[0]
3
GYRO_YOUT_L[0]
4
GYRO_ZOUT_L[0]
5
ACCEL_XOUT_L[0]
6
ACCEL_YOUT_L[0]
7
ACCEL_ZOUT_L[0]
FSYNC will be latched to capture short strobes. This will be done such that if FSYNC toggles,
the latched value toggles, but won’t toggle again until the new latched value is captured by
the sample rate strobe.
[2:0]
DLPF_CFG[2:0]
For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See Table 16.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The gyroscope and temperature sensor are filtered according
to the value of DLPF_CFG and FCHOICE_B as shown in Table 16.
@TDK InvenSense IA M '2 068 0 Temperature 3~dE EW anse EW Rate arr NAME FUNCTION [7] x5757 x Gyro sexnest [5] my v Gyro selHesL [5] 25,57 2 Gyro sexnest. Gyro Full Sca‘e Select: 00 : 1250 dps 01: 1500 dps 10 11000 dps 11 : 12000 dps [2] , Reserved. [1:0] FCHOICLBU a] Used to bypass DLPF as shown m Tame 15 above arr NAME FUNCTION [7] XA7$T >< acce‘="" sexnest.="" [5]="" my="" v="" accel="" selhesl="" [5]="" 2/057="" zacce\="" sexnesx.="" accel="" full="" scale="" select:="" 12g="" 100i,="" :ag="" (01),="" :83i10d,:16g(11)="">
IAM-20680
Document Number: DS-000196 Page 35 of 52
Revision: 1.1
FCHOICE_B
DLPF_CFG
Gyroscope Temperature
Sensor
<1> <0> 3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz) 3-dB BW (Hz)
X
1
X
8173
8595.1
32
4000
1 0 X 3281
3451.0
32
4000
0 0 0 250 306.6
8
4000
0
0
1
176
177.0
1
188
0
0
2
92
108.6
1
98
0 0 3 41 59.0
1
42
0 0 4 20 30.5
1
20
0
0
5
10
15.6
1
10
0
0
6
5
8.0
1
5
0 0 7 3281 3451.0 8 4000
Table 16. Configuration
9.11 REGISTER 27 GYROSCOPE CONFIGURATION
Register Name: GYRO_CONFIG
Register Type: READ/WRITE
Register Address: 27 (Decimal); 1B (Hex)
BIT
NAME
FUNCTION
[7]
XG_ST
X Gyro self-test.
[6]
YG_ST
Y Gyro self-test.
[5]
ZG_ST
Z Gyro self-test.
[4:3] FS_SEL[1:0]
Gyro Full Scale Select:
00 = ±250 dps
01= ±500 dps
10 = ±1000 dps
11 = ±2000 dps
[2]
-
Reserved.
[1:0]
FCHOICE_B[1:0]
Used to bypass DLPF as shown in Table 16 above.
9.12 REGISTER 28 ACCELEROMETER CONFIGURATION
Register Name: ACCEL_CONFIG
Register Type: READ/WRITE
Register Address: 28 (Decimal); 1C (Hex)
BIT
NAME
FUNCTION
[7]
XA_ST
X Accel self-test.
[6]
YA_ST
Y Accel self-test.
[5]
ZA_ST
Z Accel self-test.
[4:3] ACCEL_FS_SEL[1:0]
Accel Full Scale Select:
±2g (00), ±4g (01), ±8g (10), ±16g (11)
[2:0]
-
Reserved.
@TDK InvenSense [AM-20680 BIT NAME FUNCTION [7:6] . Reserved. Averaging filter settings for Low Power Accelerometer made: 0 = Average 4 samples 1 = Average 3 samples verage 16 samples rAverage 32 samples [3] ACCELJCHOICLB Used to bypass DLPF as shown in Table 17. [2:0] Aimvrgcre Accelerometer low pass filter setting as shown in Table 17. 3-dB BW Noise BW Rate
IAM-20680
Document Number: DS-000196 Page 36 of 52
Revision: 1.1
9.13 REGISTER 29 ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT
NAME
FUNCTION
[7:6]
-
Reserved.
[5:4] DEC2_CFG[1:0]
Averaging filter settings for Low Power Accelerometer mode:
0 = Average 4 samples
1 = Average 8 samples
2 = Average 16 samples
3 = Average 32 samples
[3]
ACCEL_FCHOICE_B
Used to bypass DLPF as shown in Table 17.
[2:0]
A_DLPF_CFG
Accelerometer low pass filter setting as shown in Table 17.
ACCEL_FCHOICE_B A_DLPF_CFG
Accelerometer
3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz)
1 X 1046.0 1100.0 4
0
0
218.1
235.0
1
0
1
218.1
235.0
1
0 2 99.0 121.3
1
0 3 44.8 61.5
1
0
4
21.2
31.0
1
0
5
10.2
15.5
1
0 6 5.1 7.8
1
0 7 420.0 441.6 1
Table 17. Accelerometer Data Rates and Bandwidths (Low-noise mode)
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where SMPLRT_DIV is an 8-bit
integer. Following is a small subset of ODRs that are configurable for the accelerometer in the low-noise mode in this manner (Hz):
3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K.
Table 18 lists the accelerometer filter bandwidths, noise, and current consumption available in the low-power mode of operation. In
the low-power mode of operation, the accelerometer is duty-cycled.
ACCEL_FCHOICE_B 1 0 0 0 0
A_DLPF_CFG x 7 7 7 7
DEC2_CFG
x
0
1
2
3
Averages
1x
4x
8x
16x
32x
Ton (ms) 1.084 1.84 2.84 4.84 8.84
Noise BW (Hz) 1100.0 441.6 235.4 121.3 61.5
Noise (mg) TYP based on 250 µg/Hz
8.3
5.3
3.8
2.8
2.0
SMPLRT_DIV
ODR (Hz)
Current Consumption (µA) TYP
255 3.9 8.4 9.4 10.8 13.6 19.2
127 7.8 9.8 11.9 14.7 20.3 31.4
63
15.6
12.8
17.0
22.5
33.7
55.9
31
31.3
18.7
27.1
38.2
60.4
104.9
15 62.5 30.4 47.2 69.4 113.9 202.8
7 125.0 57.4 87.5 132.0 220.9 N/A
3
250.0
100.9
168.1
257.0
N/A
1
500.0
194.9
329.3
N/A
Table 18. Accelerometer Filter Bandwidths, Noise, and Current Consumption
@TDK InvenSense arr NAME Fuucnou [7] vaogcvcuz When set to '1' lownpawer gyroscope made is enabled. Default setting is '0‘ Averagingfilter configuration for lownpnwergymscope mmie. Default setting is '000' [3:0] , Reserved. BIT NAME FUNCTION [7:0] WOM,THR[7:D] This register holds the threshold value for the Wake an Motion Interrupt for accelerometer.
IAM-20680
Document Number: DS-000196 Page 37 of 52
Revision: 1.1
9.14 REGISTER 30 LOW POWER MODE CONFIGURATION
Register Name: LP_MODE_CFG
Register Type: READ/WRITE
Register Address: 30 (Decimal); 1E (Hex)
BIT
NAME
FUNCTION
[7]
GYRO_CYCLE
When set to1 low-power gyroscope mode is enabled. Default setting is ‘0
[6:4] G_AVGCFG[2:0]
Averaging filter configuration for low-power gyroscope mode. Default
setting is ‘000
[3:0]
-
Reserved.
To operate in gyroscope low-power mode or 6-axis low-power mode, GYRO_CYCLE should be set to ‘1.’ Gyroscope filter
configuration is determined by G_AVGCFG[2:0] that sets the averaging filter configuration. It is not dependent on DLPF_CFG[2:0].
Table 19 shows some example configurations for gyroscope low power mode.
FCHOICE_B 0 0 0 0 0 0 0 0
G_AVGCFG 0 1 2 3 4 5 6 7
Averages
1x
2x
4x
8x
16x
32x
64x
128x
Ton (ms)
1.73
2.23
3.23
5.23
9.23
17.23
33.23
65.23
Noise BW (Hz) 650.8 407.1 224.2 117.4 60.2 30.6 15.6 8.0
Noise (dps) TYP based on
0.008 dps/Hz
0.20 0.16 0.12 0.09 0.06 0.04 0.03 0.02
SMPLRT_DIV ODR (Hz) Current Consumption (mA) TYP
255
3.9
1.3
1.3
1.3
1.3
1.4
1.4
1.5
1.8
99
10.0
1.3
1.3
1.4
1.4
1.5
1.6
1.9
2.5
64 15.4 1.4 1.4 1.4 1.5 1.6 1.8 2.2 N/A
32 30.3 1.4 1.4 1.5 1.6 1.8 2.2 N/A
19
50.0
1.5
1.5
1.6
1.8
2.1
2.8
9
100.0
1.6
1.7
1.9
2.2
3.0
N/A
7 125.0 1.7 1.8 2.0 2.5 N/A
4 200.0 1.9 2.1 2.5 N/A
3
250.0
2.1
2.3
2.7
2
333.3
2.3
2.6
N/A
1 500.0 2.9 N/A
Table 19. Example Configurations of Gyroscope Low Power Mode
9.15 REGISTER 31 WAKE-ON MOTION THRESHOLD (ACCELEROMETER)
Register Name: ACCEL_WOM_THR
Register Type: READ/WRITE
Register Address: 31 (Decimal); 1F (Hex)
BIT
NAME
FUNCTION
[7:0]
WOM_THR[7:0]
This register holds the threshold value for the Wake on Motion Interrupt for accelerometer.
@TDK InvenSense IA M '2 0680 BIT NAME FUNCTION 1 — Write TEMP70UT7H and TEMPiouTiL to the FIFO at the sample rate; if enabled, buffering of data occurs 0— Function is disabled 1 — Write GVR07XOUT7H and GVROJOULLm the FIFO at the sample rate; if enabled, buffering of data occurs 0— Function is disabled 1 — write GVROJOULH and GVRCLVOUTiLm the HR) at the sample rate; if enabled, buffering of data occurs e 0— Function is disabled Note. Fnabling any one of the bits corresponding tot the we even though thatdata path is not enabled 1 — Write GYRO,ZOUT7H and GVROJOULLm the FiFo at the sample rate; ifenabled, buffering of data occurs e 0— Function is disabled 1 — write ACCELXOU‘LH, ACCELXOULL, ACCELJOULH, ACCELJOULL, ACCELZOU‘LH, and ACCELZOU‘LL to th 0— Function is disabled [2:0] . Reserved. BIT NAME FUNCTION This bit automatically sets to 1 when a Fsvnc interrupt has been generated The bit clears to a after the register has been read BIT NAME FUNCTION 1 — The logic level for lNT/DRDV pin is active low. 0 — The logic level for lNT/DRDV pin is active high. 1 — INT/DRDV pin is configured as open drain. 0 — INT/DRDV pin is configured as pushrpull 1 — INT/DRDV pin level held until interrupt status is cleared. 0 — INT/DRDV pin indicates interrupt pulse’s Width is 50 ps. 1 — interrupt status is cleared it any read operation is performed. 0 — interrupt status is cleared only by reading INTisTATUS register. 1 — The logic level for the FSVNC pin as an interrupt is active low 0 — The logic level for the FSVNC pin as an interrupt is active high. when this bit is equal to 1, the FSVNC pin will trigger an interrupt when it transitionsto the level specified by FSYNCJNLLE disabled from causing an interrupt. [1] . Reserved. [a] . Always set to u
IAM-20680
Document Number: DS-000196 Page 38 of 52
Revision: 1.1
9.16 REGISTER 35 FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT
NAME
FUNCTION
[7] TEMP_FIFO_EN
1 Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 Function is disabled.
[6] XG_FIFO_EN
1 Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 Function is disabled.
[5] YG_FIFO_EN
1 Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 Function is disabled.
Note: Enabling any one of the bits corresponding to the Gyros or Temp data paths, data are buffered into
the FIFO even though that data path is not enabled.
[4] ZG_FIFO_EN
1 Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 Function is disabled.
[3] ACCEL_FIFO_EN
1 Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H,
and ACCEL_ZOUT_L to the FIFO at the sample rate;
0 Function is disabled.
[2:0]
-