TPS769xxEVM User Guide Datasheet by Texas Instruments

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J9 TEXAS INSTRUMENTS TPS 769xx SOT-23 LDO Linear Regulator Evaluation Module
February 2000 Mixed-Signal Products
Users Guide
SLVU024
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
iii
Chapter Title—Attribute Reference
Preface
Related Documentation From Texas Instruments
TPS76901, TPS76912, TPS76915, TPS76918, TPS76925,
TPS76927, TPS76928, TPS76930, TPS76933, TPS76950 Ultra
Low-Power 100-mA Low-Dropout Linear Regulators
(TI
Literature Number SLVS203) provides detailed information on the
TPS769xx family of devices.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
TI is a trademark of Texas Instruments Incorporated.
iv
Running Title—Attribute Reference
v
Contents
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Output Voltages Greater Than VREF 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Output Voltages Less Than VREF 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Fixed Voltage Options 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Board Layers and Assembly Drawings 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Board Layers 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Assembly Drawings 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Testing 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Testing 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Test Setup 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
1–1 Schematic Diagram (TPS76901EVM-127, VO = 1 V) 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Fixed Voltage Version of the TPS769xxEVM–127 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Top Layer 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Top Silk Screen 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Bottom Layer (Top View) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Bottom Silk Screen (Top View) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Drill Drawing and Drill Table 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Top Assembly 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Bottom Assembly (Bottom View) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Load Regulation 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Quiescent Current vs Output Current 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Line Regulation 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Quiescent Current vs Output Current 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Line Regulation from 2.7 V 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1–1 Resistor Values 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Bill Of Materials 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
1-1
Introduction
Introduction
The TPS76901EVM–127, the TPS76918EVM-127, and the
TPS76933EVM-127 LDO regulator modules provide the user with cost-effec-
tive solutions for providing power to various low-voltage options. These EVMs
are pin-compatible with standard 3-terminal type regulators. The EVMs are set
up as 1-V, 1.8-V, and 3.3-V output at 100 mA. Various options can be imple-
mented with the board to give a range of output voltages from 0 to 5.5 V.
Topic Page
1.1 Introduction 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Output Voltages Greater Than VREF 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Output Voltages Less Than VREF 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Fixed Voltage Options 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1
Introduction
1-2
Introduction
1.1 Introduction
Low cost and simplicity of design make LDO regulators popular solutions in
low-power step-down applications where lack of isolation from the input
source is not a concern.
Applications of the EVM include single DSP C5400 device, digital camera,
medical test equipment, cell phones, consumer audio equipment, and battery
backup electronics.
Figure 1–1 shows the schematic of the TPS76901EVM-127 configured for a
1-V output. The TPS76933EVM–127 (3.3 V) schematic is shown in
Figure 1–2. The LDO utilizes a PMOS pass element, which reduces the device
quiescient current to 28 µA (max). Other features of the PMOS LDO is the low
dropout voltage of 71 mV (typ), thermal protection, over current limit, and 2 µA
shutdown quiescient current.
Figure 1–1. Schematic Diagram (TPS76901EVM-127, V
O
= 1 V)
J2
GND
R2/C2
0
C1
TL431CPK
U2
R1
Open
R5
J1
IN
(3 – 6 V)
C4
C3
+
Vfb
R6
R3
J3 OUT
Back-side
Components
R4
Open
4
5
EN
GND
IN
1
2
3
OUT
NC/FB
U1
TPS76901
1.3 k
0.001 µF
VREF = 2.495 V
IREF
130 k
1 µF4.7 µF
19.1 k
The basic functionality of the EVM is to provide output voltages of 0 V to
5.5 V.
By means of external resistors and a voltage reference (R1–R6 and U1), the
output voltage is adjusted to provide an output voltage that is either above or
below the TPS76901 nominal, internal reference voltage of 1.224 V (VFB).
OquuI Voltages Greater Than V95;
Output Voltages Greater Than V
REF
1-3
Introduction
1.2 Output Voltages Greater Than VREF
For applications requiring an output voltage greater than the internal reference
voltage (VFB) of 1.224 V, a standard linear regulator circuit with an external
voltage divider is all that is necessary. The lower section of Figure 1 shows a
generic linear regulator circuit with an input capacitor (C1), output capacitor
(C3), external voltage divider (R3/R4), and the enable circuit with either a
pullup resistor (R1) or pulldown resistor (R2) as required. None of the backside
components are required for this application. If a delayed enabled is desired,
the R1 and R2/C2 component pads can be used for an RC circuit. When using
the TPS76918EVM–127 or the TPS76933EVM–127, the external divider is
not required and R3 is a 0- resistor used to connect the sense terminal to VO.
When using the TPS76901EVM–127 (adjustable output voltage), it is recom-
mended that the divider current (IREF) be set to 7 µA. Choosing R4 to be
169 k and calculating R3 for VO accomplishes this.
R3 VO
VFB 1R4 (1)
Where:
VFB = 1.224 V
R4 = 169 k
Then R3 138.07 VO169 k
Lower value resistors can be used but are not as power efficient. Higher value
resistors should be avoided due to leakage currents at FB increasing the out-
put voltage error. Table 1–1 shows various voltage options and the suggested
resistor values.
Table 1–1.Resistor Values
OUTPUT VOLTAGE
(V)
DIVIDER RESISTANCE
(k)
(V)
R3 R4
2.5 174 169
3.3 287 169
3.6 324 169
4.0 383 169
5.0 523 169
Output Voltages Less Than V
REF
1-4
Introduction
1.3 Output Voltages Less Than VREF
Applications requiring a lower output voltage than the internal reference volt-
age needs additional circuitry. The backside components shown in the upper
section of figure 1 along with the deletion of R4 will implement this option. The
backside components function as a second (but fixed) voltage source to artifi-
cially increase the voltage at the feedback terminal, thus requiring less output
voltage to satisfy the error amplifier. The two voltage sources are summed at
the error amplifier input node and compared to the internal reference voltage
of 1.224 V. The contribution of the TL431 reference is:
VAR3
R3 R6 VREF R3
R3 R6 2.495 V
The contribution of the output voltage is:
VBR6
R3 R6 VO
The total feedback voltage at VFB then is the sum of the two previous equa-
tions:
VFB VAVBR3
R3 R6 2.495 R6
R3 R6 VO
Selecting R6 = 130 k and solving for R3 yields:
R3 VFB VO
VREF VFB
R6 125.19 102.28 VOk
This circuit can only work down to 0 V due to the lack of a negative supply volt-
age. The accuracy of the output voltage is determined by the accuracy of both
regulators, but since the load for the TL431 portion of the circuit is constant,
only its line regulation and drift are important to the output voltage accuracy.
Additional features include a delayed enable by placing a capacitor for C2 and
calculating R1 and C2 for an RC circuit. If no delayed enable is needed, then
place a zero ohm resistor for R2 since the enable pin is active low. (note that
C2 and R2 share the same component location).
Fixed Voltage Options
1-5
Introduction
1.4 Fixed Voltage Options
The TPS76918EVM–127 (Vout = 1.8 V) and the TPS76933EVM–127 (Vout = 3.3 V)
fixed voltage options are also available. Both of these EVMs use only 4 components
(see Figure 1–2) and can be used as a three terminal regulator.
Figure 1–2. Fixed Voltage Version of the TPS769xxEVM–127
J2
GND
R2/C2
0
C1
1.0 F
R1
Open
J1
IN
(3 – 6 V)
C3
4.7 F
+
Vfb
R3
0
J3 OUT
R4
Open
4
5
EN
GND
IN
1
2
3
OUT
NC/FB
U1
TPS769XX
µµ
IREF
Refer to SLVA071 application brief and TPS76901 datasheet for additional
information.
1-6
Introduction
2-1
Board Layers and Assembly Drawings
Board Layers and Assembly Drawings
This chapter shows the board layers and assembly drawings of the TPS769xx
EVM.
Topic Page
2.1 Board Layers 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Assembly Drawings 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2
A m e R 2 C / R 1 R 1 C 5 AN Fm>._w
Board Layers
2-2
Board Layers and Assembly Drawings
2.1 Board Layers
Figure 2–1. Top Layer
Figure 2–2. Top Silk Screen
a9: 3 (/i #0 67!
Board Layers
2-3
Board Layers and Assembly Drawings
Figure 2–3. Bottom Layer (Top View)
Figure 2–4. Bottom Silk Screen (Top View)
Drill Table Hole Dia (inch) Symbol Quantity Plated 0.012 + 5 Yes
Board Layers
2-4
Board Layers and Assembly Drawings
Figure 2–5. Drill Drawing and Drill Table
2 In. C / E n R S m uR AN E>n_w
Assembly Drawings
2-5
Board Layers and Assembly Drawings
2.2 Assembly Drawings
Figure 2–6. Top Assembly
Figure 2–7. Bottom Assembly (Bottom View)
2-6
Board Layers and Assembly Drawings
3-1
Testing
Testing
This chapter provides details on testing the TPS76901–EVM–127
Topic Page
3.1 Testing 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
SLVPO127U
Testing
3-2
Testing
3.1 Testing
+
Power Supply
5-V, 150-mA Supply Load
0 – 100 mA
3.2 Test Setup
Test Procedure (for TPS76901EVM-127, VO = 1 V)
1) Connect test setup as shown in the previous illustration. Set load to zero
current. Set input voltage to 5 V and apply.
2) Verify output voltage is 1.00 V ±50 mV.
3) Adjust load for 100 mA and again verify output voltage is
1.00 V ±50 mV.
Test Setup
3-3
Testing
Table 3–1.Bill Of Materials
REF DES QTY PART NUMBER DESCRIPTION MFG SIZE
C1 1 ECJ-2VF1C105Z Capacitor, ceramic, 1 µF, 16 V,
+80%–20%, Y5V Panasonic 805
C2 Not used 603
C3 1 TPSC475K035R0600 Capacitor, tantalum, 4.7 µF, 35 V, 20% AVX C
C3 (Alt) ECST1AC226R Capacitor, tantalum, 22 µF, 10 V, 20% Panasonic C
C4 1 GRM39X7R102K050A Capacitor, ceramic, 1000 pF, 50 V, 10%,
X7R muRata 603
J1 3 CA26DA-D36K-0FA Clip, surface-mount, 0.040 board, 0.090
stand-off NAS Interplex 0.1
J2 CA26DA-D36K-0FA Clip, surface-mount, 0.040 board, 0.090
stand-off NAS Interplex 0.1
J3 CA26DA-D36K-0FA Clip, Surface-mount, 0.040 board, 0.090
stand-off NAS Interplex 0.1
R1 Not used 603
R2 1 Std Resistor, chip, 0 , 1/16W, 5% 603
R3 1 Std Resistor, chip, 19.1 k, 1/16W, 1% 603
R4 Not used 603
R5 1 Std Resistor, chip, 1.3 k, 1/16W, 5% 603
R6 1 Std Resistor, chip, 130 k, 1/16W, 1% 603
U1 1 TPS76901DBV IC, LDO TI SOT23-5
U2 1 TL431CPK IC, shunt regulator, 2.5 V, 2% TI SOT-89A
1 SLVP127 PCB, 2 layer, 1 oz, 0.55 × 0.37 × 0.040
(Finished)
Figure 3–1. Load Regulation
–4
–2
0
2
4
020 40 60 80 100
VAVG = 1.036
IO – Output Current – mA 120
VO– Change in
Output Voltage – mV
LOAD REGULATION
Test Setup
3-4
Testing
Figure 3–2. Quiescent Current vs Output Current
1
1.2
1.4
1.6
1.8
2
020 40 60 80 100
QUIESCIENT CURRENT
vs
OUTPUT CURRENT
VADJ = 1 V
VIN = 5 V
IO – Output Current – mA
– Quiscent Current – mA
IQ
Figure 3–3. Line Regulation
1.02
1.025
1.03
1.035
1.04
1.045
1.05
2345678910
II=99.4 mA
II=15 mA
VI – Input Voltage – V
– Output Voltage – V
VO
LINE REGULATION
—\ mA
Test Setup
3-5
Testing
Operation of the 1-V EVM with input voltages from 2.7 V to 3 V requires in-
creasing the bias current for the TL431. Changing R5 to 180 accomplishes
this at the expense of higher quiescent currents. Figures 3–4 and 3–5 show
the results of this modification.
Figure 3–4. Quiescent Current vs Output Current
0
2
4
6
8
10
12
14
16
020406080100
QUIESCIENT CURRENT
vs
OUTPUT CURRENT
VIN = 5 V
R5=180
IO – Output Current – mA
– Quiscent Current – mA
IQ
Figure 3–5. Line Regulation from 2.7 V
1.033
1.0335
1.034
1.0345
1.035
1.0355
1.036
1.0365
1.037
1.0375
2 2.5 3 3.5
II =95.6 mA
II =12 mA
VI – Input Voltage – V
– Output Voltage – V
VO
4 4.5 5
R5=180
LINE REGULATION FROM 2.7 V
3-6
Testing

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