TPS2148, 58 Datasheet by Texas Instruments

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*9 TEXAS INSTRUMENTS 7 7 J of: — Leif — 7 7 7 J 7 7 7 J 7 7 J F 7 7j7_ 7j7_ “4 ’1" 7717 7 1 PowerP 53°33'12"" mam {II TEXAS INSTRUMENTS www.li.cnm
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1
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FEATURES
DComplete Power Management Solution for
USB Bus-Powered Peripherals
D3.3-V 200 mA Low-Dropout Voltage Regulator
With Enable
D3.3-V 340-m (Typ) High-Side MOSFET
D5-V 340-m (Typ) High-Side MOSFET
DIndependent Thermal- and Short-Circuit
Protection for LDO and Each Switch
D2.9-V to 5.5-V Operating Range
DCMOS- and TTL-Compatible Enable Inputs
D75-µA (Typ) Supply Current
DAvailable in 8-Pin MSOP (PowerPAD)
D−40°C to 85°C Ambient Temperature Range
APPLICATIONS
DUSB Peripherals
− Digital Cameras
− Zip Drives
− Speakers and Headsets
DESCRIPTION
The TPS2148 incorporates two power distribution
switches and an LDO in one small package, providing
a USB peripheral power management solution that
saves up to 60% in board space over typical
implementations.
The TPS2148 meets USB 2.0 bus-powered peripheral
requirements. An integrated LDO regulates the 5-V bus
power down to 3.3 V for the USB controller, and a
MOSFET switch that is internally connected to the
output of the LDO simplifies meeting the suspend and
enumeration current requirements imposed by the USB
specification.
A second switch is available to support a downstream
port, stage power to a second voltage regulator, or
disable power to selected circuitry in power-save
modes.
Each power-distribution switch is capable of supplying
200 mA of continuous current, and the independent
logic enables are compatible with 5-V logic and 3-V
logic. The switches and the LDO are designed with
controlled rise times and fall times to minimize current
surges.
The TPS2148 has active-low enables while the
TPS2158 has active-high enables.
LDO and dual switch family selection guide and schematics
LDO LDO_OUT
LDO_ADJ
OC1
OUT1
OUT2
OC2
VIN/SW1
LDO_EN
EN1
SW2
EN2
GND
TPS2145/55
TSSOP−14
LDO
OC1
OC2
EN1
SW2
EN2
GND
TPS2147/57
MSOP−10
LDO
EN2
EN1
GND
TPS2148/58
MSOP−8
LDO
OC
EN1
EN2
GND
TPS2149/59
MSOP−8
VIN/SW1 LDO_OUT
OUT1
OUT2
VIN/SW1
LDO_EN
LDO_OUT
OUT2
OUT1
VIN LDO_OU
T
OUT1
OUT2
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PowerPAD is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PACKAGE 17.1 mWF {'5 TEXAS INSTRUMENTS
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AVAILABLE OPTIONS
PACKAGE
PACKAGED DEVICES
TADESCRIPTION
PACKAGE
AND PIN
COUNT ACTIVE LOW
(SWITCH) ACTIVE HIGH
(SWITCH)
Adjustable LDO with LDO enable TSSOP-14 TPS2145IPWP TPS2155IPWP
3.3-V fixed LDO MSOP-10 TPS2147IDGQ TPS2157IDGQ
−40°C to 85°C3.3-V Fixed LDO with LDO enable and LDO output
switch MSOP-8 TPS2148IDGN TPS2158IDGN
3.3-V Fixed LDO, shared input with switches MSOP-8 TPS2149IDGN TPS2159IDGN
NOTE: All options available taped and reeled. Add an R suffix (e.g. TPS2145IPWPR)
TPS2148, TPS2158
MSOP (DGN) PACKAGE
(TOP VIEW)
EN1
EN2
LDO_EN
GND
8
7
6
5
1
2
3
4
OUT1
VIN/SWIN1
LDO_OUT
OUT2
Pins 7 and 8 are active high for TPS2158.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range: VI(VIN/SWIN1), VI(ENx), VI(LDO_EN) −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range: VO(OUTx), VO(LDO_OUT), VO(OCx) −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(OUT), IO(LDO_OUT) Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual-junction temperature range, TJ−40°C to 110°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged device model (CDM) 1 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
MSOP8 1455.5 mW 17.1 mW/°C684.9 mW 428.08 mW
Input voHage Vw VINJSWIN1 Vw ENx Vw LDO EN Vomum and SW‘NZ No load an LDOioUT OUTX LDO_EN : don't care b TEXAS INSTRUMENTS
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recommended operating conditions
MIN MAX UNIT
VI(VIN/SWIN1) 2.9 5.5
Input voltage VI(ENx) 0 5.5 V
Input voltage
VI(LDO_EN) 0 5.5
V
Continuous output current, IO
LDO_OUT 200
mA
Continuous output current, IOOUT1, OUT2 150 mA
Output current limit, IO(LMT)
LDO_OUT 275 550
mA
Output current limit, IO(LMT) OUT1, OUT2 200 400 mA
Operating virtual-junction temperature range, TJ−40 100 °C
electrical characteristics over recommended operating junction-temperature range,
2.9 V VI(VIN/SWIN1) 5.5 V, TJ = −40°C to 100°C (unless otherwise noted)
general
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Off-state supply current
VI(ENx) = 5 V (inactive),
VI(LDO_EN) = 0 V (inactive),
VO(LDO_OUT) = no load,
VO(OUTx) = no load
20 µA
Forward leakage current
VI(VIN/SWIN1) = 5 V VI(ENx) = 5 V (inactive),
VI(LDO_EN) = 0 V (inactive),
VO(LDO_OUT) = 0 V,
VO(OUTx) = 0 V
(measured from outputs to
ground)
1µA
V = 5 V,
VI(LDO_EN) = 5 V (active),
VI(ENx) = on (active) 150 µA
IITotal input current at VIN/SWIN1
and SWIN2
VI(VIN/SWIN1) = 5 V,
No load on OUTx,
No load on LDO_OUT
VI(LDO_EN) = 0 V (inactive),
VI(ENx) = on (active) 100 µA
and SWIN2
No load on LDO_OUT
VI(LDO_EN) = 5 V (active),
VI(ENx) = off (inactive) 100 µA
power switches
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static drain-source on-state
resistance, VIN/SWIN1 or
IO(LDO_OUT) = 50 mA,
IOUT1 and IOUT2 = 150 mA, TJ = −40°C to 100°C680
m
rDS(on
resistance, VIN/SWIN1 or
SWIN2 to OUTx IO(LDO_OUT) = 50 mA,
IOUT1 and IOUT2 = 150 mA, TJ = 25°C340
m
VI(ENx) = 5 V, VI(ENx) = 0 V,
VI(VIN/SWIN1) = 5 V 10
Ilkg(R) Reverse leakage current at
OUTx VO(OUTx) = 5 V,
LDO_EN = don’t care VI(ENx) = 5 V, VI(ENx) = 0 V,
VI(VIN/SWIN1) = 2.9 V 10 µA
OUTx
LDO_EN = don’t care
VI(ENx) = 5 V, VI(ENx) = 0 V,
VI(VIN/SWIN1) = 0 V 10
IOS Short circuit output current OUTx connected to GND, device enabled into short circuit 0.2 0.4 A
NOTE 1: Specified by design, not tested in production.
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electrical characteristics over recommended operating junction-temperature range,
2.9 V VI(VIN/SWIN1) 5.5 V, TJ = −40°C to 100°C (unless otherwise noted)
timing parameters, power switches
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Turnon time, OUTx switch, (see Note 1)
CL = 100 µF
RL = 33
0.5 6
ton Turnon time, OUTx switch, (see Note 1) CL = 1 µFRL = 33 0.1 3
Turnoff time, OUTx switch (see Note 1)
CL = 100 µF
RL = 33
5.5 10
ms
toff Turnoff time, OUTx switch (see Note 1) CL = 1 µFRL = 33 0.05 2 ms
Rise time, OUTx switch (see Note 1)
CL = 100 µF
RL = 33
0.5 5
trRise time, OUTx switch (see Note 1) CL = 1 µFRL = 33 0.1 2
Fall time, OUTx switch (see Note 1)
CL = 100 µF
RL = 33
5.5 9
tfFall time, OUTx switch (see Note 1) CL = 1 µFRL = 33 0.05 1.2
NOTE 1. Specified by design, not tested in production.
undervoltage lockout at VIN/SWIN1
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO Threshold 2.2 2.85 V
Hysteresis (see Note 1) 260 mV
Deglitch (see Note 1) 50 µs
NOTE 1. Specified by design, not tested in production.
undervoltage lockout at switch 2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO Threshold 2.2 2.85 V
Hysteresis (see Note 1) 260 mV
Deglitch (see Note 1) 50 µs
NOTE 1. Specified by design, not tested in production.
Reverse leakage current mm m 0.1 ms‘ RL :15 a ammo our) b TEXAS INSTRUMENTS
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electrical characteristics over recommended operating junction-temperature range,
2.9 V VI(VIN/SWIN1) 5.5 V, VI(ENx) = 0 V, VI(LDO_EN) = 5 V, CL(LDO_OUT) = 10 µF,
TJ = −40°C to 100°C (unless otherwise noted)
3.3 V LDO
PARAMETER TEST CONDITIONSMIN TYP MAX UNIT
VOOutput voltage, dc VI(VIN/SWIN1) = 4.25 V to 5.25 V,
IO(LDO_OUT) = 0.5 mA to 200 mA 3.20 3.3 3.40 V
Dropout voltage VI(VIN/SWIN1) = 3.2 V, IO = 200 mA, IO(OUT) = 150
mA 0.35 V
Line regulation voltage (see Note 1) VI(VIN/SWIN1) = 4.25 V to 5.25 V, IO(LDO_OUT) = 5
mA 0.1 %/V
Load regulation voltage (see Note 1) VI(VIN/SWIN1) = 4.25 V, IO(LDO_OUT) = 5 mA to 200
mA 0.4 1%
IOS Short-circuit current limit VI(VIN/SWIN1) = 4.25 V, LDO_OUT connected to
GND 0.275 0.33 0.55 A
Reverse leakage current into
LDO_OUT
VO(LDO_OUT) = 3.3 V, VI(VIN/SWIN1) = 0 V,
VI(LDO_EN) = 0 V 10 µA
lkg(R)
Reverse leakage current into
LDO_OUT VO(LDO_OUT) = 5.5 V, VI(VIN/SWIN1) = 2.7 V,
VI(LDO_EN) = 0 V 10 µA
Power supply rejection f = 1 kHz, CL(LDO_OUT) = 4.7 µF, ESR = 0.25 , IO =
5 mA, VI(VIN/SWIN1)p−p = 100 mV 50 dB
ton Turnoff time, LDO_EN
transitioning low (see Note 1) RL = 16 , CL(LDO_OUT) = 10 µF 0.25 1 ms
toff Turnon time, LDO_EN
transitioning high (see Note 1) RL = 16 , CL(LDO_OUT) = 10 µF 0.1 1 ms
Ramp-up time, LDO_OUT (0% to 90%) VI(LDO_EN) = 5 V, VIN ramping up from 10% to 90%
in 0.1 ms, RL = 16 , CL(LDO_OUT) = 10 µF0.1 1 ms
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
NOTE 1. Specified by design, not tested in production.
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electrical characteristics over recommended operating junction-temperature range,
2.9 V VI(VIN/SWIN1) 5.5 V, 2.9 V VI(SWIN2) 5.5 V, VI(ENx) = 0 V, VI(LDO_EN) = 5 V, TJ = −40°C to
100°C (unless otherwise noted)
enable input, ENx (active low)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IIInput current, pullup (source) VI(ENx) = 0 V 5µA
enable input, ENx (active high)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IIInput current, pulldown (sink) VI(ENx) = 5 V 5µA
enable input, LDO_EN (active high)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IIInput current, pulldown VI(LDO_EN) = 5 V 5µA
Falling-edge deglitch (see Note 1) 50 µs
NOTE 1. Specified by design, not tested in production.
thermal shutdown characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
First thermal shutdown (shuts down switch or regulator
in overcurrent) Occurs at or above specified temperature
when overcurrent is present. 120
Recovery from thermal shutdown 110
°C
Second thermal shutdown (shuts down all switches and
regulator) Occurs on rising temperature, irrespective of
overcurrent. 155
°C
Second thermal shutdown hysteresis 10
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TPS2148 functional block diagram
3.3 V / 200 mA
LDO
CS
Driver
Charge
Pump Current
Limit
Thermal
Sense
CS
Driver
Thermal
Sense
Current
Limit
LDO_OUT
OUT2
OUT1
VIN/SWIN1
LDO_EN
EN2
EN2
GND
Terminal Functions
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME
TPS2148 TPS2158
I/O
DESCRIPTION
EN1 8 ILogic level enable to transfer power to OUT1
EN1 8
I
Logic level enable to transfer power to OUT1
EN2 7 ILogic level enable to transfer power to OUT2
EN2 7
I
Logic level enable to transfer power to OUT2
GND 5 5 Ground
LDO_EN 6 6 I Logic level LDO enable. Active high.
LDO_OUT 3 3 O LDO output
OUT1 1 1 OSwitch 1 output
OUT2 4 4
O
Switch 2 output
VIN/SWIN1 2 2 I Input for LDO and switch 1; device supply voltage
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detailed description
VIN/SWIN1
The VIN/SWIN1 serves as the input to the internal LDO and as the input to one N-channel MOSFET. The 3.3-V
LDO has a dropout voltage of 0.35 V and is rated for 200 mA of continuous current. The power switch is an
N-channel MOSFET with a maximum on-state resistance of 580 mΩ. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch is rated
at 150 mA, continuous current. VIN/SWIN1 must be connected to a voltage source for device operation.
OUTx
OUT1 and OUT2 are the outputs from the internal power-distribution switches.
LDO_OUT
LDO_OUT is the output of the internal 200-mA LDO. It is also the input to a second power switch. This power
switch in an N-channel MOSFET with a maximum on-state resistance of 580 m. Configured as a high-side
switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch
is rated at 150 mA, continuous current.
LDO_EN
The active high input, LDO_EN, is used to enable the internal LDO and is compatible with TTL and CMOS logic.
enable (ENx, ENx)
The logic enable disables the power switch. Both switches have independent enables and are compatible with
both TTL and CMOS logic.
current sense
A sense FET monitors the current supplied to the load. Current is measured more efficiently by the sense FET
than by conventional resistance methods. When an overload or short circuit is encountered, the current-sense
circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power
FET into its saturation region, which switches the output into a constant-current mode and holds the current
constant while varying the voltage on the load.
thermal sense
A dual-threshold thermal trip is implemented to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature
rises to approximately 120°C, the internal thermal sense circuitry determines which power switch is in an
overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the
adjacent power switch. Because hysteresis is built into the thermal sense, the switch turns back on after the
device has cooled approximately 10 degrees. The switch continues to cycle off and on until the fault is removed.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2.5 V, a control
signal turns off the power switch.
toff
tpd(off)
ton
tpd(on)
50% 50%
90% 90%
10% 10%
trtf
90% 90%
10% 10%
VI(ENx)
VO(OUTx)
VO(OUTx)
TIMING
Figure 1. Timing and Internal Voltage Regulator Transition Waveforms
VI
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TYPICAL CHARACTERISTICS
Figure 2
VO(OUT)
(2 V/div) VI = 5 V
TA = 25°C
CL = 1 µF
RL = 25
SWITCH TURNON DELAY AND RISE TIME
WITH 1-µF LOAD
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4.2
t − Time − ms
VI(EN)
(5 V/div)
Figure 3
SWITCH TURNOFF DELAY AND FALL TIME
WITH 1-µF LOAD
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4.2
t − Time − ms
VO(OUT)
(2 V/div) VI = 5 V
TA = 25°C
CL = 1 µF
RL = 25
VI(EN)
(5 V/div)
Figure 4
SWITCH TURNON DELAY AND RISE TIME
WITH 120-µF LOAD
t − Time − ms
02 46 8
10 12 14 16 18 20
VO(OUT)
(2 V/div) VI = 5 V
TA = 25°C
CL = 120 µF
RL = 25
VI(EN)
(5 V/div)
Figure 5
SWITCH TURNOFF DELAY AND FALL TIME
WITH 120-µF LOAD
t − Time − ms
04 81216202428323640
VO(OUT)
(2 V/div)
VI = 5 V
TA = 25°C
CL = 120 µF
RL = 25
VI(EN)
(5 V/div)
VI
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TYPICAL CHARACTERISTICS
Figure 6
SHORT-CIRCUIT CURRENT, SWITCH
ENABLED INTO A SHORT
t − Time − ms
01 23 45678910
IO(OUT)
(100 mA/div)
VI(EN)
(5 V/div)
Figure 7
VI(LDO_EN)
(5 V/div)
VO(LDO_OUT)
(1 V/div
LDO TURNON DELAY AND RISE TIME
WITH 4.7-µF LOAD
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4.2
t − Time − ms
VI = 5 V
TA = 25°C
CL = 4.7 µF
RL = 13.2
Figure 8
LINE TRANSIENT RESPONSE
t − Time − µs
0 100 200 300 400 500 600 700 800 900 100
0
VO(LDO_OUT)
(0.05 V/div) TA = 25°C
CL(LDO_OUT) = 4.7 µF
ESR = 1
IO(LDO_OUT) = 200 mA
5.25 V
VI(VIN)
4.25 V
Figure 9
LOAD TRANSIENT RESPONSE
t − Time − µs
0 100 200 300 400 500 600 700 800 900100
0
VO(LDO_OUT)
(100 mV/div)
TA = 25°C
CL(LDO_OUT) = 4.7 µF
ESR = 1
IO(LDO_OUT)
(200 mA/div)
um _ Supply Current—VA rDS(on)_ Slalil: Drain-Source OrI-Slale Resistance —i2 I40 |20 |00 30 60 40 20 0 >40 —20 0 20 40 so so 100 TJ — Temperature » it: Figure 10 0.6 0.55 0.5 0.45 sw1 0.4 5/ s 2 0.35 4/ 0.25 0.2 0.15 P —40 —2a a 20 40 so so 100 TJ — Junction Temperature » °c Figure 12 Q“ TEXAS INSTRUMENTS www.li.cnm
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TYPICAL CHARACTERISTICS
Figure 10
0
20
40
60
80
100
120
140
−40 −20 0 20 40 60 80 100
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
DD
I Supply Current − −Aµ
TJ − Temperature − °CFigure 11
0
20
40
60
80
100
120
140
2.5 3 3.5 4 4.5 5 5.5
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
DD
I Supply Current − −Aµ
VCC − Supply Voltage − V
Figure 12
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
−40 −20 0 20 40 60 80 100
SW1
SW2
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
rDS(on)− Static Drain-Source On-State Resistance −
TJ − Junction Temperature − °C
Figure 13
0.3
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
2.5 3 3.5 4 4.5 5 5.
5
SW1
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
SUPPLY VOLTAGE
VCC − Supply Voltage
SW2
rDS(on)− Static Drain-Source On-State Resistance −
Shun Circuil Currenl — mA 400 380 360 340 320 300 280 260 240 220 200 —40 —20 o 20 40 so TJ — Free-Air Temperature » to Figure 14 80 100 12 *9 TEXAS INSTRUMENTS www.li.com
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12 www.ti.com
TYPICAL CHARACTERISTICS
Figure 14
200
220
240
260
280
300
320
340
360
380
400
−40 −20 0 20 40 60 80 100
Short Circuit Current − mA
SHORT CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
TJ − Free-Air Temperature − °C
SW1
SW2
Figure 15
200
220
240
260
280
300
320
340
360
380
400
2.5 3 3.5 4 4.5 5 5.5
Short Circuit Current − mA
SHORT CIRCUIT CURRENT
vs
SUPPLY VOLTAGE
SW1
SW2
VCC − Supply Voltage
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
−40 −25 −10 5 20 35 50 65
UVLO − Undervoltage Lockout − V
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
Rising
Falling
80 95 110
Figure 16
3.3 v Circuitry Q“ TEXAS INSTRUMENTS www.li.cnm
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www.ti.com
APPLICATION INFORMATION
USB
Function
Controller
5-V
Circuitry
3.3 V Circuitry
0.1 µF10 µF
TPS2148
3.3 V
LDO
1.5 k
0.1 µF4.7 µF
D+
D−
GND
5 V
Upstream Data Port
Figure 17. Example of a Peripheral Design With TPS2148
external capacitor requirements on power lines
A ceramic bypass capacitor (0.01-µF to 0.1-µF) between VIN/SWIN1 and GND, close to the device, is
recommended to improve load transient response and noise rejection.
A bulk capacitor (4.7-µF ) between VIN/SWIN1 and GND is also recommended, especially if load transients in
the hundreds of milliamps with fast rise times are anticipated.
A 66-µF bulk capacitor is recommended from OUTx to ground, especially when the output load is heavy. This
precaution helps reduce transients seen on the power rails. Additionally, bypassing the outputs with a 0.1-µF
ceramic capacitor improves the immunity of the device to short-circuit transients.
LDO output capacitor requirements
Stabilizing the internal control loop requires an output capacitor connected between LDO_OUT and GND. The
minimum recommended capacitance is a 4.7 µF with an ESR value between 200 m and 10 . Solid tantalum
electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the
ESR requirements.
overcurrent
A sense FET is used to measure current through the device. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current. Complete shut down occurs only if the fault is present long enough to
activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output is shorted before the device is
enabled or before VIN has been applied. The TPS2148 and TPS2158 sense the short and immediately switches
to a constant-current output.
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a very short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded. The TPS2148 and TPS2158 are capable of delivering current up to the current-limit threshold without
damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
*9 TEXAS INSTRUMENTS
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APPLICATION INFORMATION
power dissipation and junction temperature
The main source of power dissipation for the TPS2148 and TPS2158 comes from the internal voltage regulator
and the N-channel MOSFETs. Checking the power dissipation and junction temperature is always a good
design practice and it starts with determining the rDS(on) of the N-channel MOSFET according to the input voltage
and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and
read rDS(on) from the graphs shown in the Typical Characteristics section of this data sheet. Using this value,
the power dissipation per switch can be calculated using:
PD+rDS(on) I2
Multiply this number by two to get the total power dissipation coming from the N-channel MOSFETs.
The power dissipation for the internal voltage regulator is calculated using:
PD+ǒVI–VO(min)Ǔ IO
The total power dissipation for the device becomes:
PD(total) +PD(voltage regulator) )ǒ2 PD(switch)Ǔ
Finally, calculate the junction temperature:
TJ+PD RqJA )TA
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance °C/W, equal to inverting the derating factor found on the power
dissipation table in this datasheet.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
b TEXAS INSTRUMENTS
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15
www.ti.com
APPLICATION INFORMATION
thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS2148 and TPS2158 into constant-current mode at first, which
causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across
the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high
levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 10 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.
The TPS2148 and TPS2158 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 120°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 120°C and reach
155°C, the device will turn off.
undervoltage lockout (UVLO)
An undervoltage lockout ensures that the device (LDO and switches) is in the off state at power up. The UVLO
will also keep the device from being turned on until the power supply has reached the start threshold (see
undervoltage lockout table), even if the switches are enabled. The UVLO will also be activated whenever the
input voltage falls below the stop threshold as defined in the undervoltage lockout table. This facilitates the
design of hot-insertion systems where it is not possible to turn off the power switches before input power is
removed. Upon reinsertion, the power switches will be turned on with a controlled rise time to reduce EMI and
voltage overshoots.
universal serial bus (USB) applications
The universal serial bus (USB) interface is a multiplexed serial bus operating at either 12 Mb/s, or 1.5 Mb/s for
USB 1.1, or 480 Mb/s for USB 2.0. The USB interface is designed to accommodate the bandwidth required by
PC peripherals such as keyboards, printers, scanners, and mice. The four-wire USB interface was conceived
for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two
lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub or across long cables. Each function must provide its own regulated
3.3 V from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions
The TPS2148 and TPS2158 are well suited for USB peripheral applications.
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APPLICATION INFORMATION
USB power distribution requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
Hosts/self-powered hubs must:
Current-limit downstream ports
Report overcurrent conditions on USB VBUS
DBus-powered hubs must:
Enable/disable power to downstream ports
Power up at <100 mA
Limit inrush current (<44 and 10 µF)
DFunctions must:
Limit inrush currents
Power up at <100 mA
USB applications
Figure 17 shows the TPS2148 being used in a USB bus-powered peripheral design. The internal 3.3-V LDO
is used to provide power for the USB function controller as well as to the 1.5-k pullup resistor.
Switch 1 provides power to the 5-V circuitry which is only enabled after enumeration is complete to ensure
meeting the 100-mA USB power up requirement. Switch 2 provides power to the 3.3-V circuitry. Switch 2 is also
enabled only after enumeration is complete to satisfy the 100 mA requirement.
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS2148IDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AXB
TPS2158IDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AXC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
www.ti.com
GENERIC PACKAGE VIEW
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
PowerPAD VSSOP - 1.1 mm max heightDGN 8
SMALL OUTLINE PACKAGE
3 x 3, 0.65 mm pitch
4225482/A
www.ti.com
PACKAGE OUTLINE
C
6X 0.65
2X
1.95
8X 0.38
0.25
5.05
4.75 TYP
SEATING
PLANE
0.15
0.05
0.25
GAGE PLANE
0 -8
1.1 MAX
0.23
0.13
1.57
1.28
1.89
1.63
B3.1
2.9
NOTE 4
A
3.1
2.9
NOTE 3
0.7
0.4
PowerPAD VSSOP - 1.1 mm max heightDGN0008D
SMALL OUTLINE PACKAGE
4225481/A 11/2019
1
4
5
8
0.13 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
PowerPAD is a trademark of Texas Instruments.
TM
A 20
DETAIL A
TYPICAL
SCALE 4.000
EXPOSED THERMAL PAD
1
45
8
9
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(2)
NOTE 9
(3)
NOTE 9
(1.22)
(0.55)
( 0.2) TYP
VIA
(1.57)
(1.89)
PowerPAD VSSOP - 1.1 mm max heightDGN0008D
SMALL OUTLINE PACKAGE
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SYMM
SYMM
1
4
5
8
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
SEE DETAILS
9
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(1.57)
BASED ON
0.125 THICK
STENCIL
(1.89)
BASED ON
0.125 THICK
STENCIL
PowerPAD VSSOP - 1.1 mm max heightDGN0008D
SMALL OUTLINE PACKAGE
4225481/A 11/2019
1.33 X 1.600.175
1.43 X 1.730.15
1.57 X 1.89 (SHOWN)0.125
1.76 X 2.110.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
SYMM
SYMM
1
45
8
METAL COVERED
BY SOLDER MASK SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
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