TLC5940 Datasheet by Texas Instruments

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Delay
x0
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
Temperature
ErrorFlag
(TEF)
Max.OUTn
Current
Delay
x1
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
Delay
x15
6−BitDot
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
OUT0
OUT1
OUT15
SOUT
SINSCLK
IREF
XERR
XLAT
GSCLK
BLANK
DCPRG
DCPRG
DCPRG
VPRG
VPRG
VPRG
GNDVCC
VPRG
Input
Shift
Register
Input
Shift
Register
VPRG 110
2312
191180
9590
116
5
VPRG
0
0
95
96
191
LEDOpen
Detection
(LOD)
5
9590
6 11
DCPRG
0
192
96
0
1
01 0
1
01
GSCounter CNT
CNT
CNT
CNT
96
96
Status
Information:
LOD,
TED,
DCDATA
192
0
191
1
0
0
1
VREF =1.24V
Correction
6−BitDot
Correction
6−BitDot
Correction
01
Blank
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TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
TLC5940 16-Channel LED Driver With DOT Correction and Grayscale PWM Control
1 Features 3 Description
The TLC5940 is a 16-channel, constant-current sink
1 16 Channels LED driver. Each channel has an individually
12 bit (4096 Steps) Grayscale PWM Control adjustable 4096-step grayscale PWM brightness
Dot Correction control and a 64-step, constant-current sink (dot
correction). The dot correction adjusts the brightness
6 bit (64 Steps) variations between LED channels and other LED
Storable in Integrated EEPROM drivers. The dot correction data is stored in an
Drive Capability (Constant-Current Sink) integrated EEPROM. Both grayscale control and dot
correction are accessible through a serial interface. A
0 mA to 60 mA (VCC < 3.6 V) single external resistor sets the maximum current
0 mA to 120 mA (VCC > 3.6 V) value of all 16 channels.
LED Power Supply Voltage up to 17 V The TLC5940 features two error information circuits.
• VCC =3Vto5.5V The LED open detection (LOD) indicates a broken or
Serial Data Interface disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature
Controlled In-Rush Current condition.
30 MHz Data Transfer Rate
CMOS Level I/O Device Information(1)
Error Information PART NUMBER PACKAGE BODY SIZE (NOM)
LOD: LED Open Detection PDIP (28) 35.69 mm × 6.73 mm
TEF: Thermal Error Flag TLC5940 HTSSOP (28) 9.70 mm × 4.40 mm
VQFN (32) 5.00 mm × 5.00 mm
2 Applications (1) For all available packages, see the orderable addendum at
the end of the datasheet.
Monocolor, Multicolor, Full-Color LED Displays
LED Signboards
Display Backlighting
General, High-Current LED Drive
Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
8.2 Functional Block Diagram ....................................... 13
1 Features.................................................................. 1
8.3 Feature Description................................................. 13
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 18
3 Description ............................................................. 19 Application and Implementation ........................ 23
4 Revision History..................................................... 29.1 Application Information............................................ 23
5 Pin Configuration and Functions......................... 39.2 Typical Application ................................................. 23
6 Specifications......................................................... 510 Power Supply Recommendations ..................... 25
6.1 Absolute Maximum Ratings ...................................... 511 Layout................................................................... 25
6.2 ESD Ratings.............................................................. 511.1 Layout Guidelines ................................................. 25
6.3 Recommended Operating Conditions....................... 511.2 Layout Example .................................................... 25
6.4 Thermal Information.................................................. 611.3 Power Dissipation Calculation .............................. 26
6.5 Electrical Characteristics........................................... 712 Device and Documentation Support ................. 27
6.6 Switching Characteristics.......................................... 812.1 Community Resources.......................................... 27
6.7 Typical Characteristics.............................................. 912.2 Trademarks ........................................................... 27
7 Parameter Measurement Information ................ 11 12.3 Electrostatic Discharge Caution............................ 27
7.1 Test Parameter Equations ...................................... 12 12.4 Glossary ................................................................ 27
8 Detailed Description ............................................ 13 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................. 13 Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2007) to Revision D Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision B (September 2007) to Revision C Page
Changed tsu5 setup time from: 30 ms to: 30 ns ...................................................................................................................... 6
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THERMAL
PAD
GSCLK
24
SOUT
23
XERR
22
OUT15
21
OUT14
20
OUT13
19
OUT12
18
OUT11
17
OUT1016
OUT9
15
OUT8
14
NC
13
NC
12
OUT7
11
OUT6
10
OUT5
9
OUT4 8
OUT3 7
OUT2 6
OUT1 5
OUT0 4
VPRG 3
SIN 2
SCLK 1
DCPRG 25
IREF 26
VCC 27
NC 28
NC 29
GND 30
BLANK 31
XLAT 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
22
21
20
19
26
25
24
23
28
27
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
GND
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
SCLK
XLAT
BLANK
OUT0
VPRG
SIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
BLANK
XLAT
SCLK
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
Thermal
PAD
TLC5940
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SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
5 Pin Configuration and Functions
PWP Package NT Package
28-Pin HTSSOP 28-Pin PDIP
Top View Top View
RHB Package
32-Pin VQFN
Top View
NC – No internal connection
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Pin Functions
PIN TYPE DESCRIPTION
NAME DIP NO. PWP NO. RHB NO.
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF.
BLANK 23 2 31 I GS counter is also reset. When BLANK = L, OUTn are controlled by
grayscale PWM control.
Switch DC data input. When DCPRG = L, DC is connected to
EEPROM. When DCPRG = H, DC is connected to the DC register.
DCPRG 19 26 25 I DCPRG also controls EEPROM writing, when VPRG = V(PRG).
EEPROM data = 3 Fh (default)
GND 22 1 30 G Ground
GSCLK 18 25 24 I Reference clock for grayscale PWM control
IREF 20 27 26 I Reference current terminal
— — 12
— — 13
NC No connection
— — 28
— — 29
OUT0 28 7 4 O Constant current output
OUT1 1 8 5 O Constant current output
OUT2 2 9 6 O Constant current output
OUT3 3 10 7 O Constant current output
OUT4 4 11 8 O Constant current output
OUT5 5 12 9 O Constant current output
OUT6 6 13 10 O Constant current output
OUT7 7 14 11 O Constant current output
OUT8 8 15 14 O Constant current output
OUT9 9 16 15 O Constant current output
OUT10 10 17 16 O Constant current output
OUT11 11 18 17 O Constant current output
OUT12 12 19 18 O Constant current output
OUT13 13 20 19 O Constant current output
OUT14 14 21 20 O Constant current output
OUT15 15 22 21 O Constant current output
SCLK 25 4 1 I Serial data shift clock
SIN 26 5 2 I Serial data input
SOUT 17 24 23 O Serial data output
VCC 21 28 27 I Power supply voltage
Multifunction input pin. When VPRG = GND, the device is in GS mode.
When VPRG = VCC, the device is in DC mode. When VPRG = V(VPRG),
VPRG 27 6 3 I DC register data can programmed into DC EEPROM with
DCPRG=HIGH. EEPROM data = 3 Fh (default)
Error output. XERR is an open-drain terminal. XERR goes L when LOD
XERR 16 23 22 O or TEF is detected.
Level triggered latch signal. When XLAT = high, the TLC5940 writes
data from the input shift register to either GS register (VPRG = low) or
XLAT 24 3 32 I DC register (VPRG = high). When XLAT = low, the data in GS or DC
register is held constant.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC –0.3 6 V
Input voltage(2) V(BLANK), V(DCPRG), V(SCLK), V(XLAT), V(SIN),–0.3 VCC +0.3 V
V(GSCLK), V(IREF)
V(SOUT), V(XERR) –0.3 VCC +0.3 V
Output voltage V(OUT0) to V(OUT15) –0.3 18 V
Output current (dc) 130 mA
EEPROM program range V(VPRG) –0.3 24 V
EEPROM write cycles 50
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operting Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±500
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN NOM MAX UNIT
DC CHARACTERISTICS
VCC Supply Voltage 3 5.5 V
VOVoltage applied to output (OUT0–OUT15) 17 V
VIH High-level input voltage 0.8 VCC VCC V
VIL Low-level input voltage GND 0.2 VCC V
IOH High-level output current VCC = 5 V at SOUT –1 mA
IOL Low-level output current VCC = 5 V at SOUT, XERR 1 mA
OUT0 to OUT15, VCC < 3.6 V 60 mA
IOLC Constant output current OUT0 to OUT15, VCC > 3.6 V 120 mA
V(VPRG) EEPROM program voltage 20 22 23 V
TAOperating free-air temperature range -40 85 °C
AC CHARACTERISTICS
VCC = 3 V to 5.5 V, TA= –40°C to 85°C (unless otherwise noted)
f(SCLK) Data shift clock frequency SCLK 30 MHz
f(GSCLK) Grayscale clock frequency GSCLK 30 MHz
twh0/twl0 SCLK pulse duration SCLK = H/L (see Figure 11) 16 ns
twh1/twl1 GSCLK pulse duration GSCLK = H/L (see Figure 11) 16 ns
twh2 XLAT pulse duration XLAT = H (see Figure 11) 20 ns
twh3 BLANK pulse duration BLANK = H (see Figure 11) 20 ns
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Recommended Operating Conditions (continued)
MIN NOM MAX UNIT
tsu0 SIN to SCLK (1) (see Figure 11) 5 ns
tsu1 SCLK to XLAT (see Figure 11) 10 ns
tsu2 VPRG ↑↓to SCLK (see Figure 11) 10 ns
tsu3 Setup time VPRG ↑ ↓XLAT (see Figure 11) 10 ns
tsu4 BLANK to GSCLK (see Figure 11) 10 ns
tsu5 XLAT to GSCLK (see Figure 11) 30 ns
tsu6 VPRG to DCPRG (see Figure 16) 1 ms
th0 SCLK to SIN (see Figure 11) 3 ns
th1 XLAT to SCLK (see Figure 11) 10 ns
th2 SCLK to VPRG ↑↓(see Figure 11) 10 ns
Hold Time
th3 XLAT to VPRG ↑↓(see Figure 11) 10 ns
th4 GSCLK to BLANK (see Figure 11) 10 ns
th5 DCPRG to VPRG (see Figure 11) 1 ms
tprog Programming time for EEPROM (see Figure 16) 20 ms
(1) and indicates a rising edge, and a falling edge respectively.
6.4 Thermal Information
TLC5940
THERMAL METRIC(1) PWP (HTSSOP) RHB (VQFN) UNIT
28 PINS 32 PINS
RθJA Junction-to-ambient thermal resistance 36.7 34.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.9 36.8 °C/W
RθJB Junction-to-board thermal resistance 15.9 8.5 °C/W
ψJT Junction-to-top characterization parameter 0.6 0.3 °C/W
ψJB Junction-to-board characterization parameter 15.8 8.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 1.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
6.5 Electrical Characteristics
VCC = 3 V to 5.5 V, TA= –40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = -1 mA, SOUT VCC –0.5 V
VOL Low-level output voltage IOL = 1 mA, SOUT 0.5 V
VI= VCC or GND; BLANK, DCPRG, GSCLK, SCLK, SIN, –1 1
XLAT
μA
VI= GND; VPRG –1 1
IIInput current
VI= VCC; VPRG 50
VI= 22 V; VPRG; DCPRG = VCC 4 10 mA
No data transfer, all output OFF, 0.9 6
VO= 1 V, R(IREF) = 10 k
No data transfer, all output OFF, 5.2 12
VO= 1 V, R(IREF) = 1.3 k
ICC Supply current mA
Data transfer 30MHz, all output ON, 16 25
VO= 1 V, R(IREF) = 1.3 k
Data transfer 30MHz, all output ON, 30 60
VO= 1 V, R(IREF) = 640
Constant sink current (see
IO(LC) All output ON, VO= 1 V, R(IREF) = 640 54 61 69 mA
Figure 10)
All output OFF, VO= 15 V, R(IREF) = 640 ,
Ilkg Leakage output current 0.1 μA
OUT0 to OUT15
All output ON, VO= 1 V, R(IREF) = 640 ,±1% ±4%
OUT0 to OUT15, –20°C to 85°C
All output ON, VO= 1V, R(IREF) = 640 ,±1% ±8%
OUT0 to OUT15(1)
Constant sink current error
ΔIO(LC0) (see Figure 10)All output ON, VO= 1V, R(IREF) = 320 ,±1% ±6%
OUT0 to OUT15, –20°C to 85°C
All output ON, VO= 1V, R(IREF) = 320 ,±1% ±8%
VCC = 4.5 V to 5.5 V, OUT0 to OUT15(1)
–2%
Constant sink current error Device to device, Averaged current from OUT0 to
ΔIO(LC1) ±4%
(see Figure 10) OUT15, R(IREF) = 1920 (20 mA)(2) +0.4%
–2.7%
Constant sink current error Device to device, Averaged current from OUT0 to
ΔIO(LC2) ±4%
(see Figure 10) OUT15, R(IREF) = 480 (80 mA)(2) +2%
All output ON, VO= 1V, R(IREF) = 640 ±1 ±4 %/V
OUT0 to OUT15, VCC = 3 V to 5.5 V(3)
ΔIO(LC3) Line regulation (see Figure 10)All output ON, VO= 1V, R(IREF) = 320 ,±1 ±6 %/V
OUT0 to OUT15, VCC = 3 V to 5.5 V(3)
All output ON, VO= 1 V to 3 V, R(IREF) = 640 ,±2 ±6 %/V
OUT0 to OUT15(4)
Load regulation (see
ΔIO(LC4) Figure 10)All output ON, VO= 1 V to 3 V, R(IREF) = 320 ,±2 ±8 %/V
OUT0 to OUT15(4)
T(TEF) Thermal error flag threshold Junction temperature(5) 150 170 °C
V(LED) LED open detection threshold 0.3 0.4 V
Reference voltage
V(IREF) R(IREF) = 640 1.20 1.24 1.28 V
output
(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Test Parameter Equations.
(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Test
Parameter Equations. The ideal current is calculated by Equation 3 in Test Parameter Equations.
(3) The line regulation is calculated by Equation 4 in Test Parameter Equations.
(4) The load regulation is calculated by Equation 5 in Test Parameter Equations.
(5) Not tested. Specified by design
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6.6 Switching Characteristics
VCC = 3V to 5.5V, TA= -40°C to 85°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr0 SOUT 16
Rise time ns
tr1 OUTn, VCC = 5 V, TA= 60°C, DCn = 3 Fh 10 30
tf0 SOUT 16
Fall time ns
tf1 OUTn, VCC = 5 V, TA= 60°C, DCn = 3 Fh 10 30
tpd0 SCLK to SOUT (see Figure 11) 30 ns
tpd1 BLANK to OUT0 60 ns
tpd2 OUTn to XERR (see Figure 11) 1000 ns
Propagation delay time
tpd3 GSCLK to OUT0 (see Figure 11) 60 ns
tpd4 XLAT to IOUT (dot correction) (see Figure 11) 60 ns
tpd5 DCPRG to OUT0 (see Figure 11) 30 ns
tdOutput delay time OUTn to OUT(n+1) (see Figure 11) 20 30 ns
ton-err Output on-time error touton– Tgsclk (see Figure 11), GSn = 01h, GSCLK = 11 MHz 10 –50 –90 ns
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-8
-6
-4
-2
0
2
4
6
8
0 20 40 60 80
I -OutputCurrent-mA
O
Δ I -ConstantOutputCurrent-%
OLC
T =25 C,
V =5V
A
CC
°
0
1k
3k
4k
2k
T − Free-AirTemperature − C
A
o
0-20 20 100
PowerDissipationRate-mW
-40 80
6040
TLC5940PWP
PowerPADSoldered
TLC5940PWP
PowerPADUnsoldered
TLC5940RHB
TLC5940NT
100
1k
10k
I − OutputCurrent − mA
O
0 20 60 100
ReferenceResistor,R -
(IREF) W
40 80 120
7.68kΩ
1.92kΩ
0.96kΩ
0.64kΩ
0.38kΩ
0.32kΩ
0.48kΩ
TLC5940
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SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
6.7 Typical Characteristics
Figure 1. Reference Resistor vs Output Current Figure 2. Power Dissipation Rate vs Free-Air Temperature
Figure 3. Output Current vs Output Voltage Figure 4. Output Current vs Output Voltage
Figure 6. Constant Output Current, ΔIOLC
Figure 5. Constant Output Current, ΔIOLC vs Output Current
vs Ambient Temperature
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0
10
20
30
40
50
60
70
0 10 20 30 40 50 60 70
DotCorrectionData-dec
I -OutputCurrent-mA
O
T =-40 C
A
°
T =25 C
A
°
T =85 C
A
°
I =60mA,
V =5V
O
CC
0
20
40
60
80
100
120
140
0 10 20 30 40 50 60 70
DotCorrectionData-dec
I -OutputCurrent-mA
O
I =5mA
O
I =60mA
O
I =80mA
O
I =120mA
O
I =30mA
O
T =25 C,
V =5V
A
CC
°
TLC5940
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Typical Characteristics (continued)
Figure 7. Output Current Figure 8. Output Current
vs DOT Correction Linearity (ABS Value) vs DOT Correction Linearity (ABS Value)
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MW
VCC
INPUT
GND
400 W
INPUTEQUIVALENTCIRCUIT
(BLANK,XLAT,SCLK,SIN,GSCLK,DCPRG)
23 W
23
SOUT
GND
OUTPUTEQUIVALENTCIRCUIT(SOUT)
_
+
Amp
400 W
100 W
VCC
INPUT
GND
INPUTEQUIVALENTCIRCUIT(IREF)
XERR
GND
OUTPUTEQUIVALENTCIRCUIT(XERR)
23 W
INPUT
INPUT
GND
GND
INPUTEQUIVALENTCIRCUIT(VCC)
INPUTEQUIVALENTCIRCUIT(VPRG)
OUT
GND
OUTPUTEQUIVALENTCIRCUIT(OUT)
VCC
W
V(IREF)
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SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
7 Parameter Measurement Information
Resistor values are equivalent resistances, and they are not tested.
Figure 9. Input and Output Equivalent Circuits
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Testpoint
C =15pF
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Testpoint
R =51W
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C =15pF
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V =1V
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OUTn
V =1Vto3V
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OUTn
IREF
R470kΩ
(IREG)
Testpoint
V(IREF)
VCC
XERR
tpd3
I , I , I , I , I
O(LC) O(LC0) O(LC1) O(LC2) O(LC3)
D D D D
DIO(LC4)
=640W
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
Parameter Measurement Information (continued)
Figure 10. Parameter Measurement Circuits
7.1 Test Parameter Equations
(1)
(2)
(3)
(4)
(5)
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Product Folder Links: TLC5940
Delay
x0
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
Temperature
ErrorFlag
(TEF)
Max.OUTn
Current
Delay
x1
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
Delay
x15
6−BitDot
12−BitGrayscale
PWMControl
DCRegister
GSRegister
DCEEPROM
ConstantCurrent
Driver
LEDOpenDetection
OUT0
OUT1
OUT15
SOUT
SINSCLK
IREF
XERR
XLAT
GSCLK
BLANK
DCPRG
DCPRG
DCPRG
VPRG
VPRG
VPRG
GNDVCC
VPRG
Input
Shift
Register
Input
Shift
Register
VPRG 110
2312
191180
9590
116
5
VPRG
0
0
95
96
191
LEDOpen
Detection
(LOD)
5
9590
6 11
DCPRG
0
192
96
0
1
01 0
1
01
GSCounter CNT
CNT
CNT
CNT
96
96
Status
Information:
LOD,
TED,
DCDATA
192
0
191
1
0
0
1
VREF =1.24V
Correction
6−BitDot
Correction
6−BitDot
Correction
01
Blank
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
8 Detailed Description
8.1 Overview
The TLC5940 is a 16-channel constant current sink driver. Each channel has an individually-adjustable, 4096-
step, pulse width modulation (PWM), grayscale (GS) brightness control, and a 64-step dot correction brightness
control. GS data and DC data are input via a serial interface port. The dot correction data is stored in an
integrated EEPROM. The TLC5940 has a 120-mA current capability. The maximum current value of all channels
is determined by an external resistor. The TLC5940 has a LED open detection (LOD) function that indicates a
broken or disconnected LED at an output terminal and a thermal error flag (TEF) indicates an overtemperature
condition.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Serial Interface
The TLC5940 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal
shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT
signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT
signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the
programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although
new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale
data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing
grayscale data. Figure 11 shows the timing chart. More than two TLC5940s can be connected in series by
connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5940s is shown in Figure 12 and the timing chart is shown in Figure 13. The SOUT pin can also be
connected to the controller to receive status information from TLC5940 as shown in Figure 22.
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‘5‘ TEXAS INSTRUMENTS 4 C "W 3| \ w w w “4’“ 1%: +1: ,tJm—J‘LLUHHFUUUL I—V +}+ +1 1+ .-----. we
SIN SOUT
SIN(a) SOUT(b )
TLC5940(a)
GSCLK,
BLANK,
SIN SOUT
TLC5940(b)
SCLK,XLAT,
VPRG
DCPRG,
VPRG
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
196
DC
MSB DC
LSB
DC
MSB
1 192 193 1192 193 1
1 4096
tsu4
th4
twh3
1
GS1
MSB GS1
LSB
GS1
MSB GS2
MSB
GS2
LSB
GS2
MSB
SID2
MSB
SID2
MSB-1
SID1
MSB
SID1
MSB-1
SID1
LSB
GS3
MSB
- --
twh2
tsu2 tsu1 twh0
twl0
tsu0 th0
tpd0
tpd1
t +t
pd1 d
t +15xt
pd1 d
tpd3
td
15xtd
tpd2
t +t
pd3 d
tpd3
tpd4
twl1
twh1
DCDataInputMode GSDataInputMode
1stGSDataInputCycle 2ndGSDataInputCycle
1stGSDataOutputCycle 2ndGSDataOutputCycle
tsu3
th3
th2 th1
tsu5
Tgsclk
touton
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
Feature Description (continued)
Figure 11. Serial Data Input Timing Chart
Figure 12. Cascading Two TLC5940 Devices
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l TEXAS INSTRUMENTS _‘__‘ it, fl _ fl H :[m HIM legw HI firm—HIIJWflj—flfm Iiwwwmmw \IHfiH IH ............
VPRG
XLAT
SIN(a)
SCLK
SOUT(b)
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
1
192X2
DCb
MSB
DCa
LSB
DCb
MSB
1 384 385 1384 385 1
14096 1
GSb1
MSB
GSa1
LSB
GSb1
MSB
GSb2
MSB
GSa2
LSB
GSb2
MSB
SIDb2
MSB
SIDb2
MSB-1
SIDb1
MSB
SIDb1
MSB-1
SIDa1
LSB
GSb3
MSB
- --
192
96X2
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
Feature Description (continued)
Figure 13. Timing Chart for Two Cascaded TLC5940 Devices
8.3.2 Error Information Output
The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned
on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and
pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error
(see Figure 22).
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 1. XERR Truth Table
ERROR CONDITION ERROR INFORMATION SIGNALS
TEMPERATURE OUTn VOLTAGE TEF LOD BLANK XERR
TJ< T(TEF) Don't Care L X H
H
TJ> T(TEF) Don't Care H X L
OUTn > V(LED) L L H
TJ< T(TEF) OUTn < V(LED) L H L
L
OUTn > V(LED) H L L
TJ> T(TEF) OUTn < V(LED) H H L
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
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l TEXAS INSTRUMENTS
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
8.3.3 TEF: Thermal Error Flag
The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If
the junction temperature exceeds the threshold temperature (160°C typical), TEF becomes H and XERR pin
goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes
L and XERR pin becomes high impedance. TEF status can also be read out from the TLC5940 status register.
8.3.4 LOD: LED Open Detection
The TLC5940 has an LED-open detector that detects broken or disconnected LEDs. The LED open detector
pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the Status
Information Data is only active under the following open-LED conditions.
1. OUTn is on and the time tpd2 (1 μs typical) has passed.
2. The voltage of OUTn is < 0.3 V (typical)
The LOD status of each output can be also read out from the SOUT pin. See STATUS INFORMATION OUTPUT
section for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low
after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch the
LOD error into the Status Information Data for subsequent reading via the serial shift register.
8.3.5 Delay Between Outputs
The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current
driver block of the device (see the functional block diagram). The fixed-delay time is 20 ns (typical), OUT0 has no
delay, OUT1 has a 20-ns delay, and OUT2 has a 40-ns delay, etc. The maximum delay is 300 ns from OUT0 to
OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large
inrush currents which reduces the bypass capacitors when the outputs turn on.
8.3.6 Output Enable
All OUTn channels of the TLC5940 can be switched off with one signal. When BLANK is set high, all OUTn
channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When
BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high
again in less than 300 ns, all outputs programmed to turn on still turn on for either the programmed number of
grayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if all
outputs are programmed to turn on for 1 ms, but the BLANK signal is only low for 200 ns, all outputs still turn on
for 200 ns, even though some outputs are turning on after the BLANK signal has already gone high.
Table 2. BLANK Signal Truth Table
BLANK OUT0 - OUT15
LOW Normal condition
HIGH Disabled
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l TEXAS INSTRUMENTS
Imax
V(IREF)
R(IREF)
31.5
=×
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
8.3.7 Setting Maximum Channel Current
The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between
IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of
1.24 V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of
31.5. The maximum output current per channel can be calculated by Equation 6.
where
• V(IREF) = 1.24 V
• R(IREF) = User-selected external resistor. (6)
Imax must be set between 5 mA and 120 mA. The output current may be unstable if Imax is set lower than 5 mA.
Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dot
correction.
Figure 1 shows the maximum output current IOversus R(IREF). R(IREF) is the value of the resistor between IREF
terminal to GND, and IOis the constant output current of OUT0 to OUT15. A variable power supply may be
connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum
output current per channel is 31.5 times the current flowing out of the IREF pin.
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TLC5940
l TEXAS INSTRUMENTS no
DC0.0
0
DC1.0
6
DC15.0
90
DC15.5
95
DC0.5
5
DC14.5
89
MSB LSB
DCOUT15 DCOUT0
DCOUT14 − DCOUT2
IOUTn Imax
DCn
63
=×
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
8.4 Device Functional Modes
8.4.1 Operating Modes
The TLC5940 has operating modes depending on the signals DCPRG and VPRG. Table 3 shows the available
operating modes. The TPS5940 GS operating mode (see Figure 11) and shift register values are not defined
after power up. One solution to solve this is to set dot correction data after TLS5940 power-up and switch back
to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch
it while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register are
unknown just after power on. The DC and GS register values should be properly stored through the serial
interface before starting the operation.
Table 3. TLC5940 Operating Modes Truth Table
SIGNAL INPUT SHIFT REGISTER MODE DC VALUE
DCPRG VPRG
L EEPROM
GND 192 bit Grayscale PWM Mode
H DC Register
L EEPROM
VCC 96 bit Dot Correction Data Input Mode
H DC Register
L EEPROM
V(VPRG) X EEPROM Programming Mode
H Write dc register value to EEPROM. (Default
data: 3Fh)
8.4.2 Setting DOT Correction
The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently.
This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to
the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The
channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. Dot correction
for all channels must be entered at the same time. Equation 7 determines the output current for each output n.
where
• Imax = the maximum programmable output current for each output.
DCn = the programmed dot correction value for output n (DCn = 0 to 63).
n = 0 to 15 (7)
Figure 14 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC
15.5 in Figure 14 stands for the 5th most significant bit for output 15.
Figure 14. Dot Correction Data Packet Format
When VPRG is set to VCC, the TLC5940 enters the dot correction data input mode. The length of input shift
register becomes 96 bits. After all serial data are shifted in, the TLC5940 writes the data in the input shift register
to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a
level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed
while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal
does not need to be high to latch in new data. XLAT has setup time (tsu1) and hold time (th1) to SCLK as shown
in Figure 15.
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Product Folder Links: TLC5940
{L} TEXAS INSTRUMENTS X “““ xiim H SM ><><><>< il="">
DCPRG
OUT0
(Current)
tpd5 tpd5
OUT15
(Current)
VPRG
DCPRG
XLAT
SIN
SCLK
SOUT
196
DC
MSB
-
DC
MSB DC
LSB
VCC
V(PRG)
tsu6 tprog th5
tsu1
DCn
MSB
DCn
MSB−1
DCn
MSB−2
DCn
LSB+1
DCn
LSB
DCn
MSB
DCn+1
MSB
DCn+1
MSB−1
DCn
MSB−1
DCn
MSB−2
DCn−1
LSB
DCn−1
LSB+1
DCn−1
MSB
DCn−1
MSB−1
DCn−1
MSB−2
1 2 3 95 96 1 2
SCLK
SOUT
SIN
VPRG
XLAT
DCModeData
InputCyclen DCModeData
InputCyclen+1
VCC
twh0
twl0
DCn−1
LSB
twh2
th1
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
Figure 15. Dot Correction Data Input Timing Chart
The TLC5940 also has an EEPROM to store dot correction data. To store data from the dot correction register to
EEPROM, DCPRG is set to high after applying VPRG to the VPRG pin. Figure 16 shows the EEPROM
programming timings. The EEPROM has a default value of all 1 s.
Figure 16. EEPROM Programming Timing Chart
Figure 17. DCPRG and OUTn Timing Diagram
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Product Folder Links: TLC5940
l TEXAS INSTRUMENTS GSn 4095 00 u. u. u.
GS0.0
0
GS1.0
12
GS15.0
180
GS15.11
191
GS0.11
11
GS14.11
179
MSB LSB
GSOUT15 GSOUT0GSOUT14 − GSOUT2
Brightness in % GSn
4095 100
=×
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
8.4.3 Setting Grayscale
The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits
per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 8 determines
the brightness level for each output n.
where
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
n = 0 to 15
Grayscale data for all OUTn (8)
Figure 18 shows the grayscale data packet format which consists of 12 bits x 16 channels, totaling 192 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc.
Figure 18. Grayscale Data Packet Format
When VPRG is set to GND, the TLC5940 enters the grayscale data input mode. The device switches the input
shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into
the grayscale register (see Figure 11). New grayscale data immediately becomes valid at the rising edge of the
XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is
high.The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to
complete the grayscale update cycle. All GS data in the input shift register is replaced with status information
data (SID) after updated the grayscale register.
8.4.4 Status Information Output
The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG=GND).
After the XLAT signal latches the data into the GS register the input shift register data will be replaced with status
information data (SID) of the device (see Figure 18). LOD, TEF, and dot correction EEPROM data
(DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at SOUT pin. The status
information data packet is 192 bits wide. Bits 0-15 contain the LOD status of each channel. Bit 16 contains the
TEF status. If DCPRG is low, bits 24-119 contain the data of the dot-correction EEPROM. If DCPRG is high, bits
24-119 contain the data of the dot-correction register.The remaining bits are reserved. The complete status
information data packet is shown in Figure 19.
SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown Figure 20.
The next SCLK pulse, which will be the clock for receiving the SMB of the next grayscale data, transmits MSB-1
of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status flage becomes
active. The LOD status flag is an internal signal that pulls XERR pin down to low when the LOD status flag
becomes active. The delay time, tpd2 (1 μs maximum), is from the time of turning on the output sink current to
the time LOD status flage becomes valid. The timing for each channel's LOD status to become valid is shifted by
the 30-ns (maximum) channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD status is
valid; tpd3 + tpd2 = 60 ns + 1 μs. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 μs = 1.09 μs.
OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 μs, and so on. It takes 1.51 μs maximum (tpd3 + 15*td +
tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be > 1.51 μs (see Figure 20) to
ensure that all LOD data are valid.
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Product Folder Links: TLC5940
‘5‘ TEXAS INSTRUMENTS | | IL: | m IwIII IIIII « .H H
VPRG
XLAT
SIN
SCLK
SOUT
BLANK
GSCLK
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
1 192 193 1192
14096
GS1
MSB
GS1
LSB
GS1
MSB
GS2
MSB
GS2
LSB
GS2
MSB
SID1
MSB
SID1
MSB-1
SID1
LSB
- -
t +15xt +t
pd3 d pd2
tpd3
td
15xtd
tpd2
GSDataInputMode
1stGSDataInputCycle 2ndGSDataInputCycle
(1stGSDataOutputCycle)
tsuLOD
>tpd4+15xtd+tpd3
LOD15 DC15.5 DC0.0 X
XX
023
LODData DCValues Reserved
MSB LSB
119 120
24
TEF
LOD0 TEF
16
X
15 191
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
Figure 19. Status Information Data Packet Format
Figure 20. Readout Status Information Data (SID) Timing Chart
8.4.5 Grayscale PWM Operation
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low
increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following
rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of
each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values
are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and
completes the grayscale PWM cycle (see Figure 21). When the counter reaches a count of FFFh, the counter
stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets
the counter to zero.
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TLC5940
‘5‘ TEXAS INSTRUMENTS M W _L s u G Ilflj IIIIIIIIIIIIIIIIIII w .F n III +1 All w I _ w w rwl + + i ,xfi “NH“ \ 1+ w. «I I I+| II+| I ||II IMIII+ IIIIIM I
GSCLK
BLANK
GSPWM
Cyclen
1 2 3 1
GSPWM
Cyclen+1
OUT0
OUT1
OUT15
XERR
nxt d
tpd1
tpd1 +td
tpd1 +15xtd
tpd2
tpd3
twh1
twl1
twl1 tpd3
4096
th4 twh3
tpd3+nxtd
tsu4
(Current)
(Current)
(Current)
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
Figure 21. Grayscale PWM Cycle Timing Chart
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Product Folder Links: TLC5940
l TEXAS INSTRUMENTS
TLC5940
SIN SOUT
OUT0 OUT15
SCLK
GSCLK
XLAT
VPRG
BLANK
IREF
XERR
DCPRG
TLC5940
SIN SOUT
OUT0 OUT15
SCLK
GSCLK
XLAT
VPRG
BLANK
IREF
XERR
DCPRG
IC 0 IC n
7
SIN
SCLK
GSCLK
XLAT
BLANK
XERR
DCPRG
Controller
SOUT
VPRG_D
VPRG_OE
W_EEPROM
100 k
50 k
50 k
50 k
50 k
50 k
50 k
VPRG
100 nF
V(LED)
V(LED)
V(LED)
V(LED)
VCC
100 nF
V(22V)
V(22V)
VCC VCC
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The device is a 16-channel, constant sink current, LED driver. This device can be connected in series to drive
many LED lamps with only a few controller ports. Output current control data, dot correction data and PWM
control data can be written from the SIN input terminal.
9.2 Typical Application
Figure 22. Cascading Devices
9.2.1 Design Requirements
For this design example, use the input parameters shown in Table 4.
Table 4. Design Parameters
PARAMETERS VALUES
VCC input voltage range 3.0 V to 5.5 V
LED lamp (VLED) input voltage range >Maximum LED forward voltage (VF) + IC knee voltage
SIN, SCLK, XLAT, GSCLK, and BLANK voltage range Low level = GND, High level = VCC
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TLC5940
l TEXAS INSTRUMENTS H4 W OUTPUTZ N nouTPLITI I 2.oov w . 2.oov w 4.00115 imam/v I \ 4.2ov T I 23.00 as 20M ,5
f(GSCLK) 4096 f(update)
f(SCLK) 193 f(update) n
=
=
×
××
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
9.2.2 Detailed Design Procedure
9.2.2.1 Serial Data Transfer Rate
Figure 22 shows a cascading connection of nTLC5940 devices connected to a controller, building a basic
module of an LED display system. The maximum number of cascading TLC5940 devices depends on the
application system and is in the range of 40 devices. Equation 9 calculates the minimum frequency needed:
where
• f(GSCLK): minimum frequency needed for GSCLK
• f(SCLK): minimum frequency needed for SCLK and SIN
• f(update): update rate of whole cascading system
n: number cascaded of TLC5940 device (9)
9.2.2.2 Grayscale (GS) Data
There are a total of 16 sets of 12-bit GS data for the PWM control of each output. Select the GS data of each
LED lamp and write the GS data to the register following the signal timing.
9.2.3 Application Curve
Figure 23. Output Waveform with Different Grayscale PWM Data
24 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TLC5940
{L} TEXAS INSTRUMENTS
GND
BLANK
OUT11
OUT10
OUT15
OUT14
OUT13
OUT12
XLAT
SCLK
VCC
IREF
GSCLK
SOUT
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
1
2
6
8
10
12
13
3
4
5
7
9
11
14
27
25
23
21
20
18
17
28
26
24
22
19
GND VCC
Thermal
Pad
GND
Via to
Heatsink
Layer
15
16 OUT9
OUT8
XERR
DCPRG
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
10 Power Supply Recommendations
The VCC power supply voltage should be decoupled by placing a 0.1uF ceramic capacitor close to VCC pin and
GND plane. Depending on panel size, several electrolytic capacitors must be placed on board equally distributed
to get a well regulated LED supply voltage (VLED). VLED voltage ripple should be less than 5% of its nominal
value. Furthermore, the VLED should be set to the voltage calculated by equation:
VLED > VF + 0.4V ( 10mA constant current example) where Vf = maximum forward voltage of all LEDs.
11 Layout
11.1 Layout Guidelines
1. Place the decoupling capacitor near the VCC pin and GND plane.
2. Place the current programming resistor Riref close to IREF pin and IREFGND pin.
3. Route the GND pattern as widely as possible for large GND currents.
4. Routing wire between the LED cathode side and the device OUTn pin should be as short and straight as
possible to reduce wire inductance.
5. When several ICs are chained, symmetric placements are recommended.
11.2 Layout Example
Figure 24. Layout Recommendation
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TLC5940
l TEXAS INSTRUMENTS
P =V xI +
D CC CC V xI
OUT MAX x
DCn
63
xdPWM xN
(
()
)
TLC5940
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
www.ti.com
11.3 Power Dissipation Calculation
The device power dissipation must be below the power dissipation rating of the device package to ensure correct
operation. Equation 10 calculates the power dissipation of device.
where
• VCC: device supply voltage
• ICC: device supply current
• VOUT: TLC5940 OUTn voltage when driving LED current
• IMAX: LED current adjusted by R(IREF) Resistor
• DCn: maximum dot correction value for OUTn
N: number of OUTn driving LED at the same time
• dPWM: duty cycle defined by BLANK pin or GS PWM value (10)
26 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: TLC5940
l TEXAS INSTRUMENTS
TLC5940
www.ti.com
SLVS515D –DECEMBER 2004REVISED NOVEMBER 2015
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2004–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TLC5940
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940
TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940
TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940
TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940
TLC5940RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC
5940
TLC5940RHBRG4 ACTIVE VQFN RHB 32 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC
5940
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2015
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC5940 :
Enhanced Product: TLC5940-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “KO '«PT» Reel Diame|er AD Dimension des‘gned to accommodate the componem wwdlh E0 Dimension damned to eccemmodam the component \ength KO Dimenslun desgned to accommodate the componem thickness 7 w Overen with loe earner cape i p1 Pitch between successwe cavuy eemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pocket Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC5940RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Oct-2014
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC5940RHBR VQFN RHB 32 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Oct-2014
Pack Materials-Page 2
www.ti.com
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
TSSOP - 1.2 mm max height
TM
PowerPADPWP 28
SMALL OUTLINE PACKAGE
4.4 x 9.7, 0.65 mm pitch
4224765/A
MECHANICAL DATA M 1“ AST‘C WAN OUT N’ W T HH HHHHHHHH HHH? ‘ <71,’ p="" t—="" j="" ah="" hnec'="" d'vnensmrs="" c'e="" m="" m'hmekers="" a="" 5="" tm="" drawer="" ‘5="" subje»,="" ,0="" change="" wnrau:="" name,="" a="" body="" dimensmns="" do="" nut="" mm="" mm="" flcsh="" m="" aroms‘ms="" mam="" am="" an:="" drotrns'an="" she“="" no:="" exceed="" ms="" pe'="" side="" d="" ”‘3="" pomagc="" \s="" ccs‘qhcd="" to="" be="" so‘gl‘yqg="" to="" a="" “www="" pad="" on="" ihc="" boavd="" refer="" k)="" cchmm‘="" hhcf,="" ’owc'pad="" tr'eurtu="" erhuncec="" fucmge‘="" texts="" \nst'mreuts="" utemlue="" no="" s="" vauoz="" my="" wow-um)"="" veguvcmg="" vecovrmenced="" buuvd="" \uyull="" th5="" duumen:="" es="" uvu="" ub‘e="" u:="" wwwl="" r=""><‘vttu www="" uto'vv=""> See me accmonm hqure 'v the Jmmfl Dam Swee! ‘nr cams reqmdwg Me exaosed Mer'mfl pad features and mmensmns E, Fc‘s wwtmr JEDEC M0 153 NOTES, PawevPAD is a trademalk 0! Texas \nurumems. {I} TEXAS INSTRUMENTS www.ti.com
THERMAL PAD MECHANICAL DATA PWP (RmPDSOmGZB) F’owerPADTM SMALL PLASTIC OUTLlNE THERMAL lNFORMATlON This PowerPAD‘“ package incorporates an exposed thermal pad that is designed to be attached to a printed circuit board (PCB). The thermal pad must he soldered directly to the PCB After soldering. the PCB can be used as a heatsink. in addition, through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device. or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC). For additional information on the PowerPAD package and how to take advantage of its heat dissipating ab' ies. refer to Technical Brief, PowerPAD Thermally Enhanced Package. Texas instruments Literature No‘ SLMAOUZ and Application Brief PowerPAD Made Easy, Texas instruments Literature Na, SLMAOUIL Both documents are available at www.ti.corn. The exposed thermal pad dimensions for this package are shown in the following illustration fiiiiiiiiiiiiifi & gun rfi iiiiiiiiiiiiii Exposed Thermal Pod Dimensions 4205532, 33/A0 Ol /l 5 NOTE: A. All linear dimensions are in millimeters AExposed tie strao features may not be present inIrPAD is a tndomark olT-xas lnslfumlnts {I} TEXAS INSTRUMENTS www.ti.com
LAND PATTERN DATA PWP ( R—PDSO—GZB) PowerF’ADTM PLASTTC SMALL OUTLINE 11 “0.30 Example Board Layout Via pattern and copper pad size may vary depending on iuyollt constraints increasing copper area will enhance thermal pertormance stencil Openinghs Based on a stencil t ictness oi .i27mm (.ooeinch). Relerence table below ror other soider stencil thicknesses Ar Taxi.” 41 rZGXOfiS HHHHHHH l_l (See Note 0) *HH Vi: 28x0.25 4" i? THHHHHHHHT i.55 IV W (V W 5/ oJ-Tigi’w o o 0 2,40 3'40 5.60 (See Note E) Y 2.40 i \ X J ‘,__ M A” W ”W W I 6.17 i Musk Over Solder] L Copper Example Example \solder Mask Opening \ (See Note F) l aiie ii Pod Geometry 0.07 Ali Around / LS Example Solder Musk Defined Pad (See Note c. D) THHHHHHHHT 26x0,65 d Center Power Pad Solder Slencii Opening Stencil Thickness X Y 0.1mm 6.6 2.6 0.127rnm 6.17 2.4 0.152mm 5.8 2.3 0.178rnm 5.6 2.2 420760949”! 09/15 NOTES: All linear dimensions are in millimeters. rhis drawing is subiect to change without notice. Customers should place a note on the circuit board iabrication drawing not to alter the center solder mask derined pad. This package is designed to be soldered to a thermal pad on the board Rerer to rechnical Brier, PowerPud Thermnily Enhanced Package. Texas instruments Literature No. SLMAOOZ. SLMAOM. and also the Product Dam Sheets, For specific thermal inrormation. via requirements. and recommended board iayoui. These documents are available at wwwlicom , Publication ch—735i is recommended ror alternate designs. Laser cutting apertures with trapezoidal walls and also rounding corners will otler better paste release. Customers should contact their board assembly site ror stencil design recommendations. Example stencil design based on a 50% vaiurnelrl'c metal load solder paste. Refer to worms her other stencil Customers should contact their board rabrication site for solder musk tolerances between and around signal pads. ' TEXAS INSTRUMENTS wwwrticon
www.ti.com
GENERIC PACKAGE VIEW
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
VQFN - 1 mm max heightRHB 32
PLASTIC QUAD FLATPACK - NO LEAD
5 x 5, 0.5 mm pitch
4224745/A
MECHANICAL DATA NB (6 HC QUA \LA ‘ACK 0 LC/AJ ‘ 4r V ‘ , ‘ v LJULLVUUV ‘ , 3 *6 fl ‘ 3 C 3 C 3 7 W C, 3 C 3 C D ‘ 7673 D 767T V (‘ wppnflnn nmts A M \"veur d"v\e'vs\ons we w mmimetevs lwmenswoninq and Luwevurciuq per ASME v14 swam E ‘hs druwmq ‘5 54mm in c'vcnqe wmut whee C uFN (om Hatpuck NOrLeud] Package canhgwaucr, 1 The pucmge «mm pad my be so‘de’ed :0 We board :oy mmm 0rd mechanm‘ pe’fnrwance See Me uddmomfl ‘wgwe m the P'aduc: Dutc Sheet {0' deiafls regc'qu We exposed tre'r'm‘ :cc ‘eutu'es 27d d'me'vsmns FaHs wvhn JFDFC M07770 J5 TEXAS INSTRUMENTS wwwxi .com
THERMAL PAD MECHANICAL DATA RHB (S—PVQFN—NSZ) PLASTlC QUAD FLATPACK NO—LEAD THERMAL lNFORMATION This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB), After soldering. the PCB can be used as a heatsink. In addition. through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device. or alternatively. can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (lC). For information an the Quad Flatpack Na—Lead (OFN) package and its advantages. reler to Application Report. QFN/SON PCB Attachment. Texas instruments Literature Na. SLUA27i. This document is available at www.ti.com. The exposed thermal pad dimensions far this package are shown in the taiiawing illustration. PlN 1 lNDlCATOR C 0.3 32 U C- c c 4 C c c C Cm Exposed Thermal Pad 3.15i0.i0 nnnnnn\nn UUUUUUU 25 16 Tifliifliiil N 4} \l <—3.i§:t:0.io —=""> Bottom View Exposed Thermal Pad Dimensions 4206358e3/AC 05/i5 NOTE: A. All linear dimensions are in millimeters {y TEXAS INSTRUMENTS www.ti.com
LAND PATTERN DATA RHB (87PVQFN7N32) PLAST‘C QUAD FLATPACK N07LEAD Example stencil Design Example Board Layout 0,125(Thl'ck s)tenoil Note D 0,5 UJUIU FD L—’ b “”3! “ ‘“—°" , l G — UUUlUUUL, Note c ‘ l:> ROMS CI \ Cl C) Cl 3,15 (:I 03* I k l:) CI Cl ' J _3,i5 ‘ -———(:|— 4,i 5,8 __Q____'_____CI_4I15 5‘75 (:| l:) l I J CI \ (j :n is l 0,3 <2 ‘="" _‘="" |:)="" i="" ,="" cl="" “303mm="" j\="" w="" ‘l~="" a="" a,="" “0,5="" t,="" dd="" d-d="" dd="" 4="" 1="" '="" \\="" 0,254="" i?="" fii="" 5,8="" 4,="" \="" ——="" 4,15="" ——="" il="" ~\=""><7 5,75="" 4»="" l="" \="" (552="" printed="" solder="" coverage="" by="" area)="" {nan="" sold="" lin-ask="" deiined="" pad="" \\="" \‘="" \="" ,="" example="" we="" layout="" design="" exampie="" solder="" mask="" ooening="" \="" may="" vary="" depending="" on="" oonstrginls="" ‘="" (we="" e)="" \="" (note="" c,="" e)="" \.="" \'="" lodhl="" g="" 7="" 0.85="" \="" o="" +="" (1)="" r’="" ’="" \1="" 9x60,2—="" ‘="" i="" 1.0="" "l="" »="" whd="" geometry="" _="" "$-="" "4?"="" \'\="" 0,07="" j="" ’="" o="" i)="" c="" \ah="" around="" ,="" \="" i="" \\="" \="" \\""/="" 4207508—3/v="" 04/15="" notes:="" au="" all="" linear="" dimensions="" are="" in="" millimeters="" a.="" this="" drawing="" is="" suaiect="" to="" change="" without="" notice.="" a.="" this="" package="" is="" designed="" to="" be="" soldered="" to="" a="" lhermal="" add="" on="" the="" board,="" refer="" to="" application="" note.="" quad="" flat—pack="" packages,="" texas="" instruments="" literature="" no.="" stumi,="" and="" also="" the="" product="" data="" sheets="" iar="" specific="" thermal="" iniarmation,="" via="" requirements,="" and="" recommended="" board="" layout,="" these="" documents="" are="" available="" at="" awatlcam="">. Laser cutting apertures with trapezoidal walls and also rounding corners will oiier better paste release. Customers should canldct their board dssemaly site for stencil design recommendations, Reier to we 7525 lar stencil design considerations, Customers should contact lheir board idarlcdtion site lar recommended solder musk tolerances and via tentlng recommendations for any ldrger diameter vids aldeed in the thermal pod. it? TEXAS INSTRUMENTS www.li.cam
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