NCP361 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2012
February, 2019 Rev. 5
1Publication Order Number:
NCP361/D
NCP361, NCV361
USB Positive Overvoltage
Protection Controller with
Internal PMOS FET and
Overcurrent Protection
The NCP361 disconnects systems at its output when wrong VBUS
operating conditions are detected at its input. The system is positive
overvoltage protected up to +20 V.
Thanks to an integrated PMOS FET, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
The NCP361 is able to instantaneously disconnect the output from
the input if the input voltage exceeds the overvoltage threshold
(5.675 V). Thanks to an overcurrent protection, the integrated PMOS
is turning off when the charge current exceeds current limit (see
options in ordering information).
The NCP361 provides a negative going flag (FLAG) output, which
alerts the system that voltage, current or overtemperature faults have
occurred.
In addition, the device has ESDprotected input (15 kV Air) when
bypassed with a 1 mF or larger capacitor.
Features
Overvoltage Protection up to 20 V
Onchip PMOS Transistor
Overvoltage Lockout (OVLO)
Undervoltage Lockout (UVLO)
Overcurrent Protection
Alert FLAG Output
EN Enable Pin
Thermal Shutdown
Compliance to IEC6100042 (Level 4)
8 kV (Contact)
15 kV (Air)
ESD Ratings: Machine Model = B
ESD Ratings: Human Body Model = 2
UDFN6 2x2 mm and TSOP5 3x3 mm Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
This is a PbFree Device
Applications
USB Devices
Mobile Phones
Peripheral
Personal Digital Applications
MP3 Players
Set Top Boxes
6 PIN UDFN
CASE 517AB
PIN CONNECTIONS
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MARKING
DIAGRAMS
(Top View)
IN
GND
FLAGEN
OUT
OUT
xx M
G
1
1
2
3
6
5
4
1
5
1
xxx AYWG
G
xxx = Specific Device Code
M = Date Code
A = Assembly Location
Y = Year
W = Work Week
G= PbFree Package
(Note: Microdot may be in either location)
TSOP5
CASE 483
IN
GND
EN
OUT
FLAG
1
2
3
5
4
TSOP5
UDFN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
um 25 vst 0608 (:1 NCFEG! I EN m ( FLAG GND 2 I 'Il—H——< enable="" pm="" the="" devlce="" enlels="" ln="" shuloowh="" mode="" when="" ihls="" pln="" ls="" lled="" to="" a="" oulpul="" is="" dlsconnemed="" horn="" lhe="" input.="" to="" allow="" normal="" luncnonallty,="" lhe="" en="" m="" faull="" indlcallon="" pln,="" thls="" pln="" allows="" an="" exlemal="" syslem="" to="" detecl="" a="" laull="" on="" vbus="" pm,="" the="" pm="" goes="" low="" when="" lnput="" vollage="" exceeds="" ovlo="" mreshold="" slnce="" the="" fm:="" enable="" pm="" the="" devlce="" enlels="" ln="" shuloowh="" mode="" when="" ihls="" pln="" ls="" lled="" to="" a="" oulpul="" is="" dlsconnemed="" horn="" lhe="" input.="" to="" allow="" normal="" luncnonallty,="" lhe="" en="" m="" faull="" indlcallon="" pln,="" thls="" pln="" allows="" an="" exlemal="" syslem="" to="" detecl="" a="" laull="" on="" vbus="" pm,="" the="" pm="" goes="" low="" when="" lnput="" vollage="" exceeds="" ovlo="" mreshold="" slnce="" the="" fm:="">
NCP361, NCV361
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Figure 1. Typical Application Circuit (UDFN Pinout)
INPUT
FLAG
R1
1M
C1
1 mF 25 V X5R 0603
OUTPUT
1
2J2
FLAG_State
FLAG Power
IN
GND
OUT
NCP361
FLAG
C2
OUT
34
5
61
2
EN
1 mF 25 V X5R 0603
Figure 2. Functional Block Diagram
INPUT
LDO VREF
UVLO
OVLO
Soft Start
OUTPUT
FLAGV
(2 out pins in
UDFN package)
Thermal Shutdown
EN
PIN FUNCTION DESCRIPTION (UDFN Package)
Pin No. Name Type Description
1 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
2 GND POWER Ground
3 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
4, 5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to these pins.
The two OUT pins must be hardwired to common supply.
6 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to VCC must be added.
PIN FUNCTION DESCRIPTION (TSOP5 Package)
Pin No. Name Type Description
1 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
2 GND POWER Ground
3 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
4 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to VCC must be added.
5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin.
NOTE: Pin out provided for concept purpose only and might change in the final product
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MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage (IN to GND) Vminin 0.3 V
Minimum Voltage (All others to GND) Vmin 0.3 V
Maximum Voltage (IN to GND) Vmaxin 21 V
Maximum Voltage (All others to GND) Vmax 7.0 V
Maximum DC Current from Vin to Vout (PMOS) (Note 1) Imax 600 mA
Thermal Resistance, JunctiontoAir TSOP5
UDFN
RqJA 305
240
°C/W
Operating Ambient Temperature Range TA40 to +85 °C
Storage Temperature Range Tstg 65 to +150 °C
Junction Operating Temperature TJ150 °C
ESD Withstand Voltage (IEC 6100042)
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd 15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. With minimum PCB area. By decreasing RqJA, the current capability increases. See PCB recommendation page 9.
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
From EN www onsem com
NCP361, NCV361
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ELECTRICAL CHARACTERISTICS
(Min/Max limits values (40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.)
Characteristic Symbol Conditions Min Typ Max Unit
Input Voltage Range Vin 1.2 20 V
Undervoltage Lockout Threshold UVLO Vin falls down UVLO threshold 2.85 3.0 3.15 V
Uvervoltage Lockout Hysteresis UVLOhyst 50 70 90 mV
Overvoltage Lockout Threshold OVLO Vin rises up OVLO threshold 5.43 5.675 5.9 V
Overvoltage Lockout Hysteresis OVLOhyst 50 100 125 mV
Vin versus Vout Dopout Vdrop Vin = 5 V, I charge = 500 mA 150 200 mV
Overcurrent Limit Ilim Vin = 5 V 550 750 950 mA
Supply Quiescent Current Idd No Load, Vin = 5.25 V 20 35 mA
Standby Current Istd Vin = 5 V, EN = 1.2 V 26 37 mA
Zero Gate Voltage Drain Current IDSS VDS = 20 V, VGS = 0 V 0.08 mA
FLAG Output Low Voltage Volflag Vin > OVLO
Sink 1 mA on FLAG pin
400 mV
FLAG Leakage Current FLAGleak FLAG level = 5 V 5.0 nA
EN Voltage High Vih Vin from 3.3 V to 5.5 V 1.2 V
EN Voltage Low Vil Vin from 3.3 V to 5.5 V 0.55 V
EN Leakage Current ENleak EN = 5.5 V or GND 170 nA
TIMINGS
Start Up Delay ton From Vin > UVLO to Vout = 0.8xVin, See Fig 3 & 9 4.0 15 ms
FLAG going up Delay tstart From Vin > UVLO to FLAG = 1.2 V, See Fig 3 & 10 3.0 ms
Output Turn Off Time toff From Vin > OVLO to Vout 0.3 V, See Fig 4 & 11
Vin increasing from 5 V to 8 V at 3 V/ms.
No output capacitor.
0.7 1.5 ms
Alert Delay tstop From Vin > OVLO to FLAG 0.4 V, See Fig 4 & 12
Vin increasing from 5 V to 8 V at 3 V/ms
1.0 ms
Disable Time tdis From EN 0.4 to 1.2V to Vout 0.3 V, See Fig 5 & 13
Vin = 4.75 V.
No output capacitor.
3.0 ms
Thermal Shutdown Temperature Tsd 150 °C
Thermal Shutdown Hysteresis Tsdhyst 30 °C
Figure 5. Disable on W Figure 6. FLAG Response with W c/c
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1.2 V
FLAG
Vout
Vin UVLO
tstart
0.8 Vin
ton
<OVLO
Vin RDS(on) x I
FLAG
Vout
Vin
0.4 V
0.3 V
tstop
toff
OVLO
Vin RDSon x I
Figure 3. Start Up Sequence Figure 4. Shutdown on Over Voltage Detection
Figure 5. Disable on EN = 1 Figure 6. FLAG Response with EN = 1
1.2 V
FLAG
Vout
tdis
Vin RDS(on) x I
EN
0.3 V
1.2 V
FLAG
Vout
EN
tstart
UVLO
OVLO
Voltage, Current and Thermal Detection
IN OUT VIN > OVLO or VIN < UVLO
CONDITIONS
Figure 7.
Voltage, Current and Thermal Detection
IN OUT UVLO < VIN < OVLO
CONDITIONS
Figure 8.
TYPICAL OPERATING CHARACTERISTICS
— _ — ~_‘_M“ VL ,EE J” um W
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Figure 9. Start Up. Vin=Ch1, Vout=Ch2 Figure 10. FLAG Going Up Delay. Vin=Ch1,
FL:AG=Ch3
Figure 11. Output Turn Off time. Vin=Ch1,
Vout=Ch2
Figure 12. Alert Delay. Vout=Ch1, FLAG=Ch3
Figure 13. Disable Time. EN=Ch4, Vin=Ch1,
Vout=Ch2
Figure 14. Thermal Shutdown. Vin=Ch1,
Vout=Ch2, FLAG=Ch3
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TYPICAL OPERATING CHARACTERISTICS
Figure 15. RDS(on) vs. Temperature
(Load = 500 mA)
Figure 16. Output Short Circuit
Figure 17. Quiescent Current vs. Input Voltage Figure 18. Overcurrent Protection Threshold
vs. Temperature
Figure 19. Overcurrent Protection Threshold
vs. Input Voltage
RDS(on) (mW)
TEMPERATURE (°C)
0
50
100
150
200
250
300
0 50 100 15050
Vin = 3.6 V
Vin = 5 V
Vin, INPUT VOLTAGE (V)
SUPPLY QUIESCENT CURRENT (mA)
0
20
40
60
80
100
120
57911 171 3 13 15 19 21
720
740
760
780
800
820
840
860
TEMPERATURE (°C)
OVERCURRENT THRESHOLD (mA)
Vin = 5 V
05050 100 150
350
400
450
880
900
Vin = 3.25 V
140
160
180
INPUT VOLTAGE (V)
125°C
25°C
40°C
720
740
760
780
800
820
840
860
OVERCURRENT THRESHOLD (mA)
3.5 43 4.5 5.5
880
900
125°C
25°C
40°C
5
Vin = 3.6 V
Vin = 4.2 V
Vin = 5.25 V
25°C
0°C
85°C
Du to The FLAGV r llys‘crcsis FLAG EN m
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Operation
NCP361 provides overvoltage protection for positive
voltage, up to 20 V. A PMOS FET protects the systems
(i.e.: VBUS) connected on the Vout pin, against positive
overvoltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a builtin undervoltage lock out (UVLO)
circuit. During Vin positive going slope, the output remains
disconnected from input until Vin voltage is above 3.0 V
nominal. The FLAGV output is pulled to low as long as Vin
does not reach UVLO threshold. This circuit has a 70 mV
hysteresis to provide noise immunity to transient condition.
Figure 20. Output Characteristic vs. Vin
Vin (V)
20 V
OVLO
UVLO
0
Vout
OVLO
UVLO
0
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a builtin overvoltage lock out
(OVLO) circuit. During overvoltage condition (OVLO
exceeds), the output remains disabled and FLAG is tied
low, as long as the input voltage is higher than OVLO
hysteresis. This circuit has a 100 mV hysteresis to provide
noise immunity to transient conditions.
Overcurrent Protection (OCP)
The NCP361 integrates overcurrent protection to
prevent system/battery overload or defect. The current
limit threshold is internally set at 750 mA. This value can
be changed from 150 mA to 750 mA by a metal tweak,
please contact your ON Semiconductor representative for
availability. During current fault, the internal PMOS FET
is automatically turned off (5 ms) if the charge current
exceeds Ilim. NCP361 goes into turn on and turn off mode
as long as defect is present. The internal ton delay (4 ms
typical) allows limiting thermal dissipation. The Flag pin
goes to low level when an overcurrent fault appears. That
allows the microcontroller to count defect events and turns
off the PMOS with EN pin.
Figure 21. Overcurrent Event Example
Ilim
ton
Vout
Iload Overload Retrieve
normal
operation
FLAG Output
NCP361 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon as: 1.2 V < Vin < UVLO,
Vin > OVLO, Icharge > Ilimit, TJ > 150°C. When NCP361
recovers normal condition, FLAG is held high. The pin is
an open drain output, thus a pull up resistor (typically 1 MW
Minimum 10 kW) must be provided to VCC. FLAG pin is
an open drain output.
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal PMOS FET
The NCP361 includes an internal PMOS FET to protect
the systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
RDS(on), during normal operation, will create low losses on
Vout pin, characterized by Vin versus Vout dropout.
ESD Tests
The NCP361 fully supports the IEC6100042, level 4
(Input pin, 1 mF mounted on board). That means, in Air
condition, Vin has a ±15 kV ESD protected input. In
Contact condition, Vin has ±8 kV ESD protected input.
Please refer to Figure 22 to see the IEC6100042
electrostatic discharge waveform.
300 400 500 600 Copper heal spreader area (mm"2) www.0nsemi.com 9
NCP361, NCV361
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9
Figure 22.
PCB Recommendations
The NCP361 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
By increasing PCB area, the RqJA of the package can be
decreased, allowing higher charge current to fill the battery.
Taking into account that internal bondings (wires
between package and silicon) can handle up to 1 A (higher
than thermal capability), the following calculation shows
two different example of current capability, depending on
PCB area:
With 305°C/W (without PCB area), allowing DC
current is 500 mA
With 260°C/W (200 mm2), the charge DC current
allows with a 85°C ambient temperature is:
I = (TJ-TA)/(RqJA x RDSON)
I = 625 mA
In every case, we recommend to make thermal
measurement on final application board to make sure of the
final Thermal Resistance.
80
130
180
230
280
330
380
0 100 200 300 400 500 600 700
Copper heat spreader area (mm^2)
Theta JA (C/W)
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
% Delta DFN vs TSOP5
TSOP5 1.0 oz
TSOP5 2.0 oz
DFN 2x2.2 1.0 oz
DFN 2x2.2 2.0 oz
% Delta DFN vs TSOP5
Figure 23. Thermal Resistance of UDFN 2x2 and TSOP Packages as a Function of PCB Area and Thickness
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ORDERING INFORMATION
Device Marking Package Shipping
NCP361MUTBG AD UDFN6
(PbFree) 3000 / Tape & Reel
NCP361SNT1G ACD TSOP5
(PbFree) 3000 / Tape & Reel
NCV361SNT1G* VET TSOP5
(PbFree) 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements
SELECTION GUIDE
Part number is designated as follows:
a
NCP361xxxxxTxG
bc ed
Code Contents
aOvercurrent Threshold
: 750 mA
b Package
MU: UDFN
SN: TSOP5
cUVLO Typical Threshold
: 3.00 V
dOVLO Typical Threshold
: 5.675 V
eTape & Reel Type
B: = 3000
1: = 3000
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TSOP5
CASE 483
ISSUE N
DATE 12 AUG 2020
SCALE 2:1
1
5
XXX MG
G
GENERIC
MARKING DIAGRAM*
1
5
0.7
0.028
1.0
0.039
ǒmm
inchesǓ
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
XXX = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G= PbFree Package
1
5
XXXAYWG
G
Discrete/Logic
Analog
(Note: Microdot may be in either location)
XXX = Specific Device Code
M = Date Code
G= PbFree Package
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
DIM MIN MAX
MILLIMETERS
A
B
C0.90 1.10
D0.25 0.50
G0.95 BSC
H0.01 0.10
J0.10 0.26
K0.20 0.60
M0 10
S2.50 3.00
123
54 S
A
G
B
D
H
C
J
__
0.20
5X
CAB
T0.10
2X
2X T0.20
NOTE 5
CSEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
TOP VIEW
SIDE VIEW
A
B
END VIEW
1.35 1.65
2.85 3.15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98ARB18753C
DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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TSOP5
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NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE
TERMINALS.
5. TIE BARS MAY BE VISIBLE IN THIS VIEW AND ARE CONNECTED TO
THE THERMAL PAD.
SEATING
PLANE
0.10 C
A3
A
A1
0.10 C
UDFN6 2x2, 0.65P
CASE 517AB
ISSUE C
DATE 10 APR 2013
SCALE 4:1
DIM
A
MIN MAX
MILLIMETERS
0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b0.25 0.35
D2.00 BSC
D2 1.50 1.70
0.80 1.00
E2.00 BSC
E2
e0.65 BSC
L
--- 0.15
L1
PIN ONE
REFERENCE
0.08 C
0.10 C
6X
L
e
E2
b
3
66X
1
4
D2
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
XX = Specific Device Code
M = Date Code
G= PbFree Package
XXMG
G
BOTTOM VIEW
0.25 0.35
L1
DETAIL A
L
ALTERNATE TERMINAL
CONSTRUCTIONS
L
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.65
0.47
6X
DIMENSIONS: MILLIMETERS
0.40
1.70
PITCH
0.95
6X
1
PACKAGE
OUTLINE
RECOMMENDED
TOP VIEW
SIDE VIEW
DETAIL B
NOTE 4
DETAIL A
END VIEW
A
M
0.10 BC
M
0.05 C
D
E
A B
NOTE 5
C
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
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DOCUMENT NUMBER:
DESCRIPTION:
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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UDFN6 2X2, 0.65P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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www.onsemi.com
1
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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
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