ESD7L5.0DT5G Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2012
November, 2017 Rev. 7
1Publication Order Number:
ESD7L/D
ESD7L, SESD7L
ESD Protection Diode
UltraLow Capacitance
The ESD7L Series is designed to protect voltage sensitive
components from damage due to ESD in applications that require ultra
low capacitance to preserve signal integrity. Excellent clamping
capability, low leakage and fast response time are combined with an
ultra low diode capacitance of 0.5 pF to provide best in class
protection from IC damage due to ESD. The ultra small SOT723
package is ideal for designs where board space is at a premium. The
ESD7L Series can be used to protect two unidirectional lines or one
bidirectional line. When used to protect one bidirectional line, the
effective capacitance is 0.25 pF. Because of its low capacitance, it is
well suited for protecting high frequency signal lines such as USB2.0
high speed and antenna line applications.
Specification Features:
Low Capacitance 0.5 pF Typical
Low Clamping Voltage
Small Body Outline Dimensions:
0.047” x 0.047” (1.20 mm x 1.20 mm)
Low Body Height: 0.020 (0.5 mm)
Standoff Voltage: 5 V
Low Leakage
Response Time is Typically < 1.0 ns
IEC6100042 Level 4 ESD Protection
S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AECQ101 Qualified and
PPAP Capable
This is a PbFree Device
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic
Epoxy Meets UL 94 V0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
Device Meets MSL 1 Requirements
MAXIMUM RATINGS
Rating Symbol Value Unit
IEC 6100042 (ESD) Contact ±10 kV
Total Power Dissipation on FR5 Board
(Note 1) @ TA = 25°C
°PD°150 mW
Storage Temperature Range Tstg 55 to +150 °C
Junction Temperature Range TJ55 to +150 °C
Lead Solder Temperature Maximum
(10 Second Duration)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR5 = 1.0 x 0.75 x 0.62 in.
Device Package Shipping
ORDERING INFORMATION
ESD7L5.0DT5G SOT723
(PbFree)
8000/Tape & Reel
MARKING DIAGRAM
See specific marking information in the device marking
column of the Electrical Characteristics tables starting on
page 2 of this data sheet.
DEVICE MARKING INFORMATION
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
www.onsemi.com
SOT723
CASE 631AA
L6 = Specific Device Code
M = Date Code
L6 M
1
1
3
2
PIN 1. CATHODE
2. CATHODE
3. ANODE
SESD7L5.0DT5G SOT723
(PbFree)
8000/Tape & Reel
See Application Note AND8308/D for further
description of survivability specs.
SCALE 4:1
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ESD7L, SESD7L
www.onsemi.com
2
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VCClamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IRMaximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
ITTest Current
IFForward Current
VFForward Voltage @ IF
Ppk Peak Power Dissipation
CCapacitance @ VR = 0 and f = 1.0 MHz UniDirectional
IPP
IF
V
I
IR
IT
VRWM
VCVBR
VF
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, VF = 1.1 V Max. @ IF = 10 mA for all types)
Device*
Device
Marking
VRWM
(V)
IR (mA)
@ VRWM
VBR (V)
@ IT
(Note 2) IT
C (pF),
unidirectional
(Note 3)
C (pF),
bidirectional
(Note 4)
VC (V)
@ IPP = 1 A
(Note 5) VC
Max Max Min mA Typ Max Typ Max Max
Per
IEC61000
42
(Note 6)
ESD7L5.0DT5G L6 5.0 1.0 5.4 1.0 0.5 0.9 0.25 0.45 10.4 Figures 1
and 2
* Include S-prefix devices where applicable.
2. VBR is measured with a pulse test current IT at an ambient temperature of 25°C.
3. Unidirectional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 3; pin 2 to pin 3).
4. Bidirectional capacitance at f = 1 MHz, VR = 0 V, TA = 25°C (pin1 to pin 2).
5. Surge current waveform per Figure 5.
6. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV contact per IEC 6100042
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV contact per IEC 6100042
www.cnsemi.com
ESD7L, SESD7L
www.onsemi.com
3
IEC 6100042 Spec.
Level
Test Volt-
age (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
Ipeak
90%
10%
IEC6100042 Waveform
100%
I @ 30 ns
I @ 60 ns
tP = 0.7 ns to 1 ns
Figure 3. IEC6100042 Spec
Figure 4. Diagram of ESD Test Setup
50 W
Cable
Device
Under
Test Oscilloscope
ESD Gun
50 W
The following is taken from Application Note
AND8308/D Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
Figure 5. 8 X 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
tP
tr
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE IRSM @ 8 ms
HALF VALUE IRSM/2 @ 20 ms
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4
PACKAGE DIMENSIONS
SOT723
CASE 631AA
ISSUE D
DIM MIN NOM MAX
MILLIMETERS
A0.45 0.50 0.55
b0.15 0.21 0.27
b1 0.25 0.31 0.37
C0.07 0.12 0.17
D1.15 1.20 1.25
E0.75 0.80 0.85
e0.40 BSC
H1.15 1.20 1.25
L
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
D
b1
E
b
e
A
L
C
H
Y
X
X0.08 Y
2X
E
12
3
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
L2 0.15 0.20 0.25
0.29 REF
3X
L2
3X
1
2X
TOP VIEW
BOTTOM VIEW
SIDE VIEW
RECOMMENDED
DIMENSIONS: MILLIMETERS
0.40
1.50
2X
PACKAGE
OUTLINE
0.27
2X
0.52
3X 0.36
PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81358171050
ESD7L/D
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