MAX32080E-84E Datasheet by Maxim Integrated

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MAX328OEIMAX3281EI :15kV ESD-Protected 52Mbps, 3V to 5.5V, maxim Integrated ,,
Pin Configurations appear at end of data sheet.
General Description
The MAX3280E/MAX3281E/MAX3283E/MAX3284E
are single receivers designed for RS-485 and RS-422
communication. These devices guarantee data rates
up to 52Mbps, even with a 3V power supply. Excellent
propagation delay (15ns max) and package-to-package
skew time (8ns max) make these devices ideal for
multidrop clock distribution applications.
The MAX3280E/MAX3281E/MAX3283E/MAX3284E
have true fail-safe circuitry, which guarantees a logic-high
receiver output when the receiver inputs are opened
or shorted. The receiver output will be a logic high if
all transmitters on a terminated bus are disabled (high
impedance). These devices feature 1/4-unit-load receiver
input impedance, allowing up to 128 receivers on the
same bus.
The MAX3280E is a single receiver available in a 5-pin
SOT23 package. The MAX3281E/MAX3283E single
receivers have a receiver enable (EN or EN) function and
are offered in a 6-pin SOT23 package. The MAX3284E
features a voltage logic pin that allows compatibility with
low-voltage logic levels, as in digital FPGAs/ASICs. On
the MAX3284E, the voltage threshold for a logic high
is user-defined by setting VL in the range from 1.65V to
VCC. The MAX3284E is also offered in a 6-pin SOT23
package.
Applications
Clock Distribution
Telecom Racks
Base Stations
Industrial Control
Local Area Networks
Automotive
Benefits and Features
ESD Protection:
±15kV Human Body Model
±6kV IEC 1000-4-2, Contact Discharge
±12kV IEC 1000-4-2, Air-Gap Discharge
Guaranteed 52Mbps Data Rate
Guaranteed 15ns Receiver Propagation Delay
Guaranteed 2ns Receiver Skew
Guaranteed 8ns Package-to-Package Skew Time
VL Pin for Connection to FPGAs/ASICs
Allow Up to 128 Transceivers on the Bus
(1/4-unit-load)
Tiny SOT23 Package
True Fail-Safe Receiver
-7V to +12V Common-Mode Range
3V to 5.5V Power-Supply Range
Enable (High and Low) Pins for Redundant Operation
Three-State Output Stage (MAX3281E/MAX3283E)
Thermal Protection Against Output Short Circuit
AEC-Q100 (MAX3280EAUK/V+ Only)
19-2320; Rev 7; 1/19
Click here for production status of specific part numbers.
Note 1: MAX3284E data rate is dependent on VL.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
/V denotes an automotive qualified part.
Selector Guide
Ordering Information
PART VL ENABLE DATA RATE PACKAGE
MAX3280E 52Mbps 5-Pin SOT23
MAX3281E Active High 52Mbps 6-Pin SOT23
MAX3283E Active Low 52Mbps 6-Pin SOT23
MAX3284E 52Mbps (Note 1) 6-Pin SOT23
PART TEMP RANGE PIN-
PACKAGE
TOP
MARK
MAX3280EAUK+T -40°C to +125°C 5 SOT23 +ADVM
MAX3280EAUK/V+T -40°C to +125°C 5 SOT23 +AFME
MAX3281EAUT+T -40°C to +125°C 6 SOT23 +ABAT
MAX3283EAUT+T -40°C to +125°C 6 SOT23 +ABAU
MAX3284EAUT+T -40°C to +125°C 6 SOT23 +ABAV
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
Packag SOT23-5
(All Voltages Referenced to GND)
Supply Voltage (VCC) ..............................................-0.3V to +6V
Control Input Voltage (EN, EN) ...............................-0.3V to +6V
VL Input Voltage ......................................................-0.3V to +6V
Receiver Input Voltage (A, B) ............................. -7.5V to +12.5V
Receiver Output Voltage (RO) ................. -0.3V to (VCC + 0.3V)
Receiver Output Voltage
(RO) (MAX3284E) ................................... -0.3V to (VL + 0.3V)
Receiver Output Short-Circuit Current ......................Continuous
Continuous Power Dissipation (TA = +70°C)
5-Pin SOT23 (derate 3.9mW/°C above +70°C) .....312.60mW
6-Pin SOT23 (derate 8.7mW/°C above +70°C) ..........696mW
Operating Temperature Range
MAX328_EA__ ............................................. -40°C to +125°C
Storage Temperature Range ............................ -65°C to +150°C
Junction Temperature ...................................................... +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ....................................... +260°C
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package Information
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
SOT23-6
PACKAGE CODE U6+1
Outline Number 21-0058
Land Pattern Number 90-0175
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) N/A
Junction to Case (θJC) 80°C/W
Thermal Resistance, Multi-Layer Board:
Junction to Ambient (θJA) 115°C/W
Junction to Case (θJC) 80°C/W
SOT23-5
PACKAGE CODE U5+2, U5+2A
Outline Number 21-0057
Land Pattern Number 90-0174
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) 324.30°C/W
Junction to Case (θJC) 82°C/W
Thermal Resistance, Multi-Layer Board:
Junction to Ambient (θJA) 255.90°C/W
Junction to Case (θJC) 81°C/W
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
(VCC = 3V to 5.5V, VL = VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 5V and TA = +25°C.) (Notes 2, 3)
Electrical Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 3.0 5.5 V
Supply Current ICC No load 9 15 mA
VL Input Range VLMAX3284E 1.65 VCC V
VL Supply Current ILNo load (MAX3284E) 10 µA
RECEIVER
Input Current (A and B) IA, B VCC = VGND or 5.5V VIN = +12V 250 µA
VIN = -7V -200
Receiver Differential Threshold
Voltage VTH -7V ≤ VCM ≤ +12V (Note 4) -200 -125 -50 mV
Receiver Input Hysteresis ∆VTH VA + VB = 0V 25 mV
Receiver Enable Input Low VENIL MAX3281E, MAX3283E only 0.4 V
Receiver Enable Input High VENIH MAX3281E, MAX3283E only 2 V
Receiver Enable Input Leakage ILEAK MAX3281E, MAX3283E only ±10 µA
Receiver Output High Voltage VOH
MAX3280E/MAX3281E/MAX3283E,
IOH = -4mA, RO high VCC - 0.4
V
MAX3284E, IOH = -1mA, 1.65V ≤ VL ≤ VCC,
RO high VL - 0.4
Receiver Output Low Voltage VOL
MAX3280E/MAX3281E/MAX3283E,
IOL = 4mA, RO low 0.4
V
MAX3284E, IOL = 1mA, 1.65V ≤ VL ≤ VCC,
RO low 0.4
Three-State Output Current at
Receiver IOZR 0 ≤ VO ≤ VCC, RO = high impedance ±5 µA
Receiver Input Resistance RIN -7V ≤ VCM ≤ +12V (Note 5) 48 kW
Receiver Output Short-Circuit
Current IOSR 0 ≤ VRO ≤ VCC ±130 mA
ESD PROTECTION
ESD Protection (A, B)
Human Body Model ±15
kVIEC1000-4-2 (Air-Gap Discharge) ±12
IEC1000-4-2 (Contact Discharge) ±6
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
\\ \
Note 2: Parameters are 100% production tested at +25°C, limits over temperature are guaranteed by design.
Note 3: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to device
ground, unless otherwise noted.
Note 4: VCM is the common-mode input voltage. VID is the differential input voltage.
Note 5: Not production tested. Guaranteed by design.
Note 6: See Table 2 for MAX3284E data rates with VL < VCC.
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
(VCC = 3V to 5.5V, VL = VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 5V and TA = +25°C.) (Notes 2, 3)
Typical Operating Characteristics
Switching Characteristics
2.5
3.0
4.0
3.5
4.5
5.0
-50 0-25 25 50 75 100 125
RECEIVER OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
MAX3280/1/3/4E toc03
TEMPERATURE (°C)
RECEIVER OUTPUT HIGH VOLTAGE (V)
VCC = 5V
VCC = 3.3V
VA = 1V, B = GND, IOH = -4mA
0
1
3
2
4
5
-50 -30-40 -20 -10 0
RECEIVER OUTPUT HIGH VOLTAGE
vs. OUTPUT CURRENT
MAX3280/1/3/4E toc02
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
VCC = 3.3V
VCC = 5V
0
1
3
2
4
5
0 2010 30 40 50 60
RECEIVER OUTPUT LOW VOLTAGE
vs. OUTPUT CURRENT
MAX3280/1/3/4E toc01
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
VCC = 3.3V
VCC = 5V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Maximum Data Rate fMAX CL = 15pF (Notes 5, 6) 52 Mbps
Receiver Propagation Delay tPLH Figure 1, CL = 15pF, VID = 2V, VCM = 0V 7 15 ns
tPHL Figure 1, CL = 15pF, VID = 2V, VCM = 0V 8 15
Receiver Output |tPLH - tPHL| tPSKEW Figure 1, CL = 15pF, TA = +25°C 2 ns
Device-to-Device Propagation
Delay Matching
Same power supply, maximum temperature
difference between devices = +30°C
(Note 5)
8 ns
ENABLE/DISABLE TIME FOR MAX3281E/MAX3283E
Receiver Enable to Output Low tPRZL Figure 2, CL = 15pF 500 ns
Receiver Enable to Output High tPRZH Figure 2, CL = 15pF 500 ns
Receiver Disable Time from Low tPRLZ Figure 2, CL = 15pF 500 ns
Receiver Disable Time from High tPRHZ Figure 2, CL = 15pF 500 ns
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
WWW a // //3 / WW // // Wm // 3 3
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
0.001
0.01
0.1
1
10
VL SUPPLY CURRENT
vs. TEMPERATURE
MAX3280/1/3/4 toc10
TEMPERATURE (°C)
VL
SUPPLY CURRENT (mA)
-50 25 50-25 0 75 100 125
VCC = VL = 5V
DATA RATE = 52Mbps VCC = VL = 3.3V
DATA RATE = 52Mbps
VCC = VL = 5V
DATA RATE = 100kbps
VCC = VL = 3.3V
DATA RATE = 100kbps
0
2
6
4
8
10
SUPPLY CURRENT vs. DATA RATE
MAX3280/1/3/4E toc09
DATA RATE (kbps)
SUPPLY CURRENT (mA)
10 1000100 10,000 100,000
ICC, VCC = VL = 5V
ICC, VCC = VL = 3.3V
IL, VCC = VL = 5V
IL, VCC = VL = 3.3V
60
50
40
30
20
1.5 3.52.5 4.5 5.5
MAX3284E MAXIMUM DATA RATE
vs. VOLTAGE LOGIC LEVEL
MAX3280/1/3/4E toc08
VOLTAGE LOGIC LEVEL (V)
DATA RATE (Mbps)
5
6
7
8
9
SUPPLY CURRENT vs. TEMPERATURE
MAX3280/1/3/4E toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
-50 25 50-25 0 75 100 125
VCC = 5V
VCC = 3.3V
6
7
8
9
10
-50 0-25 25 50 75 100 125
RECEIVER PROPAGATION DELAY (tPHL)
vs. TEMPERATURE
MAX3280/1/3/4E toc06
TEMPERATURE (°C)
tPHL (ns)
VCC = 5V
VCC = 3.3V
4
5
7
6
8
9
-50 0-25 25 50 75 100 125
RECEIVER PROPAGATION DELAY (tPLH)
vs. TEMPERATURE
MAX3280/1/3/4E toc05
TEMPERATURE (°C)
tPLH (ns)
VCC = 5V
VCC = 3.3V
0
50
100
150
200
-50 0-25 25 50 75 100 125
RECEIVER OUTPUT LOW VOLTAGE
vs. TEMPERATURE
MAX3280/1/3/4E toc04
TEMPERATURE (°C)
RECEIVER OUTPUT LOW VOLTAGE (mV)
VCC = 5V
VCC = 3.3V
A = GND, VB = 1V, IOL = 4mA
Maxim Integrated
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
Detailed Description
The MAX3280E/MAX3281E/MAX3283E/MAX3284E are
single, true fail-safe receivers designed to operate at data
rates up to 52Mbps. The fail-safe architecture guarantees
a high output signal if both input terminals are open or
shorted together. See the True Fail-Safe section. This
feature assures a stable and predictable output logic state
with any transmitter driving the line. These receivers func-
tion with a 3.3V or 5V supply voltage and feature excellent
propagation delay times (15ns).
The MAX3280E is a single receiver available in a 5-pin
SOT23 package. The MAX3281E (EN, active high) and
MAX3283E (EN, active low) are single receivers that
also contain an enable pin. Both the MAX3281E and
MAX3283E are available in a 6-pin SOT23 package. The
MAX3284E is a single receiver that contains a VL pin,
which allows communication with low-level logic included
in digital FPGAs. The MAX3284E is available in a 6-pin
SOT23 package.
The MAX3284E’s low-level logic application allows users
to set the logic levels. A logic high level of 1.65V will limit
the maximum data rate to 20Mbps.
±15kV ESD Protection
ESD-protection structures are incorporated on the
receiver input pins to protect against ESD encountered
during handling and assembly. The MAX3280E/
MAX3281E/MAX3283E/MAX3284E receiver inputs (A,
B) have extra protection against static electricity found
in normal operation. Maxim’s engineers developed
state-of-the-art structures to protect these pins against
±15kV ESD without damage. After an ESD event, this
family of parts continues working without latchup.
ESD protection can be tested in several ways. The
receiver inputs are characterized for protection to the
following:
±15kV using the Human Body Model
±6kV using the Contact Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
±12kV using the Air-Gap Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents test
setup, methodology, and results.
Human Body Model
Figure 3a shows the Human Body Model, and Figure
3b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the device through a 1.5kW
resistor.
IEC 1000-4-2
Since January 1996, all equipment manufactured
and/or sold in the European community has been
required to meet the stringent IEC 1000-4-2 specifica-
tion. The IEC 1000-4-2 standard covers ESD test-
ing and performance of finished equipment; it does
not specifically refer to integrated circuits. The
MAX3280E/MAX3281E/MAX3283E/MAX3284E help
Pin Description
PIN NAME FUNCTION
MAX3280E MAX3281E MAX3283E MAX3284E
1 1 1 1 VCC Positive Supply: 3V ≤ VCC ≤ 5.5V. Bypass with a 0.1µF
capacitor to GND.
2 2 2 2 GND Ground
3 3 3 3 RO Receiver Output. RO will be high if (VA - VB) ≥ -50mV. RO will
be low if (VA - VB) ≤ -200mV.
4 4 4 4 B Inverting Receiver Input
5 EN Receiver Output Enable. Drive EN low to enable RO. When
EN is high, RO is high impedance.
5 EN Receiver Output Enable. Drive EN high to enable RO. When
EN is low, RO is high impedance.
5 VL
Low-Voltage Logic-Level Supply Voltage. VL is a user-defined
voltage, ranging from 1.65V to VCC. RO output high is pulled
up to VL. Bypass with a 0.1µF capacitor to GND.
5 6 6 6 A Noninverting Receiver Input
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
users design equipment that meets Level 3 of IEC 1000-
4-2, without additional ESD-protection components.
The main difference between tests done using the Human
Body Model and IEC 1000-4-2 is higher peak current
in IEC 1000-4-2. Because series resistance is lower in
the IEC 1000-4-2 ESD test model (Figure 4a), the ESD-
withstand voltage measured to this standard is generally
lower than that measured using the Human Body Model.
Figure 4b shows the current waveform for the ±8kV IEC
1000-4-2 Level 4 ESD Contact Discharge test. The Air-
Gap test involves approaching the device with a charger
probe. The Contact Discharge method connects the
probe to the device before the probe is energized.
Machine Model
The Machine Model for ESD testing uses a 200pF stor-
age capacitor and zero-discharge resistance. It mimics
the stress caused by handling during manufacturing and
assembly. All pins (not just the RS-485 inputs) require this
protection during manufacturing. Therefore, the Machine
Model is less relevant to the I/O ports than are the Human
Body Model and IEC 1000-4-2.
True Fail-Safe
The MAX3280E/MAX3281E/MAX3283E/MAX3284E guar-
antee a logic-high receiver output when the receiver inputs
are shorted or open, or when they are connected to a
terminated transmission line with all drivers disabled. This
guaranteed logic high is achieved by setting the receiver
threshold between -50mV and -200mV. If the differential
receiver input voltage (VA - VB) is greater than or equal to
-50mV, RO is logic high. If (VA - VB) is less than or equal
to -200mV, RO is logic low.
In the case of a terminated bus with all transmitters dis-
abled, the receiver’s differential input voltage is pulled to
ground by the termination. This results in a logic high with
a 50mV minimum noise margin. Unlike previous fail-safe
devices, the -50mV to -200mV threshold complies with
the ±200mV EIA/TIA-485 standard.
Receiver Enable
(MAX3281E and MAX3283E only)
The MAX3281E and MAX3283E feature a receiver out-
put enable (EN, MAX3281E or EN, MAX3283E) input
that controls the receiver. The MAX3281E receiver
enable (EN) pin is active high, meaning the receiver
outputs are active when EN is high. The MAX3283E
receiver enable (EN) pin is active low. Receiver outputs
are high impedance when the MAX3281E’s EN pin is low
and when the MAX3283E’s EN pin is high.
Low-Voltage Logic Levels
(MAX3284E only)
An increasing number of applications now operate at
low-voltage logic levels. To enable compatibility with
these low-voltage logic level applications, such as digital
FPGAs, the MAX3284E VL pin is a user-defined supply
voltage that designates the voltage threshold for a logic
high.
At lower VL voltages, the data rate will also be lower.
A logic-high level of 1.65V will receive data at 20Mbps.
Table 2 gives data rates at various voltages at VL.
Applications Information
Propagation Delay Matching
The MAX3280E/MAX3281E/MAX3283E/MAX3284E (VCC
= VL) exhibit propagation delays that are closely matched
from one device to another, even between devices from
different production lots. This feature allows multiple data
lines to receive data and clock signals with minimal skew
with respect to each other. Figure 5 shows the typical
propagation delays. Small receiver skew times, the differ-
ence between the low-to-high and high-to-low propagation
delay, help maintain a symmetrical ratio (50% duty cycle).
The receiver skew time | tPLH - tPHL | is under 2ns for
either a 3.3V supply or a 5V supply.
Multidrop Clock Distribution
Low package-to-package skew (8ns max) makes the
MAX3280E/MAX3281E/MAX3283E/MAX3284E
(VCC = VL) ideal for multidrop clock distribution. When
distributing a clock signal to multiple circuits over long
transmission lines, receivers in separate locations, and
possibly at two different temperatures, would ideally
Table 1. MAX3281E/MAX3283E Enable
Table
Table 2. MAX3284E Data Rate Table
PART ENABLE = HIGH ENABLE = LOW
MAX3281E Active High Z
MAX3283E High Z Active
VCC = 3V TO 5.5V
VLMAXIMUM DATA RATE
1.65V 20Mbps
2.2V 33Mbps
≥3.3V 52Mbps
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
w fin fl fi Q
provide the same clock to their respective circuits.
Thus, minimal package-to-package skew is critical. The
skew must be kept well below the period of the clock
signal to ensure that all of the circuits on the network
are synchronized.
128 Receivers on the Bus
The standard RS-485 input impedance is 12kW (one-
unit load). The standard RS-485 transmitter can drive
32 unit loads. The MAX3280E/MAX3281E/MAX3283E/
MAX3284E present a 1/4-unit-load input impedance
(48kW), which allows up to 128 receivers on the bus.
Any combination of these RS-485 receivers with a total
of 32 unit loads can be connected to the same bus.
Thermal Protection
The MAX3280E/MAX3281E/MAX3283E/MAX3284E fea-
ture thermal protection. Thermal protection sets the out-
put stage in high-impedance mode when a short circuit
occurs at the output, limiting both the power dissipation
and temperature. The thermal temperature threshold is
+165°C, with a hysteresis of 20°C.
Figure 2. MAX3281E/MAX3283E Receiver Enable/Disable Timing
Figure 1. Receiver Propagation Delay
Test Circuits/Timing Diagrams
tPRZH
OUT
EN
OUT
EN
VCC/2
VCC/2
VCC
0
VOH
0
VCC
0
VOH
0
FOR MAX3281E THE ENABLE SIGNAL IS INVERTED.
S1 OPEN
S2 CLOSED
S3 = 1.5V
S1 OPEN
S2 CLOSED
S3 = 1.5V
0.25V
tPRHZ
tPRLZ
VCC/2
0.25V
OUT
EN
OUT
EN
VCC
0
VCC
VOL
VCC
0
VCC
VOL
S1 CLOSED
S2 OPEN
S3 = -1.5V
S1 CLOSED
S2 OPEN
S3 = -1.5V
tPRZL
VCC/2
VCC/2
GENERATOR
1.5V
-1.5V VID R
CL
1k
S1
VCC
S2
50
S3
VCC/2
VOH
VOL
A
B
1V
RO
-1V fIN = 1MHz
tr, tf 3ns
OUTPUT
INPUT
VCC/2 VCC/2
tPHL tPLH
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
Figure 5. Receiver Propagation Delay Driven by External
RS-485 Device
Figure 4b. IEC 1000-4-2 ESD Generator Current Waveform
Figure 4a. IEC 1000-4-2 ESD Test Model
Figure 3b. Human Body Model Current Waveform
Figure 3a. Human Body ESD Test Model
Test Circuits/Timing Diagrams (continued)
10ns
A, 1V/div
RO, 2.5V/div
B = GND
tr = 0.7ns to 1ns
30ns
60ns
t
100%
90%
10%
IPEAK
I
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50 to 100
RD
330
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
IP 100%
90%
36.8%
tRL TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
RD
1.5k
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
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MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
W Ll W
Chip Information
PROCESS: BiCMOS
Typical Operating Circuit
Pin Configurations
DATA IN
TRANSMITTER
120RO1
RO2
EN
EN
MAX3283E
MAX3281E
MAX3281E/MAX3283E IN REDUNDANT
RECEIVER APPLICATION
GND
BRO
1 5 A
+
VCC
MAX3280E
SOT23-5
TOP VIEW
2
3 4
GND
BRO
1 6 A
5
VCC
MAX3281E
MAX3283E
SOT23-6
2
3 4
EN (EN)
( ) ARE FOR MAX3283E
GND
BRO
1 6 A
5
VCC
MAX3284E
SOT23-6
2
3 4
VL
+ +
www.maximintegrated.com Maxim Integrated
10
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 1/02 Initial release
1 3/11 Added lead-free parts to the Ordering Information, deleted the transistor count from the
Chip Information section 1, 9
2 12/12 Added automotive qualified part to Ordering Information table 1
3 9/17 Added AEC-Q100 (MAX3280EAUK/V+ Only) to Benefits and Features section 1
4 5/18 Updated Absolute Maximum Ratings and added Package Information section 2
5 6/18 Updated Package Information section 2
6 9/18 Added “Automotive” to Applications section 1
7 1/19 Updated Package Information 2
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2019 Maxim Integrated Products, Inc.
11
MAX3280E/MAX3281E/
MAX3283E/MAX3284E
±15kV ESD-Protected 52Mbps, 3V to 5.5V,
SOT23 RS-485/RS-422 True Fail-Safe Receivers
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

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