SLG59M1606V Datasheet by Dialog Semiconductor GmbH

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EDDDE Tijjji G TTtd F
Silego Technology, Inc. Rev 1.01
000-0059M1606-101 Revised October 8, 2015
Dual 4.5 A Integrated Power Switch
with Reverse Current Blocking
SLG59M1606V
Block Diagram
General Description
The SLG59M1606V is designed for load switching application.
The part comes with two 4.5 A rated MOSFETs switched on by
two ON control pins. Each MOSFETs turn on time is indepen-
dently adjusted by an external capacitor.
Features
Two 4.5 A independent MOSFETs with Reverse Current
Blocking
Two Integrated VGS Charge Pumps
Independent Ramp Control
Protected by thermal shutdown
Pb-Free / RoHS Compliant
• Halogen-Free
STDFN 14L, 1 x 3 x 0.55 mm
Pin Configuration
Applications
Ideal for switching ON and OFF S0 +5.0 and 3.3V power rails with associated support circuitry
Ideal for switching ON and OFF power rails 5V or less.
Can use either channel up to 5.5A with combined maximum current of 8.5A
Maximum load capacitance of 1000 μF for each Channel Source terminal.
CAP_MOS1
MOS1_S
MOS1_S
VDD
ON_MOS1
2
3
4
12
13
14
MOS1_D
MOS1_D 1
14-pin STDFN
(Top View)
CAP_MOS2
GND
MOS2_D
ON_MOS2 5
6
10
11
MOS2_D 7MOS2_S
MOS2_S
8
9
MOS1_D
Linear Ramp
Control
ON_MOS1
Charge
Pump 1
VDD
+2.5 to 5.5 V
4.5 A
Over Temperature
Protection
CAP_MOS1
Reverse
Blocking
MOS1_S
CMOS Input
MOS2_D
Linear Ramp
Control
Charge
Pump 2
4.5 A
Over Temperature
Protection
Reverse
Blocking
MOS2_S
CAP_MOS2
VDD
ON_MOS2 CMOS Input
000-0059M1606-101 Page 2 of 10
SLG59M1606V
Pin Description
Ordering Information
Pin # Pin Name Type Pin Description
1 MOS1_D MOSFET Drain of MOSFET1
2 MOS1_D MOSFET Drain of MOSFET1 (fused with pin 1)
3 ON_MOS1 Input Turns on MOS1 (4 MΩ pull down resistor)
4 VDD VDD +5VDD Power
5 ON_MOS2 Input Turns on MOS2 (4 MΩ pull down resistor)
6 MOS2_D MOSFET Drain of MOSFET2
7 MOS2_D MOSFET Drain of MOSFET2 (fused with pin 6)
8 MOS2_S MOSFET Source of MOSFET2 (fused with pin 9)
9 MOS2_S MOSFET Source of MOSFET2
10 CAP_MOS2 Input Sets ramp and turn on time for MOSFET2
11 GND GND Ground
12 CAP_MOS1 Input Sets ramp and turn on time for MOSFET1
13 MOS1_S MOSFET Source of MOSFET1 (fused with pin 14)
14 MOS1_S MOSFET Source of MOSFET1
Part Number Type Production Flow
SLG59M1606V STDFN 14L Industrial, -40 °C to 85 °C
SLG59M1606VTR STDFN 14L (Tape and Reel) Industrial, -40 °C to 85 °C
000-0059M1606-101 Page 3 of 10
SLG59M1606V
Absolute Maximum Ratings
Electrical Characteristics
Parameter Description Conditions Min. Typ. Max. Unit
VD Power Supply -- -- 6 V
TSStorage Temperature -65 -- 150 °C
ESDHBM ESD Protection Human Body Model 2000 -- -- V
WDIS Package Power Dissipation -- -- 1.2 W
IDSMAX Max Operating Current 4.5 A
MOSFET IDSPK Peak Current from Drain to Source For no more than 10 continuous seconds
out of every 100 seconds -- -- 6 A
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TA = -40 °C to 85 °C (unless otherwise stated)
Parameter Description Conditions Min. Typ. Max. Unit
VDD Power Supply Voltage 2.5 -- 5.5 V
IDD
Power Supply Current when OFF -- 0.1 1 μA
Power Supply Current
ON_MOS_1 & ON_MOS_2
(Steady State) -- 50 100 μA
RDSON ON Resistance
TA 25°C MOSFET1 @100 mA -- 16.0 19.8 mΩ
TA 70°C MOSFET1 @100 mA -- 18.7 24.2 mΩ
TA 85°C MOSFET1 @100 mA 19.8 25.3 mΩ
TA 25°C MOSFET2 @100 mA -- 16.0 19.8 mΩ
TA 70°C MOSFET2 @100 mA -- 18.7 24.2 mΩ
TA 85°C MOSFET2 @100 mA 19.8 25.3 mΩ
MOSFET
IDS Current from Drain to Source for
each MOSFET Continuous, each channel -- -- 4.5 A
IDSLKG IDS Leakage
(Reverse Blocking enabled)
VS = 1.0 V to 5.0 V, VDD = VD = 0 V,
ON_MOS = LOW, 0 to 85 °C, each
channel -- 0.5 1.5 μA
VS = 1.0 V to 5.0 V, VDD = VD = 0 V,
ON_MOS = LOW, -40 to 0 °C, each
channel -- 3 5 μA
VDDrain Voltage 0.85 5.0 VDD V
TON_Delay ON pin Delay Time 50% ON to Ramp Begin,
RL = 20 Ω, CL = 10 μF0 300 500 μs
TTotal_ON Total Turn On Time
50% ON to 90% VSConfigurable 1ms
Example: CAP = 4 nF, VDD = VD = 5
V, Source_Cap = 10 μF, RL = 20 Ω-- 2.0 -- ms
TSLEWRATE Slew Rate
10% VS to 90% VSConfigurable 1V/ms
Example: CAP = 4 nF, VDD = VD = 5
V, Source_Cap = 10 μF, RL = 20 Ω-- 3.0 -- V/ms
CAPSOURCE Source Cap Source to GND -- -- 1000 μF
ON_VIH High Input Voltage on ON pin 0.85 -- VDD V
ON_VIL Low Input Voltage on ON pin -0.3 0 0.3 V
THERMON2Thermal shutoff turn-on temperature -- 125 -- °C
000-0059M1606-101 Page 4 of 10
SLG59M1606V
THERMOFF Thermal shutoff turn-off temperature -- 100 -- °C
THERMTIME Thermal shutoff time -- -- 1 ms
TOFF_Delay OFF Delay Time 50% ON to VS Fall, VDD = VD = 5 V,
RL = 20 Ω, no CL -- -- 15 μs
Notes:
1. Refer to table for configuration details.
2. When device enters thermal shutdown, both channels will turn off.
TA = -40 °C to 85 °C (unless otherwise stated)
Parameter Description Conditions Min. Typ. Max. Unit
SILEGO
000-0059M1606-101 Page 5 of 10
SLG59M1606V
TSLEW vs. CAP
TTOTAL_ON vs. CAP
0.000
2.000
4.000
6.000
8.000
10.000
12.000
14.000
0 2 4 6 8 10 12 14 16 18 20 22 24 26
V/ms
Cap (nF)
Slew Rate (V/ms) Vs. Cap, VDD = 5V, TA = 25C
10%VS to 90%VS, RL = 20 ohm, CL = 10 uF
VD = 1V
VD = 1.5V
VD = 2.5V
VD = 3.3V
VD = 5V
Ttotal_on vs Cap. 50%ON to 90%VS, TA = 25C
VDD = 5V, RL = 20 ohm, CL = 10 uF
0.000
1.000
2.000
3.000
4.000
5.000
6.000
7.000
8.000
9.000
10.000
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Cap (nF)
Ttotal_on (ms)
VD = 1V
VD = 1.5V
VD = 2.5V
VD = 3.3V
VD = 5V
000-0059M1606-101 Page 6 of 10
SLG59M1606V
TTotal_ON, TON_Delay and Slew Rate Measurement
90% VS
50% ON
TON_DELAY
Slew Rate (V/ms)
ON
VS
TTotal_ON
10% VS
50% ON
10% VS
TOFF_DELAY
TFALL
90% VS
000-0059M1606-101 Page 7 of 10
SLG59M1606V
Package Top Marking System Definition
PPDDL Lot #
Pin 1 Identifier
Part Code
Date Code
SILEGO A1 11mm Area(D/2xE/2) 1 ‘ .1 3—1‘ C 1 .12 1 C 0 777.7777 M77 TE I 1 J 1 C 1 3 11: 1 1 Top View BTM View A _ SIDE Vlew Unit: mm Symbol Min Nom Max Symbol Min Nom. Max A 0.50 0.55 I 0.60 D 2.95 3.00 3.05 A1 0.005 0.050 E 0.95 1.00 1.05 A2 0.10 0.15 0.20 L 0.35 0.40 0.45 b 0.13 0.18 0.23 L1 0.20 0.25 0.30 e 0.40 880 L2 0.06 0.11 0.16
000-0059M1606-101 Page 8 of 10
SLG59M1606V
Package Drawing and Dimensions
14 Lead STDFN Package 1 mm x 3 mm (Fused Lead)
MF emTM H°'° PoI Do B r l 47 I Z lb 0 o o " g a o a [J E E1E+7— g g r I Ao P1 “—3 KO 0? m
000-0059M1606-101 Page 9 of 10
SLG59M1606V
Tape and Reel Specifications
Carrier Tape Drawing and Dimensions
Recommended Reflow Soldering Profile
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 1.65 mm3 (nominal). More
information can be found at www.jedec.org.
Package
Type # of
Pins
Nominal
Package
Size
Units per
Reel
Max
Units
per Box
Reel &
Hub Size
(mm)
Trailer A Leader B Pocket Tape (mm)
Pockets Length
(mm) Pockets Length
(mm) Width Pitch
STDFN
14L 14 1x3x0.55mm 3000 3000 178/60 100 400 100 400 8 4
Package
Type
Pocket BTM
Length
[mm]
Pocket BTM
Width
[mm]
Pocket
Depth
[mm]
Index Hole
Pitch
[mm]
Pocket
Pitch
[mm]
Index Hole
Diameter
[mm]
Index Hole
to Tape
Edge
[mm]
Index Hole
to Pocket
Center
[mm]
Tape Width
[mm]
A0 B0 K0 P0 P1 D0 E F W
STDFN 14L 1.15 3.15 0.7 4 4 1.5 1.75 3.5 8
000-0059M1606-101 Page 10 of 10
SLG59M1606V
Revision History
Date Version Change
10/8/2015 1.01 Updated Block Diagram
Updated VD min to 0.85 V
9/9/2015 1.00 Production Release
Updated Electrical Characteristics conditions

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