SLG59M1603V Layout Guide Datasheet by Dialog Semiconductor GmbH

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1 2
3 4
5 6
7 8
910
CAP Array 1
1
VDD
1
D Sense1.1
1
D2
1
S2/VO2
C2
100nF
1 2
3 4
5 6
7 8
910
CAP Array 2
C1
10uF
VO1
1
ON1
2
ON2
3
VO2
4
VIN
5VO3 6
ON3 7
ON4 8
VO4 9
GND 10
U3
1
D2
1
1
1S Sense3.1
1
D Sense1.2
1S Sense3.2
1S Sense3.3
C4
100uF C6
100uF
C5
100uF
1S Sense3.4
VDD
1
GND
2
ON1
3
ON2
4
D1
5D2 6
S1 7
S2 8
CAP1 9
CAP2 10
Dual
1
D Sense2.2
1
2
3
ON2
1
2
3
ON1
1
VO3
1
D Sense2.1
1
VO4
RL1 RL1
RL2 RL2
1
S Sense1.1
1
2
3
ON3
C7
100nF
1
2
3
ON4
D2
1
ON2
2
ON1
3
D1
4S1 5
VDD 6
GND 7
S2 8
U2
C3
100uF
1 2
3 4
5 6
7 8
910
R1_Array
RL3
1
S Sense1.2
1
1
D1/VIN
1
S1/VO1
1
RL4
1 2
3 4
5 6
7 8
910
R2_Array
V_IN
1
GND
2
ON1
3
ON2
4
ON3
5ON4 6
V1_OUT 7
V2_OUT 8
V3_OUT 9
V4_OUT 10
Quad
1
S Sense2.2
1
S Sense2.1
C8
100uF C9
100uF
1D Sense3
MOS1_D
1
MOS1_D
2
ON_MOS1
3
VDD
4
ON_MOS2
5
MOS2_D
6
MOS2_D
7MOS2_S 8
MOS2_S 9
CAP_MOS2 10
GND 11
CAP_MOS1 12
MOS1_S 13
MOS1_S 14
U1
GreenFET3
SLG59M1603V
Layout Guide
Content
1. Description
2. Power and Ground Planes
Description
The SLG59M1603V is 16 m, ~ 4.5 A dual-channel
load switch that is able to switch 1.0 to 5.5 V power
rails. The product is packaged in an ultra-small 1 x 3
mm package.
Figure 1: SLG59M1603V Block Diagram
1 2
3 4
5 6
7 8
910
CAP Array 1
1
VDD
1
D Sense1.1
1
D2
1
S2/VO2
C2
100nF
1 2
3 4
5 6
7 8
910
CAP Array 2
C1
10uF
VO1
1
ON1
2
ON2
3
VO2
4
VIN
5VO3 6
ON3 7
ON4 8
VO4 9
GND 10
U3
1
D2
1
1
1S Sense3.1
1
D Sense1.2
1S Sense3.2
1S Sense3.3
C4
100uF C6
100uF
C5
100uF
1S Sense3.4
VDD
1
GND
2
ON1
3
ON2
4
D1
5D2 6
S1 7
S2 8
CAP1 9
CAP2 10
Dual
1
D Sense2.2
1
2
3
ON2
1
2
3
ON1
1
VO3
1
D Sense2.1
1
VO4
RL1 RL1
RL2 RL2
1
S Sense1.1
1
2
3
ON3
C7
100nF
1
2
3
ON4
D2
1
ON2
2
ON1
3
D1
4S1 5
VDD 6
GND 7
S2 8
U2
C3
100uF
1 2
3 4
5 6
7 8
910
R1_Array
RL3
1
S Sense1.2
1
1
D1/VIN
1
S1/VO1
1
RL4
1 2
3 4
5 6
7 8
910
R2_Array
V_IN
1
GND
2
ON1
3
ON2
4
ON3
5ON4 6
V1_OUT 7
V2_OUT 8
V3_OUT 9
V4_OUT 10
Quad
1
S Sense2.2
1
S Sense2.1
C8
100uF C9
100uF
1D Sense3
MOS1_D
1
MOS1_D
2
ON_MOS1
3
VDD
4
ON_MOS2
5
MOS2_D
6
MOS2_D
7MOS2_S 8
MOS2_S 9
CAP_MOS2 10
GND 11
CAP_MOS1 12
MOS1_S 13
MOS1_S 14
U1
Figure 4. SLG59M1603V Connection Circuit
1 2
3 4
5 6
7 8
910
CAP Array 1
1
VDD
1
D Sense1.1
1
D2
1
S2/VO2
C2
100nF
1 2
3 4
5 6
7 8
910
CAP Array 2
C1
10uF
VO1
1
ON1
2
ON2
3
VO2
4
VIN
5VO3 6
ON3 7
ON4 8
VO4 9
GND 10
U3
1
D2
1
1
1S Sense3.1
1
D Sense1.2
1S Sense3.2
1S Sense3.3
C4
100uF C6
100uF
C5
100uF
1S Sense3.4
VDD
1
GND
2
ON1
3
ON2
4
D1
5D2 6
S1 7
S2 8
CAP1 9
CAP2 10
Dual
1
D Sense2.2
1
2
3
ON2
1
2
3
ON1
1
VO3
1
D Sense2.1
1
VO4
RL1 RL1
RL2 RL2
1
S Sense1.1
1
2
3
ON3
C7
100nF
1
2
3
ON4
D2
1
ON2
2
ON1
3
D1
4S1 5
VDD 6
GND 7
S2 8
U2
C3
100uF
1 2
3 4
5 6
7 8
910
R1_Array
RL3
1
S Sense1.2
1
1
D1/VIN
1
S1/VO1
1
RL4
1 2
3 4
5 6
7 8
910
R2_Array
V_IN
1
GND
2
ON1
3
ON2
4
ON3
5ON4 6
V1_OUT 7
V2_OUT 8
V3_OUT 9
V4_OUT 10
Quad
1
S Sense2.2
1
S Sense2.1
C8
100uF C9
100uF
1D Sense3
MOS1_D
1
MOS1_D
2
ON_MOS1
3
VDD
4
ON_MOS2
5
MOS2_D
6
MOS2_D
7MOS2_S 8
MOS2_S 9
CAP_MOS2 10
GND 11
CAP_MOS1 12
MOS1_S 13
MOS1_S 14
U1
1 2
3 4
5 6
7 8
910
CAP Array 1
1
VDD
1
D Sense1.1
1
D2
1
S2/VO2
C2
100nF
1 2
3 4
5 6
7 8
910
CAP Array 2
C1
10uF
VO1
1
ON1
2
ON2
3
VO2
4
VIN
5VO3 6
ON3 7
ON4 8
VO4 9
GND 10
U3
1
D2
1
1
1S Sense3.1
1
D Sense1.2
1S Sense3.2
1S Sense3.3
C4
100uF C6
100uF
C5
100uF
1S Sense3.4
VDD
1
GND
2
ON1
3
ON2
4
D1
5D2 6
S1 7
S2 8
CAP1 9
CAP2 10
Dual
1
D Sense2.2
1
2
3
ON2
1
2
3
ON1
1
VO3
1
D Sense2.1
1
VO4
RL1 RL1
RL2 RL2
1
S Sense1.1
1
2
3
ON3
C7
100nF
1
2
3
ON4
D2
1
ON2
2
ON1
3
D1
4S1 5
VDD 6
GND 7
S2 8
U2
C3
100uF
1 2
3 4
5 6
7 8
910
R1_Array
RL3
1
S Sense1.2
1
1
D1/VIN
1
S1/VO1
1
RL4
1 2
3 4
5 6
7 8
910
R2_Array
V_IN
1
GND
2
ON1
3
ON2
4
ON3
5ON4 6
V1_OUT 7
V2_OUT 8
V3_OUT 9
V4_OUT 10
Quad
1
S Sense2.2
1
S Sense2.1
C8
100uF C9
100uF
1D Sense3
MOS1_D
1
MOS1_D
2
ON_MOS1
3
VDD
4
ON_MOS2
5
MOS2_D
6
MOS2_D
7MOS2_S 8
MOS2_S 9
CAP_MOS2 10
GND 11
CAP_MOS1 12
MOS1_S 13
MOS1_S 14
U1
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This layout guide provides some important information
about the PCB layout of SLG59M1603V applications.
SILEGO STDFN 1 x 3 - 14L PKG
Unit: um
Figure 2. SLG59M1603V Package Dimensions and
Recommended Land Pattern
Please solder your SLG59M1603V here
Figure 3. SLG59M1603V Evaluation Test Board
Note: Evaluation board has D_Sense and S_Sense pads. Please use them only
for RDS(ON) evaluation.
2. Power and Ground Planes
2.1. The VDD pin needs 0.1uF external capacitor to
smooth pulses from the power supply. Locate these
capacitor close to PIN4.
2.2. The trace length from the control IC to the ON pins
should be as short as possible and must avoid
crossing this trace with power rails.
2.3. The D and S pins carry significant current. Please
note how the D and S pads are placed directly on
the power planes in Figure 3, which minimizes the
RDS(ON) associated with long, narrow traces. The
D and S pins dissipate most of the heat generated
during high-load current condition. The layout shown
in Figure 3 is illustrating a proper solution for heat to
transfer as efficiently as possible out of the device.
2.4. The GND pin (PIN11) should be connected to GND.
2.5. 2 oz. copper is recommended for higher currents.

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