ADGS5412 Datasheet by Analog Devices Inc.

ANALOG DEVICES

SPI Interface, 4× SPST Switches,

9.8 Ω RON, ±20 V/+36 V, Mux Configurable

Data Sheet ADGS5412

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

SPI interface with error detection

Includes CRC, invalid read/write address, and SCLK count

error detection

Supports burst mode and daisy-chain mode

Industry standard SPI Mode 0 and Mode 3 interface

compatible

Guaranteed break-before-make switching allowing external

wiring of switches to deliver multiplexer configurations

VSS to VDD analog signal range

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

Latch-up proof analog switch pins

8 kV HBM ESD rating

Low on resistance (<10 Ω)

1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V

APPLICATIONS

Relay replacement

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

FUNCTIONAL BLOCK DIAGRAM

SDO

D4S4

D3S3

D2S2

D1S1

SPI

INTERFACE

SCLK SDI CS RESET/V

L

ADGS5412

15234-001

Figure 1.

GENERAL DESCRIPTION

The ADGS5412 contains four independent single-pole/single-

throw (SPST) switches. A serial peripheral interface (SPI) controls

the switches. The SPI interface has robust error detection features,

including cyclic redundancy check (CRC) error detection, invalid

read/write address detection, and serial clock (SCLK) count

error detection.

It is possible to daisy-chain multiple ADGS5412 devices together,

which enables the configuration of multiple devices with a

minimal amount of digital lines. The ADGS5412 can also

operate in burst mode to decrease the time between SPI

commands.

Each switch conducts equally well in both directions when on,

and each switch has an input signal range that extends to the

supplies. In the off condition, signal levels up to the supplies are

blocked.

The on-resistance profile is very flat over the full analog input

range, which ensures good linearity and low distortion when

switching audio signals. The ADGS5412 exhibits break-before-

make switching action, allowing use of the device in multiplexer

applications with external wiring.

PRODUCT HIGHLIGHTS

1. SPI interface removes the need for parallel conversion and

logic traces and reduces general-purpose input/output

(GPIO) channel count.

2. Daisy-chain mode removes additional logic traces when

multiple devices are used.

3. CRC, invalid read/write address, and SCLK count error

detection ensure a robust digital interface.

4. CRC error detection capabilities allow for the use of the

ADGS5412 in safety critical systems.

5. Guaranteed break-before-make switching allows the use of

the ADGS5412 in multiplexer configurations with external

wiring.

Trench isolation analog switch section guards against latch-up. A

dielectric trench separates the positive (P) and negative (N) channel

transistors thereby preventing latch-up even under severe

overvoltage conditions.

ADGS5412 Data Sheet

Rev. A | Page 2 of 30

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

±15 V Dual Supply ....................................................................... 3

±20 V Dual Supply ....................................................................... 5

12 V Single Supply ........................................................................ 7

36 V Single Supply ........................................................................ 9

Continuous Current per Channel, SX or DX ............................ 11

Timing Characteristics .............................................................. 11

Absolute Maximum Ratings .......................................................... 13

ESD Caution ................................................................................ 13

Pin Configurations and Function Descriptions ......................... 14

Typical Performance Characteristics ........................................... 15

Test Circuits ..................................................................................... 19

Terminology .................................................................................... 21

Theory of Operation ...................................................................... 22

Address Mode ............................................................................. 22

Error Detection Features ........................................................... 22

Clearing the Error Flags Register ............................................. 23

Burst Mode .................................................................................. 23

Software Reset ............................................................................. 23

Daisy-Chain Mode ..................................................................... 23

Power-On Reset .......................................................................... 24

Break-Before-Make Switching .................................................. 25

Trench Isolation .......................................................................... 25

Digital Input Buffers .................................................................. 25

Applications Information .............................................................. 26

Power Supply Rails ..................................................................... 26

Power Supply Recommendations ............................................. 26

Register Summary .......................................................................... 27

Register Details ............................................................................... 28

Switch Data Register .................................................................. 28

Error Configuration Register .................................................... 28

Error Flags Register .................................................................... 29

Burst Enable Register ................................................................. 29

Software Reset Register ............................................................. 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

7/2018—Rev. 0 to Rev. A

Changes to Table 1 ............................................................................ 3

Changes to Source Off Leakage, IS (Off) Parameter and Drain

Off Leakage, ID (Off) Parameter, Table 1 ....................................... 3

Changes to Source Off Leakage, IS (Off) Parameter and Drain

Off Leakage, ID (Off) Parameter, Table 2 ....................................... 5

Changes to Source Off Leakage, IS (Off) Parameter and Drain

Off Leakage, ID (Off) Parameter, Table 4 ....................................... 9

Deleted Figure 43 and Figure 44; Renumbered Sequentially ..... 24

Added Figure 43 and Figure 44; Renumbered Sequentially ..... 24

5/2017—Revision 0: Initial Version

Table L

Data Sheet ADGS5412

Rev. A | Page 3 of 30

SPECIFICATIONS

±15 V DUAL SUPPLY

Positive supply (VDD) = 15 V ± 10%, negative supply (VSS) = −15 V ± 10%, digital supply (VL) = 2.7 V to 5.5 V, GND = 0 V, unless

otherwise noted.

Table 1.

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

V

DD

to V

SS

V

On Resistance, RON 9.8 Ω typ VS = ±10 V, IS = −10 mA;

see Figure 29

11 14 16 Ω max VDD = +13.5 V, VSS = −13.5 V

On-Resistance Match Between Channels,

∆RON

0.35 Ω typ VS = ±10 V, IS = −10 mA

0.7 0.9 1.1 Ω max

On-Resistance Flatness, RFLAT (ON) 1.2 Ω typ VS = ±10 V, IS = −10 mA

1.6 2 2.2 Ω max

LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off ) ±0.05 nA typ VS = ±10 V, VD = μ 10 V;

see Figure 32

±0.25 ±0.75 ±6 nA max

Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = ±10 V, VD = μ 10 V;

see Figure 32

±0.25 ±0.75 ±6 nA max

Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 28

±0.4 ±2 ±12 nA max

DIGITAL OUTPUT

Output Voltage

Low, VOL 0.4 V max ISINK = 5 mA

0.2

V max

I

SINK

= 1 mA

High Impedance Leakage Current

0.001

µA typ

V

OUT

= V

GND

or V

L

±0.1 µA max

High Impedance Output Capacitance 4 pF typ

DIGITAL INPUTS

Input Voltage

High, VINH 2 V min 3.3 V < VL ≤ 5.5 V

1.35 V min 2.7 V ≤ VL ≤ 3.3 V

Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V

0.8 V max 2.7 V ≤ VL ≤ 3.3 V

Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VL

±0.1 µA max

Digital Input Capacitance, CIN 4 pF typ

DYNAMIC CHARACTERISTICS1

tON 460 ns typ RL = 300 Ω, CL = 35 pF

540 560 580 ns max VS = 10 V; see Figure 36

tOFF 185 ns typ RL = 300 Ω, CL = 35 pF

225 240 270 ns max VS = 10 V; see Figure 36

Break-Before-Make Time Delay, tD 245 ns typ RL = 300 Ω, CL = 35 pF

195 ns min VS1 = VS2 = 10 V, see Figure 35

ADGS5412 Data Sheet

Rev. A | Page 4 of 30

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

Charge Injection, QINJ 245 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;

see Figure 37

Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f =

100 kHz; see Figure 31

Channel to Channel Crosstalk

−70

dB typ

R

L

= 50 Ω, C

L

= 5 pF, f = 1 MHz;

see Figure 30

Total Harmonic Distortion + Noise,

THD + N

0.01 % typ RL = 1 kΩ, 15 V p-p, f = 20 Hz

to 20 kHz; see Figure 33

−3 dB Bandwidth 167 MHz typ RL = 50 Ω, CL = 5 pF; see

Figure 34

Insertion Loss −0.7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see Figure 34

Off Switch Source Capacitance, CS (Off ) 18 pF typ VS = 0 V, f = 1 MHz

Off Switch Drain Capacitance, CD (Off ) 18 pF typ VS = 0 V, f = 1 MHz

On Switch Capacitance, CD (On), CS (On) 57 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

Positive Supply Current, IDD 45 µA typ Digital inputs = 0 V or VL

55 70 µA max

45 µA typ All switches closed,

VL = 5.5 V

110 µA typ All switches closed,

VL = 2.7 V

Digital Supply Current, IL

Inactive 6.3 µA typ Digital inputs = 0 V or VL

8.0 µA max

Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

7 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

210 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL,

V

L

= 5 V

7.5 µA typ CS and SCLK = 0 V or VL,

VL = 3 V

SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL,

VL = 5 V

120 µA typ CS and SCLK = 0 V or VL,

VL = 3 V

Active at 50 MHz 1.8 mA typ Digital inputs toggle

between 0 V and VL,

VL = 5.5 V

2.1 mA max

0.7 mA typ Digital inputs toggle

between 0 V and VL,

VL = 2.7 V

1.0 mA max

Negative Supply Current, ISS 0.001 µA typ Digital inputs = 0 V or VL

1.0 µA max

VDD/VSS ±9/±22 V min/V max GND = 0 V

1 Guaranteed by design; not subject to production test.

Table 2‘

Data Sheet ADGS5412

Rev. A | Page 5 of 30

±20 V DUAL SUPPLY

VDD = 20 V ± 10%, VSS = −20 V ± 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V

On Resistance, RON 9 Ω typ VS = ±15 V, IS = −10 mA; see

Figure 29

10 13 15 Ω max VDD = +18 V, VSS = −18 V

On-Resistance Match Between

Channels, ∆RON

0.35

Ω typ

V

S

= ±15 V, I

S

= −10 mA

0.7 0.9 1.1 Ω max

On-Resistance Flatness, RFLAT (ON) 1.6 Ω typ VS = ±15 V, IS = −10 mA

1.9 2.3 2.7 Ω max

LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V

Source Off Leakage, IS (Off ) ±0.05 nA typ VS = ±15 V, VD = μ 15 V; see

Figure 32

±0.25

±0.75

±6

nA max

Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = ±15 V, VD = μ 15 V; see

Figure 32

±0.25 ±0.75 ±6 nA max

Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = ±15 V; see Figure 28

±0.4 ±2 ±12 nA max

DIGITAL OUTPUT

Output Voltage

Low, VOL 0.4 V max ISINK = 5 mA

0.2 V max ISINK = 1 mA

High Impedance Leakage Current 0.001 µA typ VOUT = VGND or VL

±0.1 µA max

High Impedance Output

Capacitance

4 pF typ

DIGITAL INPUTS

Input Voltage

High, V

INH

2

V min

3.3 V < V

L

≤ 5.5 V

1.35 V min 2.7 V ≤ VL ≤ 3.3 V

Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V

0.8 V max 2.7 V ≤ VL ≤ 3.3 V

Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VL

±0.1 µA max

Digital Input Capacitance, CIN 4 pF typ

ADGS5412 Data Sheet

Rev. A | Page 6 of 30

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

DYNAMIC CHARACTERISTICS1

tON 450 ns typ RL = 300 Ω, CL = 35 pF

530 540 555 ns max VS = 10 V; see Figure 36

tOFF 185 ns typ RL = 300 Ω, CL = 35 pF

230

245

260

ns max

V

S

= 10 V; see Figure 36

Break-Before-Make Time Delay, tD 235 ns typ RL = 300 Ω, CL = 35 pF

185 ns min VS1 = VS2 = 10 V, see Figure 35

Charge Injection, QINJ 310 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see

Figure 37

Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see

Figure 31

Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 30

Total Harmonic Distortion + Noise,

THD + N

0.008 % typ RL = 1 kΩ, 20 V p-p, f = 20 Hz to

20 kHz; see Figure 33

−3 dB Bandwidth

160

MHz typ

R

L

= 50 Ω, C

L

= 5 pF; see Figure 34

Insertion Loss −0.6 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 34

Off Switch Source Capacitance,

CS (Off )

17 pF typ VS = 0 V, f = 1 MHz

Off Switch Drain Capacitance,

CD (Off )

17 pF typ VS = 0 V, f = 1 MHz

On Switch Capacitance, CD (On),

CS (On)

56 pF typ VS = 0 V, f = 1 MHz

POWER REQUIREMENTS VDD = +22 V, VSS = −22 V

Positive Supply Current, IDD 50 µA typ Digital inputs = 0 V or VL

70 110 µA max

50 µA typ All switches closed, VL = 5.5 V

120 µA typ All switches closed, VL = 2.7 V

IL

Inactive 6.3 µA typ Digital inputs = 0 V or VL

8.0 µA max

Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

7 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

210 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL, VL = 5 V

7.5 µA typ CS and SCLK = 0 V or VL, VL = 3 V

SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL, VL = 5 V

120 µA typ CS and SCLK = 0 V or VL, VL = 3 V

Active at 50 MHz 1.8 mA typ Digital inputs toggle between

0 V and VL, VL = 5.5 V

2.1

mA max

0.7 mA typ Digital inputs toggle between

0 V and VL, VL = 2.7 V

1.0 mA max

Negative Supply Current, ISS 0.001 µA typ Digital inputs = 0 V or VL

1.0 µA max

VDD/VSS ±9/±22 V min/V max GND = 0 V

1 Guaranteed by design; not subject to production test.

Table 3‘

Data Sheet ADGS5412

Rev. A | Page 7 of 30

12 V SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V

On-Resistance, RON 19 Ω typ VS = 0 V to 10 V, IS = −10 mA;

see Figure 29

22 27 31 Ω max VDD = 10.8 V, VSS = 0 V

On-Resistance Match Between Channels,

∆RON

0.4

Ω typ

V

S

= 0 V to 10 V, I

S

= −10 mA

0.8 1 1.2 Ω max

On-Resistance Flatness, RFLAT (ON) 4.4 Ω typ VS = 0 V to 10 V, IS = −10 mA

5.5 6.5 7.5 Ω max

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off ) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V;

see Figure 32

±0.25

±0.75

±6

nA max

Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V;

see Figure 32

±0.25 ±0.75 ±6 nA max

Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = 1 V/10 V; see

Figure 28

±0.4 ±2 ±12 nA max

DIGITAL OUTPUT

Output Voltage

Low, VOL 0.4 V max ISINK = 5 mA

0.2 V max ISINK = 1 mA

High Impedance Leakage Current 0.002 µA typ VOUT = VGND or VL

±0.1 µA max

High Impedance Output Capacitance 4 pF typ

DIGITAL INPUTS

Input Voltage

High, V

INH

2

V min

3.3 V < V

L

≤ 5.5 V

1.35 V min 2.7 V ≤ VL ≤ 3.3 V

Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V

0.8 V max 2.7 V ≤ VL ≤ 3.3 V

Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VL

±0.1 µA max

Digital Input Capacitance, CIN 4 pF typ

DYNAMIC CHARACTERISTICS1

tON 545 ns typ RL = 300 Ω, CL = 35 pF

665 720 775 ns max VS = 8 V; see Figure 36

tOFF 200 ns typ RL = 300 Ω, CL = 35 pF

250 275 305 ns max VS = 8 V; see Figure 36

Break-Before-Make Time Delay, tD 320 ns typ RL = 300 Ω, CL = 35 pF

235 ns min VS1 = VS2 = 8 V, see Figure 35

Charge Injection, QINJ 105 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF;

see Figure 37

Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF,

f = 100 kHz; see Figure 31

Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see Figure 30

Total Harmonic Distortion + Noise,

THD + N

0.08 % typ RL = 1 kΩ, 6 V p-p, f = 20 Hz

to 20 kHz; see Figure 33

ADGS5412 Data Sheet

Rev. A | Page 8 of 30

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

−3 dB Bandwidth 180 MHz typ RL = 50 Ω, CL = 5 pF; see

Figure 34

Insertion Loss −1.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;

see Figure 34

Off Switch Source Capacitance, C

S

(Off )

22

pF typ

V

S

= 6 V, f = 1 MHz

Off Switch Drain Capacitance, CD (Off ) 22 pF typ VS = 6 V, f = 1 MHz

On Switch Capacitance, CD (On), CS (On) 56 pF typ VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

Positive Supply Current, IDD 40 µA typ Digital inputs = 0 V or VL

65 µA max

40 µA typ All switches closed, VL = 5.5 V

105 µA typ All switches closed, VL = 2.7 V

IL

Inactive 6.3 µA typ Digital inputs = 0 V or VL

8.0 µA max

Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

7 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

210 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL,

VL = 5 V

7.5 µA typ CS and SCLK = 0 V or VL,

VL = 3 V

SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL,

V

L

= 5 V

120 µA typ CS and SCLK = 0 V or VL,

VL = 3 V

Active at 50 MHz 1.8 mA typ Digital inputs toggle

between 0 V and VL,

VL = 5.5 V

2.1 mA max

0.7

mA typ

Digital inputs toggle

between 0 V and VL,

VL = 2.7 V

1.0 mA max

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1 Guaranteed by design; not subject to production test.

Table 4‘

Data Sheet ADGS5412

Rev. A | Page 9 of 30

36 V SINGLE SUPPLY

VDD = 36 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to VDD V

On Resistance, RON 10.6 Ω typ VS = 0 V to 30 V, IS = −10 mA; see

Figure 29

12 15 17 Ω max VDD = 32.4 V, VSS = 0 V

On-Resistance Match Between

Channels, ∆RON

0.35

Ω typ

V

S

= 0 V to 30 V, I

S

= −10 mA

0.7 0.9 1.1 Ω max

On-Resistance Flatness, RFLAT(ON) 2.9 Ω typ VS = 0 V to 30 V, IS = −10 mA

3.4 4 4.7 Ω max

LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V

Source Off Leakage, IS (Off ) ±0.05 nA typ VS = 1 V/30 V, VD = 30 V/1 V; see

Figure 32

±0.25

±0.75

±6

nA max

Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = 1 V/30 V, VD = 30 V/1 V; see

Figure 32

±0.25 ±0.75 ±6 nA max

Channel On Leakage, ID (On), IS (On) ±0.1 nA typ VS = VD = 1 V/30 V; see Figure 28

±0.4 ±2 ±12 nA max

DIGITAL OUTPUT

Output Voltage

Low, VOL 0.4 V max ISINK = 5 mA

0.2 V max ISINK = 1 mA

High Impedance Leakage Current 0.001 µA typ VOUT = VGND or VL

±0.1 µA max

High Impedance Output

Capacitance

4 pF typ

DIGITAL INPUTS

Input Voltage

High, V

INH

2

V min

3.3 V < V

L

≤ 5.5 V

1.35 V min 2.7 V ≤ VL ≤ 3.3 V

Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V

0.8 V max 2.7 V ≤ VL ≤ 3.3 V

Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VL

±0.1 µA max

Digital Input Capacitance, CIN 4 pF typ

ADGS5412 Data Sheet

Rev. A | Page 10 of 30

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

DYNAMIC CHARACTERISTICS1

tON 470 ns typ RL = 300 Ω, CL = 35 pF

555 565 580 ns max VS = 18 V; see Figure 36

tOFF 195 ns typ RL = 300 Ω, CL = 35 pF

245

250

260

ns max

V

S

= 18 V; see Figure 36

Break-Before-Make Time Delay, tD 245 ns typ RL = 300 Ω, CL = 35 pF

185 ns min VS1 = VS2 = 18 V, see Figure 35

Charge Injection, QINJ 285 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF; see

Figure 37

Off Isolation −78 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see

Figure 31

Channel-to-Channel Crosstalk −70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 30

Total Harmonic Distortion + Noise,

THD + N

0.03 % typ RL = 1 kΩ, 18 V p-p, f = 20 Hz to

20 kHz; see Figure 33

−3 dB Bandwidth

174

MHz typ

R

L

= 50 Ω, C

L

= 5 pF; see Figure 34

Insertion Loss −0.7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see

Figure 34

Off Switch Source Capacitance,

CS (Off )

17 pF typ VS = 18 V, f = 1 MHz

Off Switch Drain Capacitance,

CD (Off )

17 pF typ VS = 18 V, f = 1 MHz

On Switch Capacitance, CD (On),

CS (On)

55 pF typ VS = 18 V, f = 1 MHz

POWER REQUIREMENTS VDD = 39.6 V

Positive Supply Current, IDD 80 µA typ Digital inputs = 0 V or VL

100 130 µA max

80 µA typ All switches closed, VL = 5.5 V

135 µA typ All switches closed, VL = 2.7 V

IL

Inactive 6.3 µA typ Digital inputs = 0 V or VL

8.0 µA max

Inactive, SCLK = 1 MHz 14 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

7 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

SCLK = 50 MHz 390 µA typ CS = VL and SDI = 0 V or VL,

VL = 5 V

210 µA typ CS = VL and SDI = 0 V or VL,

VL = 3 V

Inactive, SDI = 1 MHz 15 µA typ CS and SCLK = 0 V or VL, VL = 5 V

7.5 µA typ CS and SCLK = 0 V or VL, VL = 3 V

SDI = 25 MHz 230 µA typ CS and SCLK = 0 V or VL, VL = 5 V

120 µA typ CS and SCLK = 0 V or VL, VL = 3 V

Active at 50 MHz 1.8 mA typ Digital inputs toggle between

0 V and VL, VL = 5.5 V

2.1

mA max

0.7 mA typ Digital inputs toggle between

0 V and VL, VL = 2.7 V

1.0 mA max

VDD 9/40 V min/V max GND = 0 V, VSS = 0 V

1 Guaranteed by design; not subject to production test.

Table 7‘

Data Sheet ADGS5412

Rev. A | Page 11 of 30

CONTINUOUS CURRENT PER CHANNEL, SX OR DX

Table 5. Four Channels On

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, S

X

OR D

X

VDD = +15 V, VSS = −15 V

LFCSP (θJA = 50°C/W) 126 94 59 mA max

VDD = +20 V, VSS = −20 V

LFCSP (θJA = 50°C/W) 133 98 63 mA max

VDD = 12 V, VSS = 0 V

LFCSP (θJA = 50°C/W) 97 71 44 mA max

VDD = 36 V, VSS = 0 V

LFCSP (θJA = 50°C/W) 131 97 62 mA max

Table 6. One Channel On

Parameter 25°C 85°C 125°C Unit

CONTINUOUS CURRENT, SX OR DX

VDD = +15 V, VSS = −15 V

LFCSP (θJA = 50°C/W) 230 154 102 mA max

VDD = +20 V, VSS = −20 V

LFCSP (θJA = 50°C/W) 241 160 104 mA max

VDD = 12 V, VSS = 0 V

LFCSP (θJA = 50°C/W) 180 126 88 mA max

VDD = 36 V, VSS = 0 V

LFCSP (θ

JA

= 50°C/W)

239

158

104

mA max

TIMING CHARACTERISTICS

VL = 2.7 V to 5.5 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not

production tested.

Table 7.

Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments

t1 20 ns min SCLK period

t2 8 ns min SCLK high pulse width

t3 8 ns min SCLK low pulse width

t4 10 ns min CS falling edge to SCLK rising edge

t5 6 ns min Data setup time

t6 8 ns min Data hold time

t7 10 ns min SCLK rising edge to CS rising edge

t8 20 ns max CS falling edge to SDO data available

t91 20 ns max SCLK falling edge to SDO data available

t10 20 ns max CS rising edge to SDO returns to high impedance

t11 20 ns min CS high time between SPI commands

t12 8 ns min CS falling edge to SCLK becomes stable

t13 8 ns min CS rising edge to SCLK becomes stable

1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. The parameter t9 determines the maximum SCLK frequency when SDO is used.

ADGS5412 Data Sheet

Rev. A | Page 12 of 30

t

1

t

2

t

3

t

4

t

5

t

8

t

9

t

10

t

6

t

7

R/W

CS

SCLK

SDI

SDO

A6 A5 D2 D1 D0

0 0 1D2 D1 D0

15234-002

Figure 2. Addressable Mode Timing Diagram

15234-003

t

1

t

2

t

3

t

4

t

5

t

8

t

9

t

10

t

6

t

7

CS

SCLK

SDI

SDO

INPUT BYTE FOR DEVICE N INPUT BYTE FOR DEVICE N + 1

ZERO BYTE INPUT BYTE FOR DEVICE N

D7 D6 D0 D7 D6 D1 D0

0 0 0 D7 D6 D1 D0

Figure 3. Daisy Chain Timing Diagram

t

13

t

11

t

12

CS

SCLK

15234-004

Figure 4. SCLK/CS Timing Relationship

ESD CAUTION A m ESD (eledrostalk Chavged dewces and (1mm boavds can aimmge mmm detection Although m pmducl mum paxemed 0v pvopvielavy pmemon mvcumy, damage may occur on devices subjected m high enevgy ESD Thevefore. pvopev ESD pvecawonx should be taken to avmd perimmame degradauon or ‘035 o! mnwonalwy

Data Sheet ADGS5412

Rev. A | Page 13 of 30

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 8.

Parameter Rating

VDD to VSS 48 V

VDD to GND −0.3 V to +48 V

VSS to GND +0.3 V to −48 V

VL to GND −0.3 V to +6 V

Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or

30 mA, whichever occurs first

Digital Inputs

1

−0.3 V to +6 V

Peak Current, SX or DX 261 mA (pulsed at 1 ms, 10%

duty cycle maximum)

Continuous Current, SX or DX2 Data + 15%

Temperature Ranges

Operating −40°C to +125°C

Storage

−65°C to +150°C

Junction Temperature 150°C

Thermal Impedance, θJA 50°C/W

Reflow Soldering Peak

Temperature, Pb Free

260 (+0/−5)°C

Human Body Model (HBM) ESD

Rating

8 kV

1 Overvoltages at the SX pins and DX pins are clamped by internal diodes. Limit

the current to the maximum ratings given.

2 See Table 5.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Only one absolute maximum rating can be applied at any one time.

ESD CAUTION

RESET RESET fe_rs CS RESET

ADGS5412 Data Sheet

Rev. A | Page 14 of 30

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

2

1

3

4

5

6

18

17

16

15

14

13

D4

S4

GND

VSS

S1

D1

D3

S3

VDD

NIC

S2

D2

8

9

10

11

7

12

20

19

21

SDO

NIC

CS

22 SCLK

23 SDI

24 NIC

ADGS5412

TOPVIEW

(NottoScale)

NOTES

1. THE EXPOSED PAD IS CONNECTED

INTERNALLY. FOR INCREASED RELIABILITY

OF THE SOLDER JOINTS AND MAXIMUM

THERMAL CAPABILITY, IT IS RECOMMENDED

THAT THE EXPOSED PAD BE SOLDEREDTO

THE SUBSTRATE, VSS.

2. NIC = NOT INTERNALLY CONNECTED.

RESET/VL

NIC

GND

NIC

15234-005

Figure 5. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description

1 D1 Drain Terminal 1. This pin can be an input or an output.

2 S1 Source Terminal 1. This pin can be an input or an output.

3 VSS Most Negative Power Supply Potential. In single-supply applications, tie this pin to GND.

4, 11 GND Ground (0 V) Reference.

5 S4 Source Terminal 4. This pin can be an input or an output.

6 D4 Drain Terminal 4. This pin can be an input or an output.

7, 8, 10,

12, 16, 19,

24

NIC Not Internally Connected.

9 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.

Pull the pin low to complete a hardware reset. All switches are opened, and the appropriate registers are set to

their default values.

13 D3 Drain Terminal 3. This pin can be an input or an output.

14 S3 Source Terminal 3. This pin can be an input or an output.

15

V

DD

Most Positive Power Supply Potential.

17 S2 Source Terminal 2. This pin can be an input or an output.

18 D2 Drain Terminal 2. This pin can be an input or an output.

20 SDO Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading

back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK.

Pull this open-drain output to VL with an external resistor.

21 CS Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it

powers on the SCLK buffers and enables the input shift register. Data is transferred in on the falling edges of the

following clocks. Taking CS high updates the switch condition.

22 SCLK Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.

23 SDI Serial Data Input. Data is captured on the positive edge of the serial clock input.

EPAD Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum

thermal capability, it is recommended that the pad be soldered to the substrate, VSS.

a. 3:53? .6 E. E. 2: 35.559. 20 E. muzﬁmﬁux .6 .5 3:52»? :0

Data Sheet ADGS5412

Rev. A | Page 15 of 30

TYPICAL PERFORMANCE CHARACTERISTICS

0

2

4

6

810

12

14

16

–20 –15 –10

10

–5 0 5 10 15 20

ON RESISTANCE (Ω)

V

S

, V

D

(V)

T

A

= 25°C V

DD

= +9V

V

SS

= –9V

V

DD

= +10V

V

SS

= –10V

V

DD

= +13.2V

V

SS

= –13.2V V

DD

= +15V

V

SS

= –15V

V

DD

= +16.5V

V

SS

= –16.5V

V

DD

= +11V

V

SS

= –11V

15234-006

Figure 6. On Resistance (RON) as a Function of VS, VD (Dual Supply)

0

2

4

6

8

10

12

–25 –20 –15 –10 –5 0 5 10 15 20 25

ON RESISTANCE (Ω)

VS, VD (V)

TA = 25°C

VDD = +18V

VSS = –18V

VDD = +20V

VSS = –20V

VDD = +22V

VSS = –22V

15234-007

Figure 7. On Resistance (RON) as a Function of VS, VD (Dual Supply)

0

5

10

15

20

25

0246810 12 14

ON RESISTANCE (Ω)

V

S

, V

D

(V)

T

A

= 25°C

V

DD

= +9V

V

SS

= 0V

V

DD

= +10V

V

SS

= 0V V

DD

= 10.8V

V

SS

= 0V

V

DD

= 11V

V

SS

= 0V

V

DD

= 13.2V

V

SS

= 0V

V

DD

= 12V

V

SS

= 0V

15234-008

Figure 8. On Resistance (RON) as a Function of VS, VD (Single Supply)

0

2

4

6

8

10

12

0 5 10 15 20 25 30 35 40 45

ON RESISTANCE (Ω)

T

A

= 25°C

V

DD

= 32.4V

V

SS

= 0V

V

DD

= 36V

V

SS

= 0V

V

DD

= 39.6V

V

SS

= 0V

V

S

, V

D

(V)

15234-009

Figure 9. On Resistance (RON) as a Function of VS, VD (Single Supply)

0

2

4

6

8

10

12

14

18

16

–15 –10 –5 0 5 10 15

ON RESISTANCE (Ω)

VS, VD (V)

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

VDD = +15V

VSS = –15V

15234-010

Figure 10. On Resistance (RON) as a Function of VS, VD for Various Temperatures,

±15 V Dual Supply

0

2

4

6

8

10

12

14

16

–20 –15 –10 –5 0 5 10 15 20

ON RESISTANCE (Ω)

VS, VD (V)

VDD = +20V

VSS = –20V

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

15234-011

Figure 11. On Resistance (RON) as a Function of VS, VD for Various Temperatures,

±20 V Dual Supply

\ TA : ‘115'6 \\

ADGS5412 Data Sheet

Rev. A | Page 16 of 30

0

5

10

15

20

25

30

024681012

ON RESISTANCE (Ω)

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

V

DD

= 12V

V

SS

= 0V

V

S

,V

D

(V)

15234-012

Figure 12. On Resistance (RON) as a Function of VS , VD for Various

Temperatures, 12 V Single Supply

0

2

4

6

8

10

12

14

16

0 5 10 15 20 25 30 35 40

ON RESISTANCE (Ω)

V

S

,V

D

(V)

V

DD

= 36V

V

SS

= 0V

T

A

= +125°C

T

A

= +85°C

T

A

= +25°C

T

A

= –40°C

15234-013

Figure 13. RON as a Function of VS ,VD for Various Temperatures,

36 V Single Supply

0 25 50 75 100 125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

0.4

0.2

–0.2

0

–0.4

0.6

0.8 V

DD

= +15V

V

SS

= –15V

V

BIAS

= +10V/–10V I

D

, I

S

(ON) + +

I

D

, I

S

(ON) – –

I

S

(OFF) + –

I

D

(OFF) – +

I

D

(OFF) + –

I

S

(OFF) – +

15234-014

Figure 14. Leakage Currents vs. Temperature, ±15 V Dual Supply

0 25 50 75 100 125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

0.4

0.2

–0.2

0

–0.6

–0.4

0.6

0.8 V

DD

= +20V

V

SS

= –20V

V

BIAS

= +15V/–15V I

D

, I

S

(ON) + +

I

D

, I

S

(ON) – –

I

S

(OFF) + –

I

D

(OFF) – +

I

D

(OFF) + –

I

S

(OFF) – +

15234-015

Figure 15. Leakage Currents vs. Temperature, ±20 V Dual Supply

0 25 50 75 100 125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

0.4

0.2

–0.2

0

0.6 V

DD

= 12V

V

SS

= 0V

V

BIAS

= 1V/10V I

D

, I

S

(ON) + +

I

D

, I

S

(ON) – –

I

S

(OFF) + –

I

D

(OFF) – +

I

D

(OFF) + –

I

S

(OFF) – +

15234-016

Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply

0 255075100125

LEAKAGE CURRENT (nA)

TEMPERATURE (°C)

0.4

0.2

–0.2

0

–0.4

–0.6

0.6

0.8 V

DD

= 36V

V

SS

= 0V

V

BIAS

= 1V/30V I

D

, I

S

(ON) + +

I

D

, I

S

(ON) – –

I

S

(OFF) + –

I

D

(OFF) – +

I

D

(OFF) + –

I

S

(OFF) – +

15234-017

Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply

>

Data Sheet ADGS5412

Rev. A | Page 17 of 30

–140

–120

–100

–80

–60

–40

–20

0

100 1k 10k 100k 1M 10M 100M 1G

OFF ISOLATION (dB)

FREQUENCY (Hz)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

15234-018

Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

10k 100k 1M 10M 100M 1G

CROSSTALK (dB)

FREQUENCY (Hz)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

15234-019

Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply

0

50

100

150

200

250

300

350

400

–20 –10 010 20 30 40

CHARGE INJECTION (pC)

Vs (V)

V

DD

= 20V, V

SS

= –20V

V

DD

= 15V, V

SS

= –15V

V

DD

= 12V, V

SS

= 0V

V

DD

= 36V, V

SS

= 0V

T

A

= 25°C

15234-020

Figure 20. Charge Injection vs. Source Voltage, VS

–120

–100

–80

–60

–40

–20

0

100 1k 10k 100k 1M 10M

AC PSRR (dB)

FREQUENCY (Hz)

100nF DECOUPLING CAP

10µF + 100nF DECOUPLING CAP

NO DECOUPLING

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

15234-021

Figure 21. AC Power Supply Rejection Ration (PSRR) vs. Frequency, ±15 V

Dual Supply

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

20 200 2k 20k

THD + N (%)

FREQUENCY (Hz)

T

A

= 25°C

20V

DS

, V

S

= 20V p-p

15V

DS

, V

S

= 15V p-p

12V

SS

, V

S

= 6V p-p

36V

SS

, V

S

= 18V p-p

15234-022

Figure 22. THD + N vs. Frequency, ±15 V Dual Supply

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–0.2

–1.5

–1.0

–0.5

0

10k 100k 1M 10M 100M 1G

INSERTION LOSS (dB)

FREQUENCY (Hz)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

15234-023

Figure 23. Bandwidth

ADGS5412 Data Sheet

Rev. A | Page 18 of 30

0

100

200

300

400

500

600

700

–40 –20 020

40 60 80 100 120

TIME (ns)

TEMPERATURE (°C)

15V

DS

,

t

ON

20V

DS

,

t

ON

12V

SS

,

t

ON

36V

SS

,

t

ON

15V

DS

,

t

OFF

20V

DS

,

t

OFF

12V

SS

,

t

OFF

36V

SS

,

t

OFF

15234-024

Figure 24. tON, tOFF Times vs. Temperature

0

10

20

30

40

50

60

70

80

90

100

2.7 3.53.0 4.0 4.5 5.0 5.5

I

DD

(uA)

V

L

(V)

12V

15V

20V

36V

T

A

= 25°C

I

DD

WITH ONE SWITCH CLOSED

15234-025

Figure 25. IDD vs. VL

0

50

100

150

200

250

300

350

400

450

110 20 30 40 50

I

L

(uA)

SCLK FREQUENCY (MHz)

V

L

= 5V

V

L

= 3V

T

A

= 25°C

15234-126

Figure 26. IL vs. SCLK Frequency When CS Is High

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

02 4 68

V

OUT

(mV)

TIME (µs)

T

A

= 25°C

V

DD

= +15V

V

SS

= –15V

SCLK = 2.5MHz

SCLK IDLE

15234-127

Figure 27. Digital Feedthrough

Data Sheet ADGS5412

Rev. A | Page 19 of 30

TEST CIRCUITS

V

D

Sx Dx

V

S

D

(ON)

15234-026

Figure 28. On Leakage

Sx Dx

S

V1

I

DS

R

ON

= V

1

/I

DS

15234-027

Figure 29. On Resistance

CHANNEL TO CHANNEL CROSSTALK = 20 log V

OUT

GND

S1

D2

D1

S2

V

OUT

NETWORK

ANALYZER

R

L

50Ω

R

L

50Ω

V

S

V

S

V

DD

V

SS

0.1µF

V

DD

0.1µF

V

SS

NIC

15234-028

Figure 30. Channel to Channel Crosstalk

V

OUT

50Ω

NETWORK

ANALYZER

R

L

50Ω

Sx

Dx

50Ω

OFF ISOLATION = 20 log V

OUT

V

S

V

S

V

DD

V

SS

0.1µF

V

DD

0.1µF

V

SS

GND

15234-029

Figure 31. Off Isolation

Sx Dx

V

S

A A

V

D

I

S

(OFF) I

D

(OFF)

15234-030

Figure 32. Off Leakage

V

DD

V

SS

V

DD

V

SS

V

OUT

R

S

AUDIO PRECISION

R

L

1kΩ

Sx

Dx

V

S

V p-p

0.1µF 0.1µF

GND

15234-031

Figure 33. THD + N

V

OUT

50Ω

NETWORK

ANALYZER

R

L

50Ω

Sx

Dx

INSERTION LOSS = 20 log V

OUT

WITH SWITCH

V

OUT

WITHOUT SWITCH

V

S

V

DD

V

SS

0.1µF

V

DD

0.1µF

V

SS

GND

15234-032

Figure 34. Bandwidth

% V51 VDD Vss 0.1uF 0 0 0.1uF aw at» V”, vs; s1 OTC m \ 6ND 52 a D2 me ‘ Ru Cm INPuT LOGIC 53mm $1 35DF Ru l on 30m ; 35pF 4—W— Voun Voun <><>

ADGS5412 Data Sheet

Rev. A | Page 20 of 30

15234-035

Figure 35. Break-Before-Make Time Delay, tD

V

DD

V

SS

V

DD

V

SS

0.1µF 0.1µF

GND

R

L

300Ω

C

L

35pF

V

S

INPUT LOGIC

SD V

OUT

SCLK

V

OUT

50% 50%

90% 10%

t

ON

t

OFF

15234-033

Figure 36. Switching Times

V

DD

V

SS

V

DD

V

SS

GND

INPUT LOGIC

C

L

1nF

SD V

OUT

R

S

V

S

CLK

3V

V

OUT

∆V

OUT

Q

INJ

= C

L

× ∆V

OUT

SWITCH OFF SWITCH ON

15234-034

Figure 37. Charge Injection

AC PSRR = 20 log V

OUT

GND

D1S1 NIC

NETWORK

ANALYZER

NOTES

1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED

FROM THE AC PSRR MEASUREMENT.

R

L

50Ω

R

L

50Ω

V

S

V

OUT

V

S

V

DD

V

SS

V

SS

15234-138

INTERNAL

BIAS

Figure 38. AC PSRR

Data Sheet ADGS5412

Rev. A | Page 21 of 30

TERMINOLOGY

IDD

IDD is the positive supply current.

ISS

ISS is the negative supply current.

VD, VS

VD and VS are the analog voltages on Terminal D and Terminal

S, respectively.

RON

RON is the ohmic resistance between Terminal D and Terminal

S.

∆RON

∆RON is the difference between the RON of any two channels.

RFLAT (ON)

RFLAT (ON) is flatness that is defined as the difference between the

maximum and minimum value of on resistance measured over

the specified analog signal range.

IS (Off)

IS (Off) is the source leakage current with the switch off.

ID (Off)

ID (Off) is the drain leakage current with the switch off.

ID (On), IS (On)

ID (On) and IS (On) are the channel leakage currents with the

switch on.

VINL

VINL is the maximum input voltage for Logic 0.

VINH

VINH is the minimum input voltage for Logic 1.

IINL, IINH

IINL and IINH are the low and high input currents of the digital

inputs.

CD (Off)

CD (Off) is the off switch drain capacitance, which is measured

with reference to the GND pin.

CS (Off)

CS (Off) is the off switch source capacitance, which is measured

with reference to the GND pin.

CD (On), CS (On)

CD (On) and CS (On) are the on switch capacitances, which are

measured with reference to the GND pin

CIN

CIN is the digital input capacitance.

tON

tON is the delay between applying the digital control input and

the output switching on.

tOFF

tOFF is the delay between applying the digital control input and

the output switching off.

tD

tD is the off time measured between the 80% point of both

switches when switching from one address state to another.

Off Isolation

Off isolation is a measure of unwanted signal coupling through

an off switch.

Charge Injection

Charge injection is a measure of the glitch impulse transferred

from the digital input to the analog output during switching.

Crosstalk

Crosstalk is a measure of unwanted signal that is coupled

through from one channel to another as a result of parasitic

capacitance.

Bandwidth

Bandwidth is the frequency at which the output is attenuated by

3 dB.

On Response

On response is the frequency response of the on switch.

Insertion Loss

Insertion loss is the loss due to the on resistance of the switch.

Total Harmonic Distortion + Noise (THD + N)

THD + N is the ratio of the harmonic amplitude plus the noise

of the signal to the fundamental.

AC Power Supply Rejection Ratio (AC PSRR)

AC PSRR is the ratio of the amplitude of signal on the output to

the amplitude of the modulation. This is a measure of the ability

of the device to avoid coupling noise and spurious signals that

appear on the supply voltage pin to the output of the switch. The dc

voltage on the device is modulated by a sine wave of 0.62 V p-p.

ADGS5412 Data Sheet

Rev. A | Page 22 of 30

THEORY OF OPERATION

The ADGS5412 is a set of serially controlled, quad SPST

switches with error detection features. SPI Mode 0 and Mode 3

can be used with the device, and it operates with SCLK frequen-

cies up to 50 MHz. The default mode for the ADGS5412 is

address mode, in which the registers of the device are accessed

by a 16-bit SPI command that is bounded by CS. The SPI

command becomes 24-bit if the user enables CRC error detection.

Other error detection features include SCLK count error and

invalid read/write error. If any of these SPI interface errors occur,

they are detectable by reading the error flags register. The

ADGS5412 can also operate in two other modes: burst mode

and daisy-chain mode.

The interface pins of the ADGS5412 are CS, SCLK, SDI, and

SDO. Hold CS low when using the SPI interface. Data is captured

on the SDI pin on the rising edge of SCLK, and data is propagated

out on the SDO pin on the falling edge of SCLK. SDO has an

open-drain output; thus, connect a pull-up to this output. When

not pulled low by the ADGS5412, SDO is in a high impedance

state.

ADDRESS MODE

Address mode is the default mode for the ADGS5412 on power-up.

A single SPI frame in address mode is bounded by a CS falling

edge and the succeeding CS rising edge. It is comprised of 16 SCLK

cycles. The timing diagram for address mode is shown in Figure 39.

The first SDI bit indicates if the SPI command is a read or write

command. When the first bit is set to 0, a write command is issued,

and if the first bit is set to 1, a read command is issued. The next

seven bits determine the target register address. The remaining

eight bits provide the data to the addressed register. The last eight

bits are ignored during a read command, because during these

clock cycles, SDO propagates out the data contained in the

addressed register.

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from this register propagates out

on SDO from the ninth to the 16th SCLK falling edge during SPI

reads. A register write occurs on the 16th SCLK rising edge

during SPI writes.

During any SPI command, SDO sends out eight alignment bits

on the first eight SCLK falling edges. The alignment bits observed

at SDO are 0x25.

ERROR DETECTION FEATURES

Protocol and communication errors on the SPI interface are

detectable. There are three detectable errors, which are incorrect

SCLK error detection, invalid read and write address error

detection, and CRC error detection. Each of these errors has a

corresponding enable bit in the error configuration register. In

addition, there is an error flag bit for each of these errors in the

error flags register.

Cyclic Redundancy Check (CRC) Error Detection

The CRC error detection feature extends a valid SPI frame by

eight SCLK cycles. These eight extra cycles are needed to send the

CRC byte for that SPI frame. The CRC byte is calculated by the SPI

block using the 16-bit payload: the R/W bit, Register Address

Bits[6:0], and Register Data Bits[7:0]. The CRC polynomial used

in the SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a

timing diagram with CRC enabled, see Figure 40. Register

writes occur at the 24th SCLK rising edge with CRC error

checking enabled.

During an SPI write, the microcontroller or CPU provides the

CRC byte through SDI. The SPI block checks the CRC byte just

before the 24th SCLK rising edge. On this same edge, the register

write is prevented if an incorrect CRC byte is received by the

SPI interface. The CRC error flag is asserted in the error flags

register in the case of the incorrect CRC byte being detected.

During an SPI read, the CRC byte is provided to the microcon-

troller through SDO.

The CRC error detection feature is disabled by default and can

be configured by the user through the error configuration register.

0 0 1 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0SDO

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SDI

S

CLK

CS

15234-037

Figure 39. Address Mode Timing Diagram

0 0 1 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0

SDO

R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0

1 2 8 9 10 16 17 18 19 20 21 22 23 24

SDI

SCLK

CS

15234-038

Figure 40. Timing Diagram with CRC Enabled

unscL CS the d Ible device: share the same R/VV

Data Sheet ADGS5412

Rev. A | Page 23 of 30

SCLK Count Error Detection

SCLK count error detection allows the user to detect if an incorrect

number of SCLK cycles are sent by the microcontroller or CPU.

When in address mode, with CRC disabled, 16 SCLK cycles are

expected. If 16 SCLK cycles are not detected, the SCLK count

error flag asserts in the error flags register. When less than

16 SCLK cycles are received by the device, a write to the register

map never occurs. When the ADGS5412 receives more than

16 SCLK cycles, a write to the memory map still occurs at the

16th SCLK rising edge, and the flag asserts in the error flags

register. With CRC enabled, the expected number of SCLK

cycles becomes 24. SCLK count error detection is enabled by

default and can be configured by the user through the error

configuration register.

Invalid Read/Write Address Error

An invalid read/write address error detects when a nonexistent

register address is a target for a read or write. In addition, this

error asserts when a write to a read only register is attempted.

The invalid read/write address error flag asserts in the error

flags register when an invalid read/write address error occurs.

The invalid read/write address error is detected on the ninth

SCLK rising edge, which means a write to the register never

occurs when an invalid address is targeted. Invalid read/write

address error detection is enabled by default and can be

disabled by the user through the error configuration register.

CLEARING THE ERROR FLAGS REGISTER

To clear the error flags register, write the special 16-bit SPI

frame, 0x6CA9, to the device. This SPI command does not

trigger the invalid R/W address error. When CRC is enabled,

the user must also send the correct CRC byte for a successful

error clear command. At the 16th or 24th SCLK rising edge, the

error flags register resets to zero.

BURST MODE

The SPI interface can accept consecutive SPI commands

without the need to deassert the CS line, which is called burst

mode. Burst mode is enabled through the burst enable register.

This mode uses the same 16-bit command to communicate

with the device. In addition, the response of the device at SDO

is still aligned with the corresponding SPI command. Figure 41

shows an example of SDI and SDO during burst mode.

The invalid read/write address and CRC error checking functions

operate similarly during burst mode as they do during address

mode. However, SCLK count error detection operates in a

slightly different manner. The total number of SCLK cycles

within a given CS frame are counted, and if the total is not a

multiple of 16 or a multiple of 24 when CRC is enabled, the

SCLK count error flag asserts.

SDO

COMMAND0[15:0]

RESPONSE0[15:0]

COMMAND1[15:0]

RESPONSE1[15:0]

COMMAND2[15:0]

RESPONSE2[15:0]

COMMAND3[15:0]

RESPONSE3[15:0]

SDI

CS

15234-039

Figure 41. Burst Mode Frame

SOFTWARE RESET

When in address mode, the user can initiate a software reset. To

do so, write two consecutive SPI commands, namely 0xA3 fol-

lowed by 0x05, targeting Register 0x0B. After a software reset,

all register values are set to default.

DAISY-CHAIN MODE

The connection of several ADGS5412 devices in a daisy-chain

configuration is possible, and Figure 42 shows this setup. All

devices share the same CS and SCLK line, whereas the SDO of a

device forms a connection to the SDI of the next device, creating a

shift register. In daisy-chain mode, SDO is an eight cycle delayed

version of SDI. When in daisy-chain mode, all commands target

the switch data register. Therefore, it is not possible to make

configuration changes while in daisy-chain mode.

S4

SDI

SCLK

CS

RESET/V

L

S3

S2

S1

D4

SDO

D3

D2

D1

ADGS5412

DEVICE 1

RESET/V

L

S4

S3

S2

S1

D4

SDO

D3

D2

D1

ADGS5412

DEVICE 2

SPI

INTERFACE SPI

INTERFACE

15234-040

Figure 42. Two SPI Controlled Switches Connected in a Daisy-Chain Configuration

ADGS5412 Data Sheet

Rev. A | Page 24 of 30

The ADGS5412 can only enter daisy-chain mode when in

address mode by sending the 16-bit SPI command, 0x2500

(see Figure 43). When the ADGS5412 receives this command,

the SDO of the device sends out the same command because

the alignment bits at SDO are 0x25, which allows multiple

daisy-connected devices to enter daisy-chain mode in a single

SPI frame. A hardware reset is required to exit daisy-chain mode.

For the timing diagram of a typical daisy-chain SPI frame, see

Figure 44. When CS goes high, Device 1 writes Command 0,

Bits[7:0] to its switch data register, Device 2 writes Command 1,

Bits[7:0] to its switches, and so on. The SPI block uses the last

eight bits it received through SDI to update the switches. After

entering daisy-chain mode, the first eight bits sent out by SDO

on each device in the chain are 0x00. When CS goes high, the

internal shift register value does not reset back to zero.

An SCLK rising edge reads in data on SDI while data is

propagated out SDO on an SCLK falling edge. The expected

number of SCLK cycles must be a multiple of eight before CS

goes high. When this is not the case, the SPI interface sends the

last eight bits received to the switch data register

POWER-ON RESET

The digital section of the ADGS5412 goes through an initialization

phase during VL power up. This initialization also occurs after a

hardware or software reset. After VL power-up or a reset, ensure

that a minimum of 120 μs from the time of power-up or reset

before any SPI command is issued. Ensure that VL does not

drop out during the 120 μs initialization phase because it may

result in incorrect operation of the ADGS5412.

0010010100000000SDO

0010010100000000

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SDI

SCL

K

CS

15234-100

Figure 43. SPI Command to Enter Daisy-Chain Mode

SDO

COMMAND3[7:0]

8’h00

COMMAND2[7:0]

COMMAND3[7:0]

COMMAND1[7:0]

COMMAND2[7:0]

COMMAND0[7:0]

COMMAND1[7:0]

SDI

SDO3

8’h00

COMMAND3[7:0]

8’h00

COMMAND2[7:0]

COMMAND3[7:0]

SDO2

DEVICE 2

DEVICE 1

DEVICE 4

DEVICE 3

CS

NOTES

1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.

15234-101

Figure 44. Example of an SPI Frame When Four ADGS5412 Devices are Connected in Daisy-Chain Mode

Data Sheet ADGS5412

Rev. A | Page 25 of 30

BREAK-BEFORE-MAKE SWITCHING

The ADGS5412 exhibits break-before-make switching action,

which allows the use of the device in multiplexer applications.

This configuration can be achieved by externally hardwiring the

device in the mux configuration that is required, as shown in

Figure 45.

4 × SPST

S1

S4

S2

S3

Dx

4:1 MUX

SCLK SDI CS RESET/V

L

SPI

INTERFACE

15234-043

Figure 45. An SPI Controlled Switch Configured into a 4:1 Mux

TRENCH ISOLATION

In the analog switch section of the ADGS5412, an insulating

oxide layer (trench) is placed between the negative channel metal-

oxide semiconductor (NMOS) and the positive channel metal-

oxide semiconductor (PMOS) transistors of each complementary

metal oxide semiconductor switch (CMOS). Parasitic junctions,

which occur between the transistors in junction isolated

switches, are eliminated, and the result is a completely latch-up

proof switch.

In junction isolation, the negative (N) and positive (P) wells of the

PMOS and NMOS transistors form a diode that is reverse-biased

under normal operation. However, during overvoltage

conditions, this diode can become forward-biased. A silicon

controlled rectifier (SCR) circuit is formed by the two transistors,

causing a significant amplification of the current that, in turn,

leads to latch-up. With trench isolation, this diode is removed,

and the result is a latch-up proof switch. The ADGS5412 analog

switch pins pass the maximum rating in the JESD78D standard

in which they are stressed with a ±500 mA pulse for 1 second.

The high voltage latch-up proof family of switches and multiplexers

provide a robust solution for instrumentation, industrial, automo-

tive, aerospace, and other harsh environments that are prone to

latch-up, which is an undesirable high current state that can

lead to device failure and which persists until the power supply

is turned off. The ADGS5412 high voltage switches allow

single-supply operation from 9 V to 40 V and dual-supply

operation from ±9 V to ±22 V.

NMOS PMOS

P-WELL N-WELL

BURIED OXIDE LAYER

HANDLE WAFER

TRENCH

15234-044

Figure 46. Trench Isolation

DIGITAL INPUT BUFFERS

There are input buffers present on the digital inputs pins CS,

SCLK, and SDI. These buffers are active at all times. As result of

this, there will be current draw from the VL supply if SCLK or SDI

are toggling, regardless whether CS is active. For typical values of

this current draw, refer to the specification tables and Figure 26.

RESET —E» —w m Table 10. Recommended Power Management Devices l‘hc vultage range that can be supplied m REbh'l‘

ADGS5412 Data Sheet

Rev. A | Page 26 of 30

APPLICATIONS INFORMATION

POWER SUPPLY RAILS

To guarantee correct operation of the ADGS5412, 0.1 µF

decoupling capacitors are required.

The ADGS5412 can operate with bipolar supplies between ±9 V

and ±22 V. The supplies on VDD and VSS do not have to be

symmetrical; however, the VDD to VSS range must not exceed 44 V.

The ADGS5412 can also operate with single supplies between

9 V and 40 V with VSS connected to GND.

The voltage range that can be supplied to RESET/VL is from 2.7 V

to 5.5 V.

The device is fully specified at ±15 V, ±20 V, +12 V, and +36 V

analog supply voltage ranges.

POWER SUPPLY RECOMMENDATIONS

Analog Devices, Inc. has a wide range of power management

products to meet the requirements of most high performance

signal chains.

An example of a bipolar power solution is shown in Figure 47.

The ADP5070 (dual switching regulator) generates a positive and

negative supply rail for the ADGS5412, amplifier, and/or a

precision converter in a typical signal chain. Also shown in

Figure 47 are two optional LDOs, ADP7118 and ADP7182,

positive and negative low dropout regulators (LDOs), respectively,

that can be used to reduce the output ripple of the ADP5070 in

ultralow noise sensitive applications.

The ADM7160 can be used to generate the RESET/VL voltage

that is required to power digital circuitry within the ADGS5412.

ADM7160

LDO

+3.3V

ADP7118

LDO

+15V

ADP7182

LDO

–15V

+16.5V

–16.5V

ADP5070

+5V

INPUT

15234-045

Figure 47. Bipolar Power Solution

Table 10. Recommended Power Management Devices

Product Description

ADP5070 1 A/0.6 A, dc-to-dc switching regulator with

independent positive and negative outputs

ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator

ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator

ADP7182 −28 V, −200 mA, low noise, LDO linear regulator

Data Sheet ADGS5412

Rev. A | Page 27 of 30

REGISTER SUMMARY

Table 11. Register Summary

Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default RW

0x01 SW_DATA [7:0] Reserved SW4_EN SW3_EN SW2_EN SW1_EN 0x00 R/W

0x02 ERR_CONFIG [7:0] Reserved RW_ERR_EN SCLK_ERR_EN CRC_ERR_EN 0x06 R/W

0x03 ERR_FLAGS [7:0] Reserved RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG 0x00 R

0x05 BURST_EN [7:0] Reserved BURST_MODE_EN 0x00 R/W

0x0B SOFT_RESETB [7:0] SOFT_RESETB 0x00 R/W

Table 12. BR Descriptions for SW7DATA Table 13. BR Descriptions for ERRiCONFlG

ADGS5412 Data Sheet

Rev. A | Page 28 of 30

REGISTER DETAILS

SWITCH DATA REGISTER

Address: 0x01, Reset: 0x00, Name: SW_DATA

The switch data register controls the status of the four switches of the ADGS5412.

Table 12. Bit Descriptions for SW_DATA

Bits Bit Name Settings Description Default Access

[7:4] Reserved These bits are reserved; set these bits to 0. 0x0 R

3 SW4_EN Enable bit for SW4. 0x0 R/W

0 SW4 open.

1

SW4 closed.

2 SW3_EN Enable bit for SW3. 0x0 R/W

0 SW3 open.

1 SW3 closed.

1 SW2_EN Enable bit for SW2. 0x0 R/W

0 SW2 open.

1

SW2 closed.

0 SW1_EN Enable bit for SW1. 0x0 R/W

0 SW1 open.

1 SW1 closed.

ERROR CONFIGURATION REGISTER

Address: 0x02, Reset: 0x06, Name: ERR_CONFIG

The error configuration register allows the user to enable/disable the relevant error features as required.

Table 13. Bit Descriptions for ERR_CONFIG

Bits Bit Name Settings Description Default Access

[7:3] Reserved These bits are reserved; set these bits to 0. 0x0 R

2 RW_ERR_EN Enable bit for detecting an invalid read/write address. 0x1 R/W

0 Disabled.

1 Enabled.

1 SCLK_ERR_EN Enable bit for detecting the correct number of SCLK cycles in an SPI frame. When

CRC is disabled and burst mode is disabled, 16 SCLK cycles are expected. When

CRC is enabled and burst mode is disabled, 24 SCLK cycles are expected. A multiple

of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A

multiple of 24 SCLK cycles is expected when CRC is enabled and burst mode is

enabled.

0x1 R/W

0 Disabled.

1 Enabled.

0 CRC_ERR_EN Enable bit for CRC error detection. SPI frames must be 24 bits wide when enabled. 0x0 R/W

0 Disabled.

1 Enabled.

the—er R/VV Table 15. BR Descriptions for BURSTJEN

Data Sheet ADGS5412

Rev. A | Page 29 of 30

ERROR FLAGS REGISTER

Address: 0x03, Reset: 0x00, Name: ERR_FLAGS

The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI

command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled then the user

must include the correct CRC byte during the SPI write in order for the clear error flags register command to be successful.

Table 14. Bit Descriptions for ERR_FLAGS

Bits

Bit Name

Settings

Description

Default

Access

[7:3] Reserved These bits are reserved and are set to 0. 0x0 R

2 RW_ERR_FLAG Error flag for invalid read/write address. The error flag asserts during an SPI read

if the target address does not exist. The error flag also asserts when the target

address of an SPI write does not exist or is read only.

0x0 R

0 No error.

1 Error.

1 SCLK_ERR_FLAG Error flag for the detection of the correct number of SCLK cycles in an SPI frame. 0x0 R

0

No error.

1 Error.

0 CRC_ERR_FLAG Error flag that determines if a CRC error occurred during a register write. 0x0 R

0 No error.

1 Error.

BURST ENABLE REGISTER

Address: 0x05, Reset: 0x00, Name: BURST_EN

The burst enable register allows the user to enable or disable the burst mode. When enabled, the user can send multiple consecutive SPI

commands without de-asserting CS.

Table 15. Bit Descriptions for BURST_EN

Bits Bit Name Settings Description Default Access

[7:1] Reserved These bits are reserved; set these bits to 0. 0x0 R

0 BURST_MODE_EN Burst mode enable bit. 0x0 R/W

0 Disabled.

1 Enabled.

SOFTWARE RESET REGISTER

Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB

This register is used to perform a software reset. Consecutively write 0xA3 and 0x05 to this register and the device registers reset to their

default states.

Table 16. Bit Descriptions for SOFT_RESETB

Bits Bit Name Settings Description Default Access

[7:0] SOFT_RESETB To perform a software reset, consecutively write 0xA3 followed by 0x05 to this

register.

0x0 R/W

ADGS5412 Data Sheet

Rev. A | Page 30 of 30

OUTLINE DIMENSIONS

0.50

BSC

0.50

0.40

0.30

COMPLIANT

TO

JEDEC STANDARDS MO-220-VGGD-8.

BOTTOM VIEW

TOP VIEW

4.10

4.00 SQ

3.90

1.00

0.95

0.90 0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

PIN 1

INDICATOR

1

24

7

12

13

18

19

6

02-09-2017-A

0.30

0.25

0.18

0.20 MIN

2.70

2.60 SQ

2.50

EXPOSED

PAD

PKG-004677

SEATING

PLANE

PIN 1

INDICATOR AREA OPTIONS

(SEE DETAIL A)

DETAIL A

(JEDEC 95)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 48. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.95 mm Package Height

(CP-24-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADGS5412BCPZ −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-17

ADGS5412BCPZ-RL7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-17

EVAL-ADGS5412SDZ Evaluation Board

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D15234-0-7/18(A)

ADGS5412 Datasheet by Analog Devices Inc.

Products related to this Datasheet