CY54,74FCT480T Datasheet by Texas Instruments

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[ ] [ ] I: 1 Significantly Improved Noise D‘ [ ] Characteristics E1 [ ] 0 lo" Supports Partial-Power-Down Mode Fl I: ] Operation G1 I: J O Matched Rise and Fall Times Hi E % O Fully Compatible With TTL Input and CHK/EE ] Output Logic Levels m [ ] 2 0 Two a-Bit Parity Generators/Checkers GM; [ ]— 0 Open-Drain Active-Low Parity-Error Output 0 Expandable for Larger Word Widths CV54FCT4801...L p O ESD Protection Exceeds JESD 22 (TOP VIEW) — ZOOO-V Human-Body Model (A114-A) — ZOO-V Machine Model (A115-A) — 1000-V Charged-Device Model (C101) 0 CY54FCT480T — 32-mA Output Sink Current — 12-mA Output Source Current 0 CY74FCT480T — 64-mA Output Sink Current — 32-mA Output Source Current l—ll—ll—ll—ll—ll—ll—l description The ’FCT480T devices are highrspeed, dual, ‘ ‘ ‘ 87bit parity generators/checkers. Each parity generator/checker accepts eight data bits and one parity bit as inputs, and generates a sum and parityrerror (ERROR) output. These devices can be used in oddrparity systems. ERROR is an openrdrain output designed lor easy expansion of the word width by a wiredrOR connection of several 'FCT480T devices. Because no add the parityrgeneration or parityrchecking times remain the same as for an individual ‘FC These devices are fully specified lor partiairpowerrdown applications using log. The ID. outputs, preventing damaging current backflow through the device when it is powered Please be aware that an lmportant nctlce concernlng avatlamllty. standard warranty, and use Texas instruments semlconductor products and dlscialrners thereto appears at the end ol thls data sh PRODMCHON nun h. utlan u current I: at puptmmr. me PruduclS mninrm m ape Alien: per the term sirens inxlluments “Ms. ”TEXAS INSTRUMENTS POST OFFICE aox 555m - DALLAS TEXAS 75255 Copyrlght (a 20m.
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B – MAY 1993 – REVISED OCTOBER 2001
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
Two 8-Bit Parity Generators/Checkers
Open-Drain Active-Low Parity-Error Output
Expandable for Larger Word Widths
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
CY54FCT480T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT480T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT480T devices are high-speed, dual,
8-bit parity generators/checkers. Each parity
generator/checker accepts eight data bits and
one parity bit as inputs, and generates a sum and
parity-error (ERROR) output. These devices can
be used in odd-parity systems. ERROR is an
open-drain output designed for easy expansion of
the word width by a wired-OR connection of several ’FCT480T devices. Because no additional logic is needed,
the parity-generation or parity-checking times remain the same as for an individual ’FCT480T device.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CY54FCT480T ...L PACKAGE
(TOP VIEW)
CY74FCT480T ...P, Q, OR SO PACKAGE
(TOP VIEW)
A1
B1
C1
D1
E1
F1
G1
H1
PAR1
CHK/GEN
ODD1
GND
VCC
A2
B2
C2
D2
E2
F2
G2
H2
PAR2
ERROR
ODD2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
32 1
13 14
5
6
7
8
9
10
11
C2
D2
E2
NC
F2
G2
H2
D1
E1
F1
NC
G1
H1
PAR1
4
15 16 17 18
GND
NC
ERROR
PAR
C
NC
28 27 26 25
24
23
22
21
20
19
12
CHK/GEN
CC
V
NC – No internal connection
2
ODD2
ODD1
1
B1
A1
A2
B2
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
~40“01055°C SOIC SO FCT4EOB I "1 2 H2 1 2 Number cl Arm wpur high ‘5 even Number cl Number 0' A1 H1 mputs mgh ‘5 odd Number 0' *9 TEXAS INSTRUMENTS
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B MAY 1993 REVISED OCTOBER 2001
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGESPEED
(ns) ORDERABLE
PART NUMBER TOP-SIDE
MARKING
DIP P Tube 6.1 CY74FCT480BTPC CY74FCT480BTPC
QSOP Q Tape and reel 6.1 CY74FCT480BTQCT FCT480B
40°Cto85°C
SOIC SO
Tube 6.1 CY74FCT480BTSOC
FCT480B
40°C
to
85°C
SOIC
SO
Tape and reel 6.1 CY74FCT480BTSOCT
FCT480B
DIP P Tube 7.5 CY74FCT480ATPC CY74FCT480ATPC
QSOP Q Tape and reel 7.5 CY74FCT480ATQCT FCT480A
55°C to 125°CLCC L Tube 7 CY54FCT480BTLMB
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS OUTPUTS
A1H1A2H2CHK/GEN PAR1PAR2ODD1ODD2ERROR
H H H L L H
Number of
HLHH LL
Number
of
A2H2 inputs, HHL L HL
high is even HLLH HL
Number of
A1H1in
p
uts
LXXH HL
A
1
H
1
i
npu
t
s,
hi
g
h i
s
e
v
e
nH H H L H L
high
is
even
Number of
HLHH HL
Number
of
inputs A2H2,HHL L LH
high is odd HLLH LL
LXXH LL
H H H H L L
Number of
HLH L LH
Number
of
A2H2 inputs, HHL H HL
high is even HLL L HL
Number of
A1H1in
p
uts
LXX L HL
A1
H1
in uts
,
hi
g
h is odd H H H H H L
high
is
odd
Number of HLH L HL
Number
of
A2H2 inputs, HHL H LL
high is odd HLL L LH
L X X L L H
H = High logic level, L = Low logic level, X = Dont care
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B MAY 1993 REVISED OCTOBER 2001
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram
ODD1
ODD2
ERROR
Pin numbers shown are for the P, Q, and SO packages.
A1
B1
C1
D1
E1
F1
G1
H1
A2
B2
C2
D2
E2
F2
G2
H2
PAR1
PAR2
CHK/GEN
1
2
3
4
5
6
7
8
9
10
23
22
21
20
19
18
17
16
11
14
13
15
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC input voltage range 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output voltage range 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC output current (maximum sink current/pin) 120 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): P package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): Q package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): SO package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient temperature range with power applied, TA 65°C to 135°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
PARAMETER TEST CONDITIONS *9 TEXAS INSTRUMENTS
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B MAY 1993 REVISED OCTOBER 2001
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
CY54FCT480T CY74FCT480T
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current 12 32 mA
IOL Low-level output current 32 64 mA
TAOperating free-air temperature 55 125 40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
CY54FCT480T CY74FCT480T
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYPMAX MIN TYPMAX
UNIT
VIK
VCC = 4.5 V, IIN = 18 mA 0.7 1.2
V
V
IK VCC = 4.75 V, IIN = 18 mA 0.7 1.2
V
VCC = 4.5 V, IOH = 12 mA 2.4 3.3
VOH
IOH = 15 mA 2.4 3.3 V
CC =
.
IOH = 32 mA 2
VOL
VCC = 4.5 V, IOL = 32 mA 0.3 0.55
V
V
OL VCC = 4.75 V, IOL = 64 mA 0.3 0.55
V
Vhys All inputs 0.2 0.2 V
II
VCC = 5.5 V, VIN = VCC 5
µA
I
IVCC = 5.25 V, VIN = VCC 5µ
A
IIH
VCC = 5.5 V, VIN = 2.7 V ±1
µA
I
IH VCC = 5.25 V, VIN = 2.7 V ±1µ
A
IIL
VCC = 5.5 V, VIN = 0.5 V ±1
µA
I
IL VCC = 5.25 V, VIN = 0.5 V ±1µ
A
Ioff VCC = 0 V, VOUT = 4.5 V ±1±1µA
IOS
VCC = 5.5 V, VOUT = 0 V 60 120 225
mA
I
OS
VCC = 5.25 V, VOUT = 0 V 60 120 225
mA
IOZH
VCC = 5.5 V, VOUT = 2.7 V 10
µA
I
OZH VCC = 5.25 V, VOUT = 2.7 V 10 µ
A
IOZL
VCC = 5.5 V, VOUT = 0.5 V 10
µA
I
OZL VCC = 5.25 V, VOUT = 0.5 V 10 µ
A
ICC
VCC = 5.5 V, VIN 0.2 V, VIN VCC 0.2 V 0.1 0.2
mA
I
CC VCC = 5.25 V, VIN 0.2 V, VIN VCC 0.2 V 0.1 0.2
mA
ICC
VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2
mA
I
CC VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.5 2
mA
Typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND
PARAMETER TEST CONDITIONS UNIT I0:0MH‘ I0:0MH‘ mA *5 TEXAS INSTRUMENTS
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B MAY 1993 REVISED OCTOBER 2001
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
CY54FCT480T CY74FCT480T
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYPMAX MIN TYPMAX
UNIT
ICCD
VCC = 5.5 V, Outputs open,
One bit switching at 50% duty cycle,
VIN 0.2 V or VIN VCC 0.2 V 0.06 0.12
mA/
I
CCD
VCC = 5.25 V, Outputs open,
One bit switching at 50% duty cycle,
VIN 0.2 V or VIN VCC 0.2 V 0.06 0.12
MHz
#
One bit
switching
at f
1
= 2.5 MHz
VIN 0.2 V or
VIN VCC 0.2 V 0.7 1.4
#
VCC = 5.5 V,
1
at 50% duty
cycle VIN = 3.4 V or GND 1 2.4
#
0 =
z,
Outputs open 16 bits
switching
at f
1
= 2.5 MHz
VIN 0.2 V or
VIN VCC 0.2 V 2.5 5||
IC#
1
at 50% duty
cycle VIN = 3.4 V or GND 6.5 21||
mA
I
C
#
One bit
switching
at f
1
= 2.5 MHz
VIN 0.2 V or
VIN VCC 0.2 V 0.7 1.4
mA
VCC = 5.25 V,
1
at 50% duty
cycle VIN = 3.4 V or GND 1 2.4
0 =
z,
Outputs open 16 bits
switching
at f
1
= 2.5 MHz
VIN 0.2 V or
VIN VCC 0.2 V 2.5 5||
1
at 50% duty
cycle VIN = 3.4 V or GND 6.5 21||
Ci5 10 5 10 pF
Co9 12 9 12 pF
Typical values are at VCC = 5 V, TA = 25°C.
This parameter is derived for use in total power-supply calculations.
#IC= ICC + ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC= Total supply current
ICC= Power-supply current with CMOS input levels
ICC= Power-supply current for a TTL high input (VIN = 3.4 V)
DH= Duty cycle for TTL inputs high
NT= Number of TTL inputs at DH
ICCD= Dynamic current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
PARAMETER tPLH tPHL tPLH tPLH tPHL tPLH tPHL *9 TEXAS INSTRUMENTS
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B MAY 1993 REVISED OCTOBER 2001
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over operating free-air temperature range (see Figure 1)
PARAMETER
FROM TO CY74FCT480AT CY54FCT480BT CY74FCT480BT
UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX
UNIT
tPLH
A
ODD 7.5 7 6.1
ns
tPHL
A
(see Figure 1) 7 6.6 6.1
ns
tPLH
CHK/GEN
ODD 6.5 6.3 5.9
ns
tPHL
CHK/GEN
(see Figure 1) 7.5 7.4 5.9
ns
tPLH
A
ERROR 7 7 6.1
ns
tPHL
A
(see Figure 2) 8.5 8.1 6.5
ns
tPLH
CHK/GEN
ERROR 7.5 7.1 5.7
ns
tPHL
CHK/GEN
(see Figure 2) 7 6.9 5.5
ns
tPLH is measured up to VOUT = VOL + 0.3 V.
0 S1 0 CL:50pF CL=50pFi (See Mme A) I (See Note A) ’.‘ LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS a-STATE OUTPUTS Timing InpuI 7K i I u—# I I I I 3 " I ,,,,,, "1P"! :X:X: Data Input / \ 0 V VOLTAGE WAVEFORMS PULSE DURATION 7 7 7 3" cquuI '"P'" o v ConIroI I ‘ I I 'PLH H “—+ ‘PHL I #I f % % In-Phase m VOH ompm ‘ ‘ I 1 cm uI Wavelorm1 p ‘ 1 VOL (See Note a) I ‘ ‘ V9; 7 L I lPHL fl H—D‘PIPLH I i ‘p % f v 7 L 7 , om-oI-Phase m— “ Wave?°"r‘:‘”2' /—4{ 0mm 7, 7 VOL (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES, A, CL Includes pmbe and pg capacIIance B, WaveIorm I Is lor an oulpm wIlh ImemaI CandIIIonS such mat Ihe oulpm Is I WaveIorm 2 Is Ior an oquuI wIIh InIemaI condllmns Such mm the oquuI l5 h C, The aquuIs are measured one aI a me wIlh ane InpuI IrarISIIIan per measu *5 TEXAS INSTRUMENTS POST OFFICE aox 555m - DALLAS IEXAS 752
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B MAY 1993 REVISED OCTOBER 2001
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3.5 V
0 V
VOL + 0.3 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
S1 7 V
500
GND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH 0.3 V
500
500
1.5 V1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
cL :Vcc 9 Mme A) 5"” ‘1 cquuI 1.5 v VOL + 0.3 v 7 7 VOL LOAD CIRCUIT FOR VOLTAGE WAVEFORMS OPEN-DRAIN OUTPUTS PROPAGATION DELAV TIMES NOTES. A. CL mcIudes probe and m capacnance. 3. AH InpuI pulses are supphed by generators havIrIg me IeIIewmg charactensucs. PRR £1 MHz, 20 e 50 a I, g 3 ns I. g 3 ns, C. The oquuIs are measured one a a me wIIh one InpuI Iransmon per measurement. *9 TEXAS NSTRUMENTS
CY54FCT480T, CY74FCT480T
DUAL 8-BIT PARITY GENERATORS/CHECKERS
SCCS025B MAY 1993 REVISED OCTOBER 2001
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
FOR OPEN-DRAIN OUTPUTS
tPHL tPLH
VCC
0 V
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
OPEN-DRAIN OUTPUTS
1.5 V 1.5 V500
Output
7 V
VOL
VCC
1.5 V VOL + 0.3 V
500
Figure 2. Load Circuit and Voltage Waveforms
I TEXAS INSTRUMENTS
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CY54FCT480BTLMB ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type
CY74FCT480ATPC ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CY74FCT480ATPCE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CY74FCT480BTPC ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CY74FCT480BTPCE4 ACTIVE PDIP NT 24 15 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CY74FCT480BTQCT ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT480BTQCTE4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT480BTQCTG4 ACTIVE SSOP/
QSOP DBQ 24 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CY74FCT480BTSOC ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT480BTSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CY74FCT480BTSOCG4 ACTIVE SOIC DW 24 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 1
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 11-Nov-2009
Addendum-Page 2
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS # Kn «P1» $®¢®®®¢® W 69 '69 0 BO Cavity +l A0 + Dlmension deslgned to accommodate the component width Dlmenslon deslgned la accommcdalc me compcncnl lenglh Dlmenslon dESlgnEd la accommodals me component lhlckness Overall wmlh ol the earner [ape Reel Dlameler A0 Bo K0 W i P1 Pllch between suoceSsive cavny centers :IZEI: 1 Reel Width (W1) QUADRANT ASSIGNMENYS 000 FOR PIN 1 ORIENTATION IN TAPE 0 O O O O SpracketHoles ,,,,, ‘ User Direction 0' Feed Pocket Ouadranls
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CY74FCT480BTQCT SSOP/
QSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2009
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CY74FCT480BTQCT SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Jul-2009
Pack Materials-Page 2
amplifier “Lam dataccnveneui com www dlg cam dsg.li.com www com/clacks interlace com IogIcM cam gawerJiLom micrcccmmller 1‘ Cam www com/Igrl www mam/audio www \cam/aulommive www \ cam/b oadband wwwm cam/dlgwtalccnlml wwwm cam/medica‘ wwwm cam/mmtam wwwm cam/oglicalnetwolk wwwm cam/security wwwm cam/(e‘eghcny www \cam/videa www \cam/w‘re‘ess
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