VND5050A(J,K)-E Datasheet by STMicroelectronics

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September 2013 Doc ID 12272 Rev 10 1/37
1
VND5050AJ-E
VND5050AK-E
Double channel high side driver with analog current sense
for automotive applications
Features
Main
Inrush current active management by
power limitation
Very low standby current
3.0 V CMOS compatible input
Optimized electromagnetic emission
Very low electromagnetic susceptibility
In compliance with the 2002/95/ec
european directive
Diagnostic functions
Proportional load current sense
High current sense precision for wide range
currents
Current sense disable
Thermal shutdown indication
Very low current sense leakage
Protections
Undervoltage shutdown
Overvoltage clamp
Load current limitation
Self limiting of fast thermal transients
Protection against loss of ground and loss
of V
CC
Thermal shutdown
Reverse battery protection (see Application
schematic on page 21)
Electrostatic discharge protection
Applications
All types of resistive, inductive and capacitive
loads
Suitable as LED driver
Description
The VND5050AJ-E, VND5050AK-E is a
monolithic device made using STMicroelectronics
VIPower M0-5 technology. It is intended for driving
resistive or inductive loads with one side
connected to ground. Active V
CC
pin voltage
clamp protects the device against low energy
spikes (see ISO7637 transient compatibility
table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open. When CS_DIS
is driven high, the current sense pin is in a high
impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shutdown intervention.
Thermal shutdown with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Max transient supply voltage V
CC
41 V
Operating voltage range V
CC
4.5 to 36 V
Max on-state resistance (per ch.) R
ON
50 mΩ
Current limitation (typ) I
LIMH
18 A
Off-state supply current I
S
A
(1)
1. Typical value with all loads connected
Table 1. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-12
VND5050AJ-E VND5050AJTR-E
PowerSSO-24
VND5050AK-E VND5050AKTR-E
PowerSSO-24PowerSSO-12
www.st.com
Contents VND5050AJ-E / VND5050AK-E
2/37 Doc ID 12272 Rev 10
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-12thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 PowerSSO-24thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 ECOPACK
®
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 PowerSSO-24™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4 PowerSSO-12packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5 PowerSSO-24packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VND5050AJ-E / VND5050AK-E List of tables
Doc ID 12272 Rev 10 3/37
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Current sense (8V<V
CC
<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Electrical transient requirements (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Electrical transient requirements (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Electrical transient requirements (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. PowerSSO-12™ thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. PowerSSO-24™ thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of figures VND5050AJ-E / VND5050AK-E
4/37 Doc ID 12272 Rev 10
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Delay response time between rising edge of output current and rising edge of current sense
(CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. I
OUT
/I
SENSE
vs I
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On-state resistance vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. On-state resistance vs V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. I
LIMH
vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one channel on). . . . 25
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 27
Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one channel on) . . . 28
Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™ . . . . . . . . . . . . . . . . . 28
Figure 36. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 37. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 38. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. PowerSS0-24
TM
tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 41. PowerSSO-24
TM
tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VND5050AJ-E / VND5050AK-E Block diagram and pin description
Doc ID 12272 Rev 10 5/37
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Pin function
Name Function
V
CC
Battery connection.
OUTPUT
1,2
Power output.
GND Ground connection. Must be reverse battery protected by an external diode/resistor
network.
INPUT
1,2
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
CURRENT
SENSE
1,2
Analog current sense pin, delivers a current proportional to the load current
CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
LOGIC
UNDERVOLTAGE
OVERTEMP. 1
I
LIM
1
PwCLAMP 1
I
OUT1
GND
INPUT1
V
CC
OUTPUT1
CURRENT
SENSE1
DRIVER 1
V
CC
CLAMP
V
DSLIM
1
I
LIM
2
PwCLAMP 2
DRIVER 2
V
DSLIM
2
OVERTEMP. 2
I
OUT2
OUTPUT2
CURRENT
SENSE2
CS_DIS
K 2
INPUT2
K 1
Pwr
LIM
1
Pwr
LIM
2
y: HHHHHHHHHHM
Block diagram and pin description VND5050AJ-E / VND5050AK-E
6/37 Doc ID 12272 Rev 10
Figure 2. Configuration diagram (top view)
Table 3. Suggested connections for unused and not connected pins
Connection/pin Current sense N.C. Output Input CS_DIS
Floating N.R.
(1)
XX X X
To ground Through 1 KΩ
resistor XN.R.
(1)
1. Not recommended.
Through 10 KΩ
resistor Through
10 KΩ resistor
PowerSSO-12
TAB = V
cc
V
cc
OUTPUT2
OUTPUT1
OUTPUT1
V
cc
OUTPUT2
12
11
10
9
8
7
1
2
3
4
5
6
CS_DIS
GND
INPUT1
CURRENT SENSE1
INPUT2
CURRENT SENSE2
N.C.
INPUT1
GND
V
CC
N.C.
INPUT2
CS_DIS.
V
CC
CURRENT SENSE1
N.C.
N.C.
CURRENT SENSE2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
PowerSSO-24
TAB = V
CC
F 1 1
VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 7/37
2 Electrical specifications
Figure 3. Current and voltage conventions
Note: V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
I
S
I
GND
V
CC
V
CC
V
SENSE2
OUTPUT1 I
OUT1
CURRENT I
SENSE1
INPUT1
I
IN1
V
IN2
V
OUT2
GND
CS_DIS
I
CSD
V
CSD
INPUT2
I
IN2
V
IN1
SENSE1
OUTPUT2 I
OUT2
CURRENT I
SENSE2
SENSE2
V
SENSE1
V
OUT1
V
Fn
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC
DC supply voltage 41 V
-V
CC
Reverse DC supply voltage 0.3 V
-I
GND
DC reverse ground pin current 200 mA
I
OUT
DC output current Internally limited A
-I
OUT
Reverse DC output current 12 A
I
IN
DC input current -1 to 10 mA
I
CSD
DC current sense disable input current -1 to 10 mA
-I
CSENSE
DC reverse CS pin current 200 mA
V
CSENSE
Current sense maximum voltage V
CC
-41
+V
CC
V
V
E
MAX
Maximum switching energy
(L= 3mH; R
L
=0Ω; V
bat
=13.5V; T
jstart
=150°C; I
OUT
= I
limL
(Typ.))104 mJ
Electrical specifications VND5050AJ-E / VND5050AK-E
8/37 Doc ID 12272 Rev 10
2.2 Thermal data
2.3 Electrical characteristics
8V<V
CC
<36V; -4C<T
j
<150 °C, unless otherwise specified.
V
ESD
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
– Input
Current sense
– CS_DIS
–Output
–V
CC
4000
2000
4000
5000
5000
V
V
V
V
V
V
ESD
Charge device model (CDM-AEC-Q100-011) 750 V
T
j
Junction operating temperature -40 to 150 °C
T
stg
Storage temperature -55 to 150 °C
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 5. Thermal data
Symbol Parameter Value Unit
PowerSSO-12 PowerSSO-24
R
thj-case
Thermal resistance junction case (max)
(with one channel on) 2.7 2.7 °C/W
R
thj-amb
Thermal resistance junction ambient
(max) See Figure 29 See Figure 33 °C/W
Table 6.
Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
Operating supply voltage 4.5 13 36 V
V
USD
Undervoltage shutdown 3.5 4.5 V
V
USDhyst
Undervoltage shutdown
hysteresis 0.5 V
R
ON
On-state resistance
(1)
I
OUT
= 2A; T
j
= 25°C
I
OUT
= 2A; T
j
= 150°C
I
OUT
= 2A; V
CC
= 5V; T
j
= 25°C
50
100
65
mΩ
mΩ
mΩ
V
clamp
Clamp voltage I
S
= 20mA 41 46 52 V
I
S
Supply current
Off-state; V
CC
=13V; T
j
=25°C;
V
IN
=V
OUT
=V
SENSE
=V
CSD
=0V
On-state; V
CC
=13V; V
IN
=5V;
I
OUT
= 0A
2
(2)
3
5
(2)
6
µA
mA
VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 9/37
I
L(off)
Off-state output
current
(1)
V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
= 25°C
V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
= 125°C
0
0
0.01 3
5
µA
V
F
Output - V
CC
diode
voltage
(1)
-I
OUT
=4A; T
j
=150°C 0.7 V
1. For each channel.
2. PowerMOS leakage included.
Table 7. Switching (V
CC
= 13V; T
j
= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
Turn-on delay time R
L
= 6.5Ω (see Figure 8)25µs
t
d(off)
Turn-off delay time R
L
= 6.5Ω (see Figure 8)35µs
dV
OUT
/dt
(on)
Turn-on voltage slope R
L
= 6.5Ω See Figure 21 V/µs
dV
OUT
/dt
(off)
Turn-off voltage slope R
L
= 6.5Ω See Figure 22 V/µs
W
ON
Switching energy losses
during t
won
R
L
= 6.5Ω (see Figure 8)0.24mJ
W
OFF
Switching energy losses
during t
woff
R
L
= 6.5Ω (see Figure 8)0.2mJ
Table 8. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level voltage 0.9 V
I
IL
Low level input current V
IN
= 0.9V 1 µA
V
IH
Input high level voltage 2.1 V
I
IH
High level input current V
IN
= 2.1V 10 µA
V
I(hyst)
Input hysteresis voltage 0.25 V
V
ICL
Input clamp voltage I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
CSDL
CS_DIS low level voltage 0.9 V
I
CSDL
Low level CS_DIS
current V
CSD
= 0.9V 1 µA
V
CSDH
CS_DIS high level
voltage 2.1 V
I
CSDH
High level CS_DIS
current V
CSD
= 2.1V 10 µA
Table 6.
Power section
(continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
CC
Electrical specifications VND5050AJ-E / VND5050AK-E
10/37 Doc ID 12272 Rev 10
V
CSD(hyst)
CS_DIS hysteresis
voltage 0.25 V
V
CSCL
CS_DIS clamp voltage I
CSD
= 1mA
I
CSD
= -1mA
5.5
-0.7
7V
V
Table 9.
Protections and diagnostics
(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short circuit current V
CC
= 13V
5V<V
CC
<36V
12 18 24
24
A
A
I
limL
Short circuit current
during thermal cycling V
CC
=13V; T
R
<T
j
<T
TSD
7A
T
TSD
Shutdown temperature 150 175 200 °C
T
R
Reset temperature
T
RS
+ 1
T
RS
+ 5 °C
T
RS
Thermal reset of
STATUS 135 °C
T
HYST
Thermal hysteresis
(T
TSD
-T
R
)
C
V
DEMAG
Turn-off output voltage
clamp I
OUT
=2A; V
IN
=0; L=6mH V
CC
-41 V
CC
-46 V
CC
-52 V
V
ON
Output voltage drop
limitation
I
OUT
=0.1A;
T
j
= -40°C...+150°C
(see Figure 9)
25 mV
Table 10. Current sense (8V<V
CC
<16V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
0
I
OUT
/I
SENSE
I
OUT
=0.05A;
V
SENSE
=0.5V;V
CSD
=0V;
T
j
= -40°C...150°C 1270 2360 3450
K
1
I
OUT
/I
SENSE
I
OUT
=1A; V
SENSE
=0.5V;V
CSD
=0V;
T
j
= -40°C
T
j
= 25°C...150°C
1470
1570
2020
2020
2610
2470
dK
1
/K
1(1)
Current sense ratio
drift
I
OUT
=1A; V
SENSE
= 0.5V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
-7 +7 %
K
2
I
OUT
/I
SENSE
I
OUT
=2A; V
SENSE
=4V;V
CSD
=0V;
T
j
= -40°C
T
j
= 25°C...150°C
1740
1790
2020
2020
2320
2250
Table 8. Logic input (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
CC
VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 11/37
dK
2
/K
2(1)
Current sense ratio
drift
I
OUT
=2 A; V
SENSE
= 4 V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
-4 +4 %
K
3
I
OUT
/I
SENSE
I
OUT
=4A; V
SENSE
=4V;V
CSD
=0V;
T
j
=-40°C
T
j
=25°C...150°C
1880
1900
2010
2010
2160
2120
dK
3
/K
3(1)
Current sense ratio
drift
I
OUT
=4 A; V
SENSE
= 4 V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
-2 +2 %
I
SENSE0
Analog sense
leakage current
I
OUT
=0A; V
SENSE
=0V;
V
CSD
=5V; V
IN
=0V;
T
j
=-40°C...150°C
V
CSD
=0V; V
IN
=5V;
T
j
=-40°C...150°C
I
OUT
=2A; V
SENSE
=0V;
V
CSD
=5V; V
IN
=5V;
T
j
=-40°C...150°C
0
0
0
1
2
1
µA
µA
µA
I
OL
Openload on-state
current detection
threshold V
IN
= 5V, I
SENSE
= 5 µA 4 20 mA
V
SENSE
Max analog sense
output voltage I
OUT
=4A; V
CSD
=0V 5 V
V
SENSEH
Analog sense
output voltage in
over temperature
condition
V
CC
=13V; R
SENSE
=10KΩ9V
I
SENSEH
Analog sense
output current in
over temperature
condition
V
CC
=13V; V
SENSE
=5V 8 mA
t
DSENSE1H
Delay response
time from falling
edge of CS_DIS
pin
V
SENSE
<4V, 0.5A<Iout<4A
I
SENSE
=90% of I
SENSE
max
(see Figure 4)
50 100 µs
t
DSENSE1L
Delay response
time from rising
edge of CS_DIS
pin
V
SENSE
<4V, 0.5A<Iout<4A
I
SENSE
=10% of I
SENSE
max
(see Figure 4)
520µs
t
DSENSE2H
Delay response
time from rising
edge of INPUT pin
V
SENSE
<4V, 0.5A<Iout<4A
I
SENSE
=90% of I
SENSE
max
(see Figure 4)
80 250 µs
Table 10. Current sense (8V<V
CC
<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
CC bi
Electrical specifications VND5050AJ-E / VND5050AK-E
12/37 Doc ID 12272 Rev 10
Figure 4. Current sense delay characteristics
Δt
DSEN
SE
2H
Delay response
time between rising
edge of output
current and rising
edge of current
sense
V
SENSE
<4V,
I
SENSE
= 90% of I
SENSEMAX,
I
OUT
= 90% of I
OUTMAX
I
OUTMAX
=2A (see Figure 5)
65 µs
t
DSENSE2L
Delay response
time from falling
edge of INPUT pin
V
SENSE
<4V, 0.5A<Iout<4A
I
SENSE
=10% of I
SENSE
max
(see Figure 4)
100 250 µs
1. Parameter guaranteed by design; it is not tested.
Table 10. Current sense (8V<V
CC
<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
SENSE CURRENT
INPUT
LOAD CURRENT
CS_DIS
t
DSENSE2H
t
DSENSE2L
t
DSENSE1L
t
DSENSE1H
‘ A‘DSENSEZH‘ “—M
VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 13/37
Figure 5. Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)
V
IN
I
OUT
I
SENSE
I
OUTMAX
I
SENSEMAX
90% I
SENSEMAX
90% I
OUTMAX
Δ
t
DSENSE2H
t
t
t
low low SENSE
Electrical specifications VND5050AJ-E / VND5050AK-E
14/37 Doc ID 12272 Rev 10
Figure 6. I
OUT
/I
SENSE
vs I
OUT
Figure 7. Maximum current sense ratio drift vs load current
Note: Parameter guaranteed by design; it is not tested.
M in -40°C to 15C
Max -4C to 15C
M in 25°C to 150°C
Max 25°C to 150°C
Typ 25°C
500
1000
1500
2000
2500
3000
12345
I
OUT
(A)
I
OUT
/I
SEN SE
-10
-5
0
5
10
1234
I
OUT
(A)
dk/k(%)
VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 15/37
Figure 8. Switching characteristics
Figure 9. Output voltage drop limitation
Table 11. Truth table
Conditions Input Output Sense (V
CSD
=0V)
(1)
1. If the V
CSD
is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation L
H
L
H
0
Nominal
Over temperature L
H
L
L
0
V
SENSEH
Undervoltage L
H
L
L
0
0
Short circuit to GND
(R
sc
10 mΩ)
L
H
H
L
L
L
0
0 if T
j
< T
TSD
V
SENSEH
if T
j
> T
TSD
Short circuit to V
CC
L
H
H
H
0
< Nominal
Negative output voltage
clamp LL 0
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff
V
on
I
out
V
cc
-V
out
T
j
=150
o
CT
j
=25
o
C
T
j
=-40
o
C
V
on
/R
on(T)
Electrical specifications VND5050AJ-E / VND5050AK-E
16/37 Doc ID 12272 Rev 10
Table 12. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
test pulse
Test levels
(1)
1. The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/pulse
repetition time Delays and
impedance
III IV
1 -75V -100V 5000
pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37V +50V 5000
pulses 0.2 s 5 s 50 µs, 2 Ω
3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 -6V -7V 1 pulse 100 ms, 0.01
Ω
5b
(2)
+65V +87V 1 pulse 400 ms, 2
Ω
Table 13. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004(E)
test pulse
Test level results
(1)
1. The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
III IV
1C C
2a C C
3a C C
3b C C
4C C
5b
(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Table 14. Electrical transient requirements (part 3/3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
EOne or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 17/37
Figure 10. Waveforms
SENSE CURRENT
INPUT
NORMAL OPERATION
UNDERVOLTAGE
V
CC
V
USD
V
USDhyst
INPUT
SENSE CURRENT
LOAD CURRENT
LOAD CURRENT
OVERLOAD OPERATION
INPUT
SENSE CURRENT
T
TSD
T
R
T
j
LOAD CURRENT
INPUT
LOAD VOLTAGE
SENSE CURRENT
LOAD CURRENT
<Nominal <Nominal
SHORT TO V
CC
CS_DIS
CS_DIS
CS_DIS
CS_DIS
T
RS
I
LIMH
I
LIML
V
SENSEH
thermal cycling
power
limitation
current
limitation
SHORTED LOAD NORMAL LOAD
Electrical specifications VND5050AJ-E / VND5050AK-E
18/37 Doc ID 12272 Rev 10
2.4 Electrical characteristics curves
Figure 11. Off-state output current Figure 12. High level input current
Figure 13. Input clamp voltage Figure 14. Input high level
Figure 15. Input low level Figure 16. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.125
0.25
0.375
0.5
0.625
0.75
0.875
1
Iloff (uA)
Off State
Vcc=13V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA)
Vin=2.1V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
5.2
5.4
5.6
5.8
6
6.2
6.4
6.6
6.8
7
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Vhyst (V)
VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 19/37
Figure 17. On-state resistance vs T
case
Figure 18. On-state resistance vs V
CC
Figure 19. Undervoltage shutdown Figure 20. I
LIMH
vs T
case
Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
10
20
30
40
50
60
70
80
90
100
Ron (mOhm)
Iout=2A
Vcc=13V
0 5 10 15 20 25 30 35 40
Vcc (V)
0
10
20
30
40
50
60
70
80
90
100
Ron (mOhm)
Tc= - 40°C
Tc= 25°C
Tc= 125°C
Tc= 150°C
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
16
Vusd (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
5
7.5
10
12.5
15
17.5
20
22.5
25
Ilimh (A)
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
(dVout/dt)on (V/ms)
Vcc=13V
RI=6.5Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
100
200
300
400
500
600
700
800
900
1000
(dVout/dt)off (V/ms)
Vcc=13V
RI=6.5Ohm
Electrical specifications VND5050AJ-E / VND5050AK-E
20/37 Doc ID 12272 Rev 10
Figure 23. STAT_DIS clamp voltage Figure 24. Low level STAT_DIS voltage
Figure 25. High level STAT_DIS voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
Vsdcl(V)
Isd=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
Vsdl(V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
Vsdh(V)
VND5050AJ-E / VND5050AK-E Application information
Doc ID 12272 Rev 10 21/37
3 Application information
Figure 26. Application schematic
Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND
resistor.
1. R
GND
600mV / (I
S(on)max
).
2. R
GND
≥ (−V
CC
) / (-I
GND
)
where -I
GND
is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in R
GND
(when V
CC
<0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND
will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
GND
.
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
μ
C
+5V
V
GND
CS_DIS
INPUT
R
prot
R
prot
CURRENT SENSE
R
SENSE
R
prot
C
EXT
Application information VND5050AJ-E / VND5050AK-E
22/37 Doc ID 12272 Rev 10
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND
=1kΩ) should be inserted in parallel to D
GND
if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
D
ld
is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the V
CC
line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prot
) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-V
CCpeak
/I
latchup
R
prot
(V
OHμC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100V and I
latchup
20mA; V
OHµC
4.5V
5kΩ R
prot
180kΩ.
Recommended values: R
prot
=10kΩ, C
EXT
=10nF.
VND5050AJ-E / VND5050AK-E Application information
Doc ID 12272 Rev 10 23/37
3.4 Maximum demagnetization energy (V
CC
= 13.5V)
Figure 27. Maximum turn-off current versus inductance (for each channel)
Note: Values are generated with R
L
=0 Ω.In case of repetitive pulses, T
jstart
(at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
1
10
100
0,1 1 10 100
L (mH)
I (A)
C:
T
jstart
= 125°C repetitive pulse
A:
T
jstart
= 150°C single pulse
B: T
jstart
= 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
V
IN
, I
L
A
B
C
Package and PCB thermal data VND5050AJ-E / VND5050AK-E
24/37 Doc ID 12272 Rev 10
4 Package and PCB thermal data
4.1 PowerSSO-12™ thermal data
Figure 28. PowerSSO-12™ PC board
Note: Layout condition of R
th
and Z
th
measurements (PCB: Double layer, Thermal Vias, FR4
area= 77 mm x 86 mm,PCB thickness=1.6 mm, Cu thickness=70 μm (front and back side),
Copper areas: from minimum pad lay-out to 8 cm
2
).
Figure 29. R
thj-amb
vs PCB copper area in open box free air condition (one channel
on)
30
35
40
45
50
55
60
65
70
0246810
RTHj_amb(°C/ W)
PCB Cu heatsink area (cm^2)
Pdch) T) =2 4‘ ,i m m Fuchz r: 07 u ,7 Q? m Rs 4%
VND5050AJ-E / VND5050AK-E Package and PCB thermal data
Doc ID 12272 Rev 10 25/37
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse (one
channel on)
Equation 1: pulse calculation formula
where δ = t
P
/T
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-12™
(a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Footprint
8 cm
2
2 cm
2
ZTHδRTH δZTHtp 1δ()+=
Package and PCB thermal data VND5050AJ-E / VND5050AK-E
26/37 Doc ID 12272 Rev 10
Table 15. PowerSSO-12™ thermal parameter
Area/island (cm
2
)Footprint28
R1= R7 (°C/W) 0.7
R2= R8 (°C/W) 2.8
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1= C7 (W.s/°C) 0.001
C2= C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
VND5050AJ-E / VND5050AK-E Package and PCB thermal data
Doc ID 12272 Rev 10 27/37
4.2 PowerSSO-24™ thermal data
Figure 32. PowerSSO-24™ PC board
Note: Layout condition of R
th
and Z
th
measurements (PCB: Double layer, Thermal Vias, FR4
area= 77 mm x 86 mm, PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8 cm
2
).
Figure 33. R
thj-amb
vs PCB copper area in open box free air condition (one channel
on)
30
35
40
45
50
55
0246810
RTHj_amb(°C/W)
PCB Cu heatsink area (cm^2)
27 H (CM!) 1000 100 8cm 10 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (a) 5 mm T. m :2 *i :3 c4 :5 cu m m l; a; a. N in mm T. a as ,7 é m Rx l;
Package and PCB thermal data VND5050AJ-E / VND5050AK-E
28/37 Doc ID 12272 Rev 10
Figure 34. PowerSSO-24™ Thermal impedance junction ambient single pulse (one
channel on)
Equation 2: pulse calculation formula
where δ = t
P
/T
Figure 35. Thermal fitting model of a double channel HSD in PowerSSO-24™
(b)
b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
ZTHδRTH δZTHtp 1δ()+=
VND5050AJ-E / VND5050AK-E Package and PCB thermal data
Doc ID 12272 Rev 10 29/37
Table 16. PowerSSO-24™ thermal parameter
Area/island (cm
2
)Footprint28
R1=R7 (°C/W) 0.4
R2=R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
CW H , E‘LHE
Package and packing information VND5050AJ-E / VND5050AK-E
30/37 Doc ID 12272 Rev 10
5 Package and packing information
5.1 ECOPACK
®
packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-12™
package information
Figure 36. PowerSSO-12™ package dimensions
VND5050AJ-E / VND5050AK-E Package and packing information
Doc ID 12272 Rev 10 31/37
Table 17. PowerSSO-12™ mechanical data
Symbol Millimeters
Min. Typ. Max.
A1.25 1.62
A1 0 0.1
A2 1.10 1.65
B0.23 0.41
C0.19 0.25
D4.8 5.0
E3.8 4.0
e0.8
H5.8 6.2
h 0.25 0.5
L 0.4 1.27
k0° 8°
X1.9 2.5
Y3.6 4.2
ddd 0.1
JWH WHTH rm ‘ ”,me
Package and packing information VND5050AJ-E / VND5050AK-E
32/37 Doc ID 12272 Rev 10
5.3 PowerSSO-24™ package information
Figure 37. PowerSSO-24™ package dimensions
Table 18. PowerSSO-24™ mechanical data
Symbol Millimeters
Min. Typ. Max.
A - 2.45
A2 2.15 2.35
a1 0 0.1
b0.33 0.51
c0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
F2.3
G0.1
H10.1 10.5
VND5050AJ-E / VND5050AK-E Package and packing information
Doc ID 12272 Rev 10 33/37
h0.4
k0° 8°
L0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N10°
X4.1 4.7
Y6.5 7.1
Table 18. PowerSSO-24™ mechanical data (continued)
Symbol Millimeters
Min. Typ. Max.
u-er nmian or had Eoooooc)o\ \\//
Package and packing information VND5050AJ-E / VND5050AK-E
34/37 Doc ID 12272 Rev 10
5.4 PowerSSO-12™ packing information
Figure 38. PowerSSO-12™ tube shipment (no suffix)
Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A1.85
B6.75
C (± 0.1) 0.6
A
C
B
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
VND5050AJ-E / VND5050AK-E Package and packing information
Doc ID 12272 Rev 10 35/37
5.5 PowerSSO-24™ packing information
Figure 40. PowerSS0-24
TM
tube shipment (no suffix)
Figure 41. PowerSSO-24
TM
tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Qty 49
Bulk Qty 1225
Tube length0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
CB
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
REEL DIMENSIONS
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Revision history VND5050AJ-E / VND5050AK-E
36/37 Doc ID 12272 Rev 10
6 Revision history
Table 19. Document revision history
Date Revision Changes
30-Mar-2006 1 Initial release.
14-Apr-2006 2 PowerSSO-24 dimensions table update.
26-Apr-2007 3 Reformatted
Figure 31 title corrected
14-May-2007 4
Table 4: corrected E
MAX
value.
Table 10: added dk1/k1, dk2/k2, dk3/k3, Δt
DSEN
SE
2H
.
Added Figure 5.
Updated Figure 6.
Added Figure 7.
Table 12: Updated test level values III and IV for test pulse 5b and
notes.
Added Section 3.4: Maximum demagnetization energy (VCC =
13.5V).
01-Jun-2007 5 Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-12™, Figure 35: Thermal fitting model of a double channel
HSD in PowerSSO-24™: added notes.
04-Dec-2007 6
Updated Table 10: Current sense (8V<V
CC
<16V):
changed t
DSENSE2H
max value from 300 µs to 250µs.
added I
OL
parameter.
Updated Section 4.1: PowerSSO-12™ thermal data:
Changed Figure 29: Rthj-amb vs PCB copper area in open box free
air condition (one channel on).
Changed Figure 30: PowerSSO-12™ thermal impedance junction
ambient single pulse (one channel on).
Updated Table : :
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
12-Feb-2008 7 Corrected typing error in Table 10: Current sense (8V<V
CC
<16V):
changed I
OL
test condition from V
IN
= 0V to V
IN
= 5V.
16-Jun-2009 8
Table 18: PowerSSO-24™ mechanical data:
Deleted A (min) value
Changed A (max) value from 2.47 to 2.45
Changed A2 (max) value from 2.40 to 2.35
Changed a1 (max) value from 0.075 to 0.1
Added F and k rows
21-Jul-2009 9
Updated Figure 37: PowerSSO-24™ package dimensions.
Updated Table 18: PowerSSO-24™ mechanical data:
Deleted G1 row
Added O, Q, S, T, and U rows
23-Sep-2013 10 Updated Disclaimer.
m
VND5050AJ-E / VND5050AK-E
Doc ID 12272 Rev 10 37/37
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