ATtiny1614/16/17 Datasheet by Microchip Technology

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6‘ MICRDCHIP
ATtiny1614
tinyAVR® 1-series
Introduction
The ATtiny1614 is a member of the tinyAVR® 1-series of microcontrollers, using the AVR® processor with
hardware multiplier, running at up to 20 MHz, with 16 KB Flash, 2 KB of SRAM, and 256 bytes of
EEPROM in a 14-pin package. The tinyAVR® 1-series uses the latest technologies with a flexible, low-
power architecture including Event System and SleepWalking, accurate analog features, and Core
Independent Peripherals. Capacitive touch interfaces with driven shield are supported with the integrated
QTouch® peripheral touch controller.
Attention:  Automotive products are documented in separate data sheets.
Features
• CPU
– AVR® CPU
Running at up to 20 MHz
Single-cycle I/O access
Two-level interrupt controller
Two-cycle hardware multiplier
• Memories
16 KB In-system self-programmable Flash memory
256 bytes EEPROM
2 KB SRAM
Write/erase endurance:
Flash 10,000 cycles
EEPROM 100,000 cycles
Data retention:
40 years at 55°C
• System
Power-on Reset (POR)
Brown-out Detector (BOD)
Clock options:
16/20 MHz low-power internal RC oscillator
32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 1
32.768 kHz external crystal oscillator
External clock input
Single-pin Unified Program and Debug Interface (UPDI)
Three sleep modes:
Idle with all peripherals running for immediate wake-up
• Standby
Configurable operation of selected peripherals
SleepWalking peripherals
Power-Down with full data retention
• Peripherals
One 16-bit Timer/Counter type A (TCA) with dedicated period register and three compare
channels
Two 16-bit Timer/Counter type B (TCB) with input capture
One 12-bit Timer/Counter type D (TCD) optimized for control applications
One 16-bit Real-Time Counter (RTC) running from an external crystal, external clock, or internal
RC oscillator
Watchdog Timer (WDT) with Window mode, with a separate on-chip oscillator
One USART with fractional baud rate generator, auto-baud, and start-of-frame detection
One master/slave Serial Peripheral Interface (SPI)
One Two-Wire Interface (TWI) with dual address match
Philips I2C compatible
Standard mode (Sm, 100 kHz)
Fast mode (Fm, 400 kHz)
Fast mode plus (Fm+, 1 MHz)
Three Analog Comparators (AC) with low propagation delay
Two 10-bit 115 ksps Analog-to-Digital Converters (ADC)
Three 8-bit Digital-to-Analog Converters (DAC) with one external channel
Multiple voltage references (VREF):
• 0.55V
• 1.1V
• 1.5V
• 2.5V
• 4.3V
Event System (EVSYS) for CPU independent and predictable inter-peripheral signaling
Configurable Custom Logic (CCL) with two programmable look-up tables
Automated CRC memory scan
Peripheral Touch Controller (PTC)
Capacitive touch buttons, sliders, wheels and 2D surfaces
Wake-up on touch
Driven shield for improved moisture and noise handling performance
Up to 6 self capacitance channels
Up to 9 mutual capacitance channels
External interrupt on all general purpose pins
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 2
I/O and Packages:
12 programmable I/O lines
14-pin SOIC150
Temperature Ranges:
-40°C to 105°C
-40°C to 125°C
Speed Grades:
0-5 MHz @ 1.8V – 5.5V
0-10 MHz @ 2.7V – 5.5V
0-20 MHz @ 4.5V – 5.5V
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 3
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Silicon Errata and Data Sheet Clarification Document............................................ 11
2. tinyAVR® 1-series Overview....................................................................................12
2.1. Configuration Summary..............................................................................................................12
3. Block Diagram......................................................................................................... 14
4. Pinout...................................................................................................................... 15
4.1. 14-Pin SOIC............................................................................................................................... 15
5. I/O Multiplexing and Considerations........................................................................16
5.1. Multiplexed Signals.................................................................................................................... 16
6. Memories.................................................................................................................17
6.1. Overview.................................................................................................................................... 17
6.2. Memory Map.............................................................................................................................. 18
6.3. In-System Reprogrammable Flash Program Memory................................................................18
6.4. SRAM Data Memory.................................................................................................................. 19
6.5. EEPROM Data Memory............................................................................................................. 19
6.6. User Row....................................................................................................................................19
6.7. Signature Bytes..........................................................................................................................20
6.8. I/O Memory.................................................................................................................................20
6.9. Memory Section Access from CPU and UPDI on Locked Device..............................................21
6.10. Configuration and User Fuses (FUSE).......................................................................................22
7. Peripherals and Architecture................................................................................... 41
7.1. Peripheral Module Address Map................................................................................................41
7.2. Interrupt Vector Mapping............................................................................................................ 42
7.3. System Configuration (SYSCFG)...............................................................................................44
8. AVR CPU.................................................................................................................47
8.1. Features..................................................................................................................................... 47
8.2. Overview.................................................................................................................................... 47
8.3. Architecture................................................................................................................................ 47
8.4. Arithmetic Logic Unit (ALU)........................................................................................................49
8.5. Functional Description................................................................................................................50
8.6. Register Summary - CPU...........................................................................................................55
8.7. Register Description...................................................................................................................55
9. NVMCTRL - Nonvolatile Memory Controller............................................................59
9.1. Features..................................................................................................................................... 59
9.2. Overview.................................................................................................................................... 59
ATtiny1614
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9.3. Functional Description................................................................................................................60
9.4. Register Summary - NVMCTRL................................................................................................. 67
9.5. Register Description...................................................................................................................67
10. CLKCTRL - Clock Controller................................................................................... 75
10.1. Features..................................................................................................................................... 75
10.2. Overview.................................................................................................................................... 75
10.3. Functional Description................................................................................................................77
10.4. Register Summary - CLKCTRL..................................................................................................82
10.5. Register Description...................................................................................................................82
11. SLPCTRL - Sleep Controller................................................................................... 92
11.1. Features..................................................................................................................................... 92
11.2. Overview.................................................................................................................................... 92
11.3. Functional Description................................................................................................................94
11.4. Register Summary - SLPCTRL.................................................................................................. 97
11.5. Register Description...................................................................................................................97
12. RSTCTRL - Reset Controller...................................................................................99
12.1. Features..................................................................................................................................... 99
12.2. Overview.................................................................................................................................... 99
12.3. Functional Description..............................................................................................................100
12.4. Register Summary - RSTCTRL................................................................................................103
12.5. Register Description.................................................................................................................103
13. CPUINT - CPU Interrupt Controller....................................................................... 106
13.1. Features................................................................................................................................... 106
13.2. Overview.................................................................................................................................. 106
13.3. Functional Description..............................................................................................................108
13.4. Register Summary - CPUINT................................................................................................... 115
13.5. Register Description................................................................................................................. 115
14. EVSYS - Event System......................................................................................... 120
14.1. Features................................................................................................................................... 120
14.2. Overview.................................................................................................................................. 120
14.3. Functional Description..............................................................................................................123
14.4. Register Summary - EVSYS.................................................................................................... 125
14.5. Register Description.................................................................................................................125
15. PORTMUX - Port Multiplexer................................................................................ 134
15.1. Overview.................................................................................................................................. 134
15.2. Register Summary - PORTMUX.............................................................................................. 135
15.3. Register Description.................................................................................................................135
16. PORT - I/O Pin Configuration................................................................................ 139
16.1. Features................................................................................................................................... 139
16.2. Overview.................................................................................................................................. 139
16.3. Functional Description..............................................................................................................141
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 5
16.4. Register Summary - PORT...................................................................................................... 145
16.5. Register Description - Ports..................................................................................................... 145
16.6. Register Summary - VPORT....................................................................................................157
16.7. Register Description - Virtual Ports.......................................................................................... 157
17. BOD - Brown-out Detector.....................................................................................162
17.1. Features................................................................................................................................... 162
17.2. Overview.................................................................................................................................. 162
17.3. Functional Description..............................................................................................................164
17.4. Register Summary - BOD.........................................................................................................166
17.5. Register Description.................................................................................................................166
18. VREF - Voltage Reference.................................................................................... 173
18.1. Features................................................................................................................................... 173
18.2. Overview.................................................................................................................................. 173
18.3. Functional Description..............................................................................................................173
18.4. Register Summary - VREF.......................................................................................................175
18.5. Register Description.................................................................................................................175
19. WDT - Watchdog Timer......................................................................................... 180
19.1. Features................................................................................................................................... 180
19.2. Overview.................................................................................................................................. 180
19.3. Functional Description..............................................................................................................182
19.4. Register Summary - WDT........................................................................................................ 186
19.5. Register Description.................................................................................................................186
20. TCA - 16-bit Timer/Counter Type A....................................................................... 190
20.1. Features................................................................................................................................... 190
20.2. Overview.................................................................................................................................. 190
20.3. Functional Description..............................................................................................................194
20.4. Register Summary - TCA in Normal Mode (CTRLD.SPLITM=0)............................................. 204
20.5. Register Description - Normal Mode........................................................................................ 204
20.6. Register Summary - TCA in Split Mode (CTRLD.SPLITM=1)..................................................224
20.7. Register Description - Split Mode.............................................................................................224
21. TCB - 16-bit Timer/Counter Type B....................................................................... 240
21.1. Features................................................................................................................................... 240
21.2. Overview.................................................................................................................................. 240
21.3. Functional Description..............................................................................................................243
21.4. Register Summary - TCB......................................................................................................... 251
21.5. Register Description.................................................................................................................251
22. TCD - 12-Bit Timer/Counter Type D...................................................................... 263
22.1. Features................................................................................................................................... 263
22.2. Overview.................................................................................................................................. 263
22.3. Functional Description..............................................................................................................267
22.4. Register Summary - TCD.........................................................................................................289
22.5. Register Description.................................................................................................................289
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 6
23. RTC - Real-Time Counter......................................................................................309
23.1. Features................................................................................................................................... 309
23.2. Overview.................................................................................................................................. 309
23.3. RTC Functional Description..................................................................................................... 312
23.4. PIT Functional Description....................................................................................................... 312
23.5. Events...................................................................................................................................... 314
23.6. Interrupts.................................................................................................................................. 315
23.7. Sleep Mode Operation............................................................................................................. 315
23.8. Synchronization........................................................................................................................316
23.9. Configuration Change Protection............................................................................................. 316
23.10. Register Summary - RTC.........................................................................................................317
23.11. Register Description................................................................................................................. 317
24. USART - Universal Synchronous and Asynchronous Receiver and Transmitter.. 333
24.1. Features................................................................................................................................... 333
24.2. Overview.................................................................................................................................. 333
24.3. Functional Description..............................................................................................................336
24.4. Register Summary - USART.................................................................................................... 352
24.5. Register Description.................................................................................................................352
25. SPI - Serial Peripheral Interface............................................................................371
25.1. Features................................................................................................................................... 371
25.2. Overview.................................................................................................................................. 371
25.3. Functional Description..............................................................................................................374
25.4. Register Summary - SPI...........................................................................................................384
25.5. Register Description.................................................................................................................384
26. TWI - Two-Wire Interface.......................................................................................391
26.1. Features................................................................................................................................... 391
26.2. Overview.................................................................................................................................. 391
26.3. Functional Description..............................................................................................................393
26.4. Register Summary - TWI..........................................................................................................407
26.5. Register Description.................................................................................................................407
27. CRCSCAN - Cyclic Redundancy Check Memory Scan........................................ 425
27.1. Features................................................................................................................................... 425
27.2. Overview.................................................................................................................................. 425
27.3. Functional Description..............................................................................................................427
27.4. Register Summary - CRCSCAN...............................................................................................430
27.5. Register Description.................................................................................................................430
28. CCL - Configurable Custom Logic.........................................................................434
28.1. Features................................................................................................................................... 434
28.2. Overview.................................................................................................................................. 434
28.3. Functional Description..............................................................................................................436
28.4. Register Summary - CCL......................................................................................................... 445
28.5. Register Description.................................................................................................................445
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 7
29. AC - Analog Comparator....................................................................................... 453
29.1. Features................................................................................................................................... 453
29.2. Overview.................................................................................................................................. 453
29.3. Functional Description..............................................................................................................455
29.4. Register Summary - AC........................................................................................................... 457
29.5. Register Description.................................................................................................................457
30. ADC - Analog-to-Digital Converter........................................................................ 462
30.1. Features................................................................................................................................... 462
30.2. Overview.................................................................................................................................. 462
30.3. Functional Description..............................................................................................................466
30.4. Register Summary - ADCn.......................................................................................................474
30.5. Register Description.................................................................................................................474
31. DAC - Digital-to-Analog Converter........................................................................ 492
31.1. Features................................................................................................................................... 492
31.2. Overview.................................................................................................................................. 492
31.3. Functional Description..............................................................................................................494
31.4. Register Summary - DAC.........................................................................................................496
31.5. Register Description.................................................................................................................496
32. Peripheral Touch Controller (PTC)........................................................................ 499
32.1. Overview.................................................................................................................................. 499
32.2. Features................................................................................................................................... 499
32.3. Block Diagram..........................................................................................................................500
32.4. Signal Description.................................................................................................................... 500
32.5. System Dependencies............................................................................................................. 501
32.6. Functional Description..............................................................................................................502
33. UPDI - Unified Program and Debug Interface....................................................... 504
33.1. Features................................................................................................................................... 504
33.2. Overview.................................................................................................................................. 504
33.3. Functional Description..............................................................................................................507
33.4. Register Summary - UPDI........................................................................................................527
33.5. Register Description.................................................................................................................527
34. Instruction Set Summary....................................................................................... 538
35. Conventions...........................................................................................................543
35.1. Numerical Notation...................................................................................................................543
35.2. Memory Size and Type.............................................................................................................543
35.3. Frequency and Time.................................................................................................................543
35.4. Registers and Bits.................................................................................................................... 544
36. Acronyms and Abbreviations.................................................................................545
37. Electrical Characteristics ...................................................................................... 548
37.1. Disclaimer.................................................................................................................................548
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 8
37.2. Absolute Maximum Ratings .....................................................................................................548
37.3. General Operating Ratings ......................................................................................................549
37.4. Power Consumption for ATtiny1614.........................................................................................550
37.5. Wake-Up Time..........................................................................................................................551
37.6. Power Consumption of Peripherals..........................................................................................552
37.7. BOD and POR Characteristics.................................................................................................553
37.8. External Reset Characteristics.................................................................................................554
37.9. Oscillators and Clocks..............................................................................................................554
37.10. I/O Pin Characteristics............................................................................................................. 556
37.11. USART..................................................................................................................................... 557
37.12. SPI........................................................................................................................................... 558
37.13. TWI...........................................................................................................................................559
37.14. VREF........................................................................................................................................561
37.15. ADC..........................................................................................................................................562
37.16. DAC..........................................................................................................................................564
37.17. AC............................................................................................................................................ 565
37.18. PTC..........................................................................................................................................566
37.19. UPDI Timing.............................................................................................................................567
37.20. Programming Time...................................................................................................................567
38. Typical Characteristics...........................................................................................569
38.1. Power Consumption.................................................................................................................569
38.2. GPIO........................................................................................................................................ 576
38.3. VREF Characteristics...............................................................................................................584
38.4. BOD Characteristics.................................................................................................................586
38.5. ADC Characteristics.................................................................................................................589
38.6. AC Characteristics....................................................................................................................594
38.7. OSC20M Characteristics..........................................................................................................598
38.8. OSCULP32K Characteristics................................................................................................... 600
39. Ordering Information..............................................................................................601
39.1. Product Information..................................................................................................................601
39.2. Product Identification System...................................................................................................601
40. Package Drawings.................................................................................................602
40.1. Online Package Drawings........................................................................................................602
40.2. 14-Pin SOIC150....................................................................................................................... 603
41. Thermal Considerations........................................................................................ 607
41.1. Thermal Resistance Data.........................................................................................................607
41.2. Junction Temperature...............................................................................................................607
42. Errata.....................................................................................................................608
42.1. Errata - ATtiny1614.................................................................................................................. 608
43. Data Sheet Revision History..................................................................................609
43.1. Rev. B - 07/2019.......................................................................................................................609
43.2. Rev. A - 06/2018.......................................................................................................................610
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 9
The Microchip Website................................................................................................ 611
Product Change Notification Service...........................................................................611
Customer Support........................................................................................................611
Microchip Devices Code Protection Feature............................................................... 611
Legal Notice.................................................................................................................612
Trademarks................................................................................................................. 612
Quality Management System...................................................................................... 613
Worldwide Sales and Service......................................................................................614
ATtiny1614
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 10
1. Silicon Errata and Data Sheet Clarification Document
Our intention is to provide our customers with the best documentation possible to ensure successful use
of Microchip products. Between data sheet updates, a Silicon Errata and Data Sheet Clarification
Document will contain the most recent information for the data sheet. The ATtiny1614 Silicon Errata and
Data Sheet Clarification Document is available at the device product page on https://www.microchip.com.
ATtiny1614
Silicon Errata and Data Sheet Clarification ...
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 11
2. tinyAVR® 1-series Overview
The figure below shows the tinyAVR® 1-series devices, laying out pin count variants and memory sizes:
Vertical migration upwards is possible without code modification, as these devices are pin compatible
and provide the same or more features. Downward migration may require code modification due to
fewer available instances of some peripherals.
Horizontal migration to the left reduces the pin count and therefore, the available features.
Figure 2-1. tinyAVR® 1-series Overview
48 KB
32 KB
16 KB
8 KB
4 KB
2 KB
8 14 20 24 Pins
Flash
ATtiny816 ATtiny817ATtiny814
ATtiny417
ATtiny1616 ATtiny1617
ATtiny414 ATtiny416
ATtiny412
ATtiny214
ATtiny212
ATtiny1614
ATtiny3216 ATtiny3217
devices ATtiny~~
ATtiny~~
Legend:
common data sheet
Devices with different Flash memory size typically also have different SRAM and EEPROM.
Related Links
6. Memories
2.1 Configuration Summary
2.1.1 Peripheral Summary
Table 2-1. Peripheral Summary
ATtiny1614
Pins 14
SRAM 2 KB
Flash 16 KB
EEPROM 256B
Max. frequency (MHz) 20
16-bit Timer/Counter type A (TCA) 1
ATtiny1614
tinyAVR® 1-series Overview
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 12
...........continued
ATtiny1614
16-bit Timer/Counter type B (TCB) 2
12-bit Timer/Counter type D (TCD) 1
Real-Time Counter (RTC) 1
USART 1
SPI 1
TWI (I2C) 1
ADC 2
ADC channels 10+4
DAC 3
AC 3
Peripheral Touch Controller (PTC)(1) 1
PTC number of self capacitance channels(1) 6XY
PTC number of mutual capacitance channels(1) 9
Configurable Custom Logic 1
Window Watchdog 1
Event System channels 6
General purpose I/O 12
External interrupts 12
CRCSCAN 1
Note: 
1. The PTC takes control over the ADC0 while the PTC is used.
ATtiny1614
tinyAVR® 1-series Overview
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 13
mm “.5 m mm m mm m n m m a m“ K 9 mm mm o m R rm u F Vc A w: D d M m 5 U B a / RESET
3. Block Diagram
Figure 3-1. ATtiny1614 Block Diagram
I
N
/
O
U
T
D
A
T
A
B
U
S
Clock generation
BUS Matrix
CPU
USART0
SPI0
CCL
AC [2:0]
ADC0 / PTC
TCA0
TCB[1:0]
AINP[2:0]
AINN[1:0]
OUT
WO[5:0]
RXD
TXD
XCK
XDIR
MISO
MOSI
SCK
SS
PORTS
System
Management
SLPCTRL
RSTCTRL
CLKCTRL
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
UPDI CRC
SRAM
NVMCTRL
Flash
EEPROM
OSC20M
OSC32K
Detectors/
References
POR
Bandgap
WDT
RTC
CPUINT
M M
S
M
S
S
OCD
RST
S
EXTCLK
LUT0-IN[2:0]
LUTn-OUT
WO
PA[7:0]
PB[3:0]
GPIOR
TWI0
SDA
SCL
TCD0
WO[A,B]
XOSC32K
TOSC2
TOSC1
To
detectors
UPDI / RESET
EVSYS EVOUT[n:0]
DAC
DAC0 OUT [2:0]
ADC1
VLM
BOD
EXTCLK
AIN[11:10, 7:0]
X[5:0]
Y[5:0]
REFA
AIN[3:0]
analog peripherals
analog peripherals
analog peripherals
digital peripherals
analog peripherals
core components
clocks/generators
®
ATtiny1614
Block Diagram
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 14
BI- LL HUGE O/RESET/
4. Pinout
4.1 14-Pin SOIC
1
2
3
4
5
6
7 8
9
13
10
11
12
14VDD GND
PA1
PA2
PA4
PA5
PA7
PA6
PB0
PB1
PA3/EXTCLK
TOSC
2
/PB3
TOSC
1
/PB2
PA0/RESET/UPDI
GPIO VDD power domain
Clock, crystal
Programming, Debug, ResetInput supply
Ground
Analog function
Digital function only
ATtiny1614
Pinout
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 15
5. I/O Multiplexing and Considerations
5.1 Multiplexed Signals
Table 5-1. PORT Function Multiplexing
SOIC 14-Pin
Pin Name (1,2) Other/Special ADC0 ADC1 PTC(4) AC0 AC1 AC2 DAC0 USART0 SPI0 TWI0 TCA0 TCBn TCD0 CCL
10 PA0 RESET/ UPDI AIN0 LUT0-IN0
11 PA1 AIN1 TxD(3) MOSI SDA(3) LUT0-IN1
12 PA2 EVOUT0 AIN2 RxD(3) MISO SCL(3) LUT0-IN2
13 PA3 EXTCLK AIN3 XCK(3) SCK WO3 TCB1 WO
14 GND
1 VDD
2 PA4 AIN4 AIN0 X0/Y0 XDIR(3) SS WO4 WOA LUT0-OUT
3 PA5 VREFA AIN5 AIN1 X1/Y1 OUT AINN0 WO5 TCB0 WO WOB
4 PA6 AIN6 AIN2 X2/Y2 AINN0 AINP1 AINP0 OUT
5 PA7 AIN7 AIN3 X3/Y3 AINP0 AINP0 AINN0 LUT1-OUT
6 PB3 TOSC1 OUT RxD WO0(3)
7 PB2 TOSC2, EVOUT1 OUT TxD WO2
8 PB1 AIN10 X4/Y4 AINP2 XCK SDA WO1
9 PB0 AIN11 X5/Y5 AINP2 AINP1 XDIR SCL WO0
Note: 
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. Notation
for signals is PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full
asynchronous detection.
3. Alternate pin positions. For selecting the alternate positions, refer to the PORTMUX documentation.
4. Every PTC line can be configured as X- or Y-line.
ATtiny1614
I/O Multiplexing and Considerations
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 16
6. Memories
6.1 Overview
The main memories are SRAM data memory, EEPROM data memory, and Flash program memory. In
addition, the peripheral registers are located in the I/O memory space.
Table 6-1. Physical Properties of EEPROM
Property ATtiny1614
Size 256 bytes
Page size 32 bytes
Number of pages 8
Start address 0x1400
Table 6-2. Physical Properties of SRAM
Property ATtiny1614
Size 2 KB
Start address 0x3800
Table 6-3. Physical Properties of Flash Memory
Property ATtiny1614
Size 16 KB
Page size 64 bytes
Number of pages 256
Start address 0x8000
Related Links
6.2 Memory Map
6.5 EEPROM Data Memory
6.4 SRAM Data Memory
6.3 In-System Reprogrammable Flash Program Memory
9. NVMCTRL - Nonvolatile Memory Controller
ATtiny1614
Memories
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 17
6.2 Memory Map
Figure 6-1. Memory Map ATtiny1614
(Reserved)
(Reserved)
NVM I/O Registers and Data
64 I/O Registers
960 Ext I/O Registers
0x0000 –
0x003F
0x0040 –
0x0FFF
Internal SRAM
2KB
EEPROM 256 bytes
0x8000 -
BOOTEND
0x1000 –
0x13FF
0x3800
0x3FFF
0x1400 –
0x14FF
0xBFFF
Application
Code
App Data
APPEND
Flash
16KB
(Reserved)
Boot
0xFFFF
6.3 In-System Reprogrammable Flash Program Memory
The ATtiny1614 contains 16 KB on-chip in-system reprogrammable Flash memory for program storage.
Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For write protection,
the Flash program memory space can be divided into three sections (see the illustration below):
Bootloader section, application code section, and application data section, with restricted access rights
among them.
The Program Counter (PC) is 13 bits wide to address the whole program memory. The procedure for
writing Flash memory is described in detail in the documentation of the Nonvolatile Memory Controller
(NVMCTRL) peripheral.
The entire Flash memory is mapped in the memory space and is accessible with normal LD/ST
instructions as well as the LPM instruction. For LD/ST instructions, the Flash is mapped from address
0x8000. For the LPM instruction, the Flash start address is 0x0000.
The ATtiny1614 also has a CRC peripheral that is a master on the bus.
ATtiny1614
Memories
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 18
FLASHSTART: OXBDDO FLASHEND
Figure 6-2. Flash and the Three Sections
FLASHSTART: 0x8000
BOOTEND>0: 0x8000+BOOTEND*256
BO OT
APPEND>0: 0x8000+APPEND*256
AP PL ICA TIO N
CO DE
AP PL ICA TIO N
DA TA
FLASH
FLASHEND
Related Links
2.1 Configuration Summary
9. NVMCTRL - Nonvolatile Memory Controller
6.4 SRAM Data Memory
The 2 KB SRAM is used for data storage and stack.
Related Links
8. AVR CPU
8.5.4 Stack and Stack Pointer
6.5 EEPROM Data Memory
The ATtiny1614 has 256 bytes of EEPROM data memory, see Memory Map section. The EEPROM
memory supports single byte read and write. The EEPROM is controlled by the Nonvolatile Memory
Controller (NVMCTRL).
Related Links
6.2 Memory Map
9. NVMCTRL - Nonvolatile Memory Controller
17. BOD - Brown-out Detector
6.6 User Row
In addition to the EEPROM, the ATtiny1614 has one extra page of EEPROM memory that can be used
for firmware settings, the User Row (USERROW). This memory supports single byte read and write as
the normal EEPROM. The CPU can write and read this memory as normal EEPROM and the UPDI can
write and read it as a normal EEPROM memory if the part is unlocked. The User Row can be written by
the UPDI when the part is locked. USERROW is not affected by a chip erase.
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Related Links
6.2 Memory Map
9. NVMCTRL - Nonvolatile Memory Controller
33. UPDI - Unified Program and Debug Interface
6.7 Signature Bytes
All ATtiny microcontrollers have a 3-byte signature code that identifies the device. The three bytes reside
in a separate address space. For the device, the signature bytes are given in the following table.
Note:  When the device is locked, only the System Information Block (SIB) can be obtained.
Table 6-4. Device ID
Device Name Signature Bytes Address
0x00 0x01 0x02
ATtiny1614 0x1E 0x94 0x22
Related Links
33.3.6 System Information Block
6.8 I/O Memory
All ATtiny1614 I/Os and peripherals are located in the I/O memory space. The I/O address range from
0x00 to 0x3F can be accessed in a single cycle using IN and OUT instructions. The extended I/O memory
space from 0x0040 - 0x0FFF can be accessed by the LD/LDS/LDD and ST/STS/STD instructions,
transferring data between the 32 general purpose working registers and the I/O memory space.
I/O registers within the address range 0x00 - 0x1F are directly bit accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC
instructions. Refer to the Instruction Set section for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O
memory addresses should never be written.
Some of the interrupt flags are cleared by writing a '1' to them. On ATtiny1614 devices, the CBI and SBI
instructions will only operate on the specified bit and can be used on registers containing such interrupt
flags. The CBI and SBI instructions work with registers 0x00 - 0x1F only.
General Purpose I/O Registers
The ATtiny1614 devices provide four general purpose I/O registers. These registers can be used for
storing any information, and they are particularly useful for storing global variables and interrupt flags.
General purpose I/O registers, which reside in the address range 0x1C - 0x1F, are directly bit accessible
using the SBI, CBI, SBIS, and SBIC instructions.
Related Links
6.2 Memory Map
34. Instruction Set Summary
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6.9 Memory Section Access from CPU and UPDI on Locked Device
The device can be locked so that the memories cannot be read using the UPDI. The locking protects both
the Flash (all BOOT, APPCODE, and APPDATA sections), SRAM, and the EEPROM including the FUSE
data. This prevents successful reading of application data or code using the debugger interface. Regular
memory access from within the application still is enabled.
The device is locked by writing any non-valid value to the LOCKBIT bit field in FUSE.LOCKBIT.
Table 6-5. Memory Access in Unlocked Mode (FUSE.LOCKBIT Valid)(1)
Memory Section CPU Access UPDI Access
Read Write Read Write
SRAM Yes Yes Yes Yes
Registers Yes Yes Yes Yes
Flash Yes Yes Yes Yes
EEPROM Yes Yes Yes Yes
USERROW Yes Yes Yes Yes
SIGROW Yes No Yes No
Other Fuses Yes No Yes Yes
Table 6-6. Memory Access in Locked Mode (FUSE.LOCKBIT Invalid)(1)
Memory Section CPU Access UPDI Access
Read Write Read Write
SRAM Yes Yes No No
Registers Yes Yes No No
Flash Yes Yes No No
EEPROM Yes No No No
USERROW Yes Yes No Yes(2)
SIGROW Yes No No No
Other Fuses Yes No No No
Note: 
1. Read operations marked No in the tables may appear to be successful, but the data is corrupt.
Hence, any attempt of code validation through the UPDI will fail on these memory sections.
2. In Locked mode, the USERROW can be written blindly using the fuse Write command, but the
current USERROW values cannot be read out.
Important:  The only way to unlock a device is a CHIPERASE, which will erase all device
memories to factory default so that no application data is retained.
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Related Links
6.10.3 Fuse Summary - FUSE
6.10.4.9 LOCKBIT
33. UPDI - Unified Program and Debug Interface
33.3.7 Enabling of KEY Protected Interfaces
6.10 Configuration and User Fuses (FUSE)
Fuses are part of the nonvolatile memory and hold factory calibration data and device configuration. The
fuses are available from device power-up. The fuses can be read by the CPU or the UPDI, but can only
be programmed or cleared by the UPDI. The configuration and calibration values stored in the fuses are
written to their respective target registers at the end of the start-up sequence.
The content of the Signature Row fuses (SIGROW) is pre-programmed and cannot be altered. SIGROW
holds information such as device ID, serial number, and calibration values.
The fuses for peripheral configuration (FUSE) are pre-programmed but can be altered by the user.
Altered values in the configuration fuse will be effective only after a Reset.
Note:  When writing the fuses write all reserved bits to ‘1’.
This device provides a User Row fuse area (USERROW) that can hold application data. The USERROW
can be programmed on a locked device by the UPDI. This can be used for final configuration without
having programming or debugging capabilities enabled.
Related Links
6.10.1 SIGROW - Signature Row Summary
6.10.3 Fuse Summary - FUSE
7.1 Peripheral Module Address Map
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6.10.1 SIGROW - Signature Row Summary
Offset Name Bit Pos.
0x00 DEVICEID0 7:0 DEVICEID[7:0]
0x01 DEVICEID1 7:0 DEVICEID[7:0]
0x02 DEVICEID2 7:0 DEVICEID[7:0]
0x03 SERNUM0 7:0 SERNUM[7:0]
0x04 SERNUM1 7:0 SERNUM[7:0]
0x05 SERNUM2 7:0 SERNUM[7:0]
0x06 SERNUM3 7:0 SERNUM[7:0]
0x07 SERNUM4 7:0 SERNUM[7:0]
0x08 SERNUM5 7:0 SERNUM[7:0]
0x09 SERNUM6 7:0 SERNUM[7:0]
0x0A SERNUM7 7:0 SERNUM[7:0]
0x0B SERNUM8 7:0 SERNUM[7:0]
0x0C SERNUM9 7:0 SERNUM[7:0]
0x0D
...
0x1F
Reserved
0x20 TEMPSENSE0 7:0 TEMPSENSE[7:0]
0x21 TEMPSENSE1 7:0 TEMPSENSE[7:0]
0x22 OSC16ERR3V 7:0 OSC16ERR3V[7:0]
0x23 OSC16ERR5V 7:0 OSC16ERR5V[7:0]
0x24 OSC20ERR3V 7:0 OSC20ERR3V[7:0]
0x25 OSC20ERR5V 7:0 OSC20ERR5V[7:0]
6.10.2 Signature Row Description
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6.10.2.1 Device ID n
Name:  DEVICEIDn
Offset:  0x00 + n*0x01 [n=0..2]
Reset:  [Device ID]
Property:  -
Each device has a device ID identifying the device and its properties; such as memory sizes, pin count,
and die revision. This can be used to identify a device and hence, the available features by software. The
Device ID consists of three bytes: SIGROW.DEVICEID[2:0].
Bit 7 6 5 4 3 2 1 0
DEVICEID[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Bits 7:0 – DEVICEID[7:0] Byte n of the Device ID
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6.10.2.2 Serial Number Byte n
Name:  SERNUMn
Offset:  0x03 + n*0x01 [n=0..9]
Reset:  [device serial number]
Property:  -
Each device has an individual serial number, representing a unique ID. This can be used to identify a
specific device in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].
Bit 7 6 5 4 3 2 1 0
SERNUM[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Bits 7:0 – SERNUM[7:0] Serial Number Byte n
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6.10.2.3 Temperature Sensor Calibration n
Name:  TEMPSENSEn
Offset:  0x20 + n*0x01 [n=0..1]
Reset:  [Temperature sensor calibration value]
Property:  -
These registers contain correction factors for temperature measurements by the ADC.
SIGROW.TEMPSENSE0 is a correction factor for the gain/slope (unsigned), SIGROW.TEMPSENSE1 is
a correction factor for the offset (signed).
Bit 7 6 5 4 3 2 1 0
TEMPSENSE[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Bits 7:0 – TEMPSENSE[7:0] Temperature Sensor Calibration Byte n
Refer to the ADC chapter for a description on how to use this register.
Related Links
30.3.2.6 Temperature Measurement
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6.10.2.4 OSC16 Error at 3V
Name:  OSC16ERR3V
Offset:  0x22
Reset:  [Oscillator frequency error value]
Property:  -
Bit 7 6 5 4 3 2 1 0
OSC16ERR3V[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Bits 7:0 – OSC16ERR3V[7:0] OSC16 Error at 3V
These registers contain the signed oscillator frequency error value when running at internal 16 MHz at 3V,
as measured during production.
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6.10.2.5 OSC16 Error at 5V
Name:  OSC16ERR5V
Offset:  0x23
Reset:  [Oscillator frequency error value]
Property:  -
Bit 7 6 5 4 3 2 1 0
OSC16ERR5V[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Bits 7:0 – OSC16ERR5V[7:0] OSC16 Error at 5V
These registers contain the signed oscillator frequency error value when running at internal 16 MHz at 5V,
as measured during production.
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6.10.2.6 OSC20 Error at 3V
Name:  OSC20ERR3V
Offset:  0x24
Reset:  [Oscillator frequency error value]
Property:  -
Bit 7 6 5 4 3 2 1 0
OSC20ERR3V[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Bits 7:0 – OSC20ERR3V[7:0] OSC20 Error at 3V
These registers contain the signed oscillator frequency error value when running at internal 20 MHz at 3V,
as measured during production.
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6.10.2.7 OSC20 Error at 5V
Name:  OSC20ERR5V
Offset:  0x25
Reset:  [Oscillator frequency error value]
Property:  -
Bit 7 6 5 4 3 2 1 0
OSC20ERR5V[7:0]
Access R R R R R R R R
Reset x x x x x x x x
Bits 7:0 – OSC20ERR5V[7:0] OSC20 Error at 5V
These registers contain the signed oscillator frequency error value when running at internal 20 MHz at 5V,
as measured during production.
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6.10.3 Fuse Summary - FUSE
Offset Name Bit Pos.
0x00 WDTCFG 7:0 WINDOW[3:0] PERIOD[3:0]
0x01 BODCFG 7:0 LVL[2:0] SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
0x02 OSCCFG 7:0 OSCLOCK FREQSEL[1:0]
0x03 Reserved
0x04 TCD0CFG 7:0 CMPDEN CMPCEN CMPBEN CMPAEN CMPD CMPC CMPB CMPA
0x05 SYSCFG0 7:0 CRCSRC[1:0] RESERVED RSTPINCFG[1:0] RESERVED EESAVE
0x06 SYSCFG1 7:0 SUT[2:0]
0x07 APPEND 7:0 APPEND[7:0]
0x08 BOOTEND 7:0 BOOTEND[7:0]
0x09 Reserved
0x0A LOCKBIT 7:0 LOCKBIT[7:0]
6.10.4 Fuse Description
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6.10.4.1 Watchdog Configuration
Name:  WDTCFG
Offset:  0x00
Reset:  -
Property:  -
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PERIOD[3:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 7:4 – WINDOW[3:0] Watchdog Window Time-out Period
This value is loaded into the WINDOW bit field of the Watchdog Control A register (WDT.CTRLA) during
Reset.
Bits 3:0 – PERIOD[3:0] Watchdog Time-out Period
This value is loaded into the PERIOD bit field of the Watchdog Control A register (WDT.CTRLA) during
Reset.
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6.10.4.2 BOD Configuration
Name:  BODCFG
Offset:  0x01
Reset:  -
Property:  -
The settings of the BOD will be reloaded from this Fuse after a Power-on Reset. For all other Resets, the
BOD configuration remains unchanged.
Bit 7 6 5 4 3 2 1 0
LVL[2:0] SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 7:5 – LVL[2:0] BOD Level
This value is loaded into the LVL bit field of the BOD Control B register (BOD.CTRLB) during Reset.
Value Name Description
0x0 BODLEVEL0 1.8V
0x2 BODLEVEL2 2.6V
0x7 BODLEVEL7 4.2V
Note: 
Values in the description are typical values.
Refer to the BOD and POR Characteristics in Electrical Characteristics for maximum and minimum
values.
Bit 4 – SAMPFREQ BOD Sample Frequency
This value is loaded into the SAMPFREQ bit of the BOD Control A register (BOD.CTRLA) during Reset.
Value Description
0x0 Sample frequency is 1 kHz
0x1 Sample frequency is 125 Hz
Bits 3:2 – ACTIVE[1:0] BOD Operation Mode in Active and Idle
This value is loaded into the ACTIVE bit field of the BOD Control A register (BOD.CTRLA) during Reset.
Value Description
0x0 Disabled
0x1 Enabled
0x2 Sampled
0x3 Enabled with wake-up halted until BOD is ready
Bits 1:0 – SLEEP[1:0] BOD Operation Mode in Sleep
This value is loaded into the SLEEP bit field of the BOD Control A register (BOD.CTRLA) during Reset.
Value Description
0x0 Disabled
0x1 Enabled
0x2 Sampled
0x3 Reserved
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6.10.4.3 Oscillator Configuration
Name:  OSCCFG
Offset:  0x02
Reset:  -
Property:  -
Bit 7 6 5 4 3 2 1 0
OSCLOCK FREQSEL[1:0]
Access R R R
Reset 0 1 0
Bit 7 – OSCLOCK Oscillator Lock
This fuse bit is loaded to LOCK in CLKCTRL.OSC20MCALIBB during Reset.
Value Description
0Calibration registers of the 20 MHz oscillator are accessible
1Calibration registers of the 20 MHz oscillator are locked
Bits 1:0 – FREQSEL[1:0] Frequency Select
These bits select the operation frequency of the 16/20 MHz internal oscillator (OSC20M) and determine
the respective factory calibration values to be written to CAL20M in CLKCTRL.OSC20MCALIBA and
TEMPCAL20M in CLKCTRL.OSC20MCALIBB.
Value Description
0x1 Run at 16 MHz with corresponding factory calibration
0x2 Run at 20 MHz with corresponding factory calibration
Other Reserved
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6.10.4.4 Timer Counter Type D Configuration
Name:  TCD0CFG
Offset:  0x04
Reset:  -
Property:  -
The bit values of this fuse register are written to the corresponding bits in the TCD.FAULTCTRL register
of TCD0 at start-up.
The CMPEN and CMP settings of the TCD will only be reloaded from the FUSE values after a Power-on
Reset. For all other resets, the corresponding TCD settings of the device will remain unchanged.
Bit 7 6 5 4 3 2 1 0
CMPDEN CMPCEN CMPBEN CMPAEN CMPD CMPC CMPB CMPA
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 4, 5, 6, 7 – CMPEN Compare x Enable
Value Description
0Compare x output on Pin is disabled
1Compare x output on Pin is enabled
Bits 0, 1, 2, 3 – CMP Compare x
This bit selects the default state of Compare x after Reset, or when entering debug if FAULTDET is '1'.
Value Description
0Compare x default state is 0
1Compare x default state is 1
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6.10.4.5 System Configuration 0
Name:  SYSCFG0
Offset:  0x05
Reset:  -
Property:  -
Bit 7 6 5 4 3 2 1 0
CRCSRC[1:0] RESERVED RSTPINCFG[1:0] RESERVED EESAVE
Access R R R R R R R
Reset 1 1 1 0 1 1 0
Bits 7:6 – CRCSRC[1:0] CRC Source
See the CRC description for more information about the functionality.
Value Name Description
0x0 FLASH CRC of full Flash (boot, application code and application data)
0x1 BOOT CRC of the boot section
0x2 BOOTAPP CRC of application code and boot sections
0x3 NOCRC No CRC
Bit 5 – RESERVED
Bits 3:2 – RSTPINCFG[1:0] Reset Pin Configuration
These bits select the Reset/UPDI pin configuration.
Value Description
0x0 GPIO
0x1 UPDI
0x2 RESET
Other Reserved
Note:  When configuring the Reset Pin as GPIO, there is a potential conflict between the GPIO actively
driving the output, and a 12V UPDI enable sequence initiation. To avoid this, the GPIO output driver is
disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this
period.
Bit 1 – RESERVED
Bit 0 – EESAVE EEPROM Save during chip erase
Note:  If the device is locked, the EEPROM is always erased by a chip erase, regardless of this bit.
Value Description
0EEPROM erased during chip erase
1EEPROM not erased under chip erase
Related Links
27. CRCSCAN - Cyclic Redundancy Check Memory Scan
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6.10.4.6 System Configuration 1
Name:  SYSCFG1
Offset:  0x06
Reset:  -
Property:  -
Bit 7 6 5 4 3 2 1 0
SUT[2:0]
Access R R R
Reset 1 1 1
Bits 2:0 – SUT[2:0] Start-Up Time Setting
These bits select the start-up time between power-on and code execution.
Value Description
0x0 0 ms
0x1 1 ms
0x2 2 ms
0x3 4 ms
0x4 8 ms
0x5 16 ms
0x6 32 ms
0x7 64 ms
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6.10.4.7 Application Code End
Name:  APPEND
Offset:  0x07
Reset:  -
Property:  -
Bit 7 6 5 4 3 2 1 0
APPEND[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – APPEND[7:0] Application Code Section End
These bits set the end of the application code section in blocks of 256 bytes. The end of the application
code section should be set as BOOT size plus application code size. The remaining Flash will be
application data. A value of 0x00 defines the Flash from BOOTEND*256 to end of Flash as application
code. When both FUSE.APPEND and FUSE.BOOTEND are 0x00, the entire Flash is BOOT section.
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6.10.4.8 Boot End
Name:  BOOTEND
Offset:  0x08
Reset:  -
Property:  -
Bit 7 6 5 4 3 2 1 0
BOOTEND[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – BOOTEND[7:0] Boot Section End
These bits set the end of the boot section in blocks of 256 bytes. A value of 0x00 defines the whole Flash
as BOOT section. When both FUSE.APPEND and FUSE.BOOTEND are 0x00, the entire Flash is BOOT
section.
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6.10.4.9 Lockbits
Name:  LOCKBIT
Offset:  0x0A
Reset:  -
Property:  -
Bit 7 6 5 4 3 2 1 0
LOCKBIT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – LOCKBIT[7:0] Lockbits
When the part is locked, UPDI cannot access the system bus, so it cannot read out anything but CS-
space.
Value Description
0xC5 Valid key - the device is open
other Invalid - the device is locked
Related Links
6.9 Memory Section Access from CPU and UPDI on Locked Device
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7. Peripherals and Architecture
7.1 Peripheral Module Address Map
The address map shows the base address for each peripheral. For complete register description and
summary for each peripheral module, refer to the respective module chapters.
Table 7-1. Peripheral Module Address Map
Base Address Name Description
0x0000 VPORTA Virtual Port A
0x0004 VPORTB Virtual Port B
0x001C GPIO General Purpose I/O registers
0x0030 CPU CPU
0x0040 RSTCTRL Reset Controller
0x0050 SLPCTRL Sleep Controller
0x0060 CLKCTRL Clock Controller
0x0080 BOD Brown-Out Detector
0x00A0 VREF Voltage Reference
0x0100 WDT Watchdog Timer
0x0110 CPUINT Interrupt Controller
0x0120 CRCSCAN Cyclic Redundancy Check Memory Scan
0x0140 RTC Real-Time Counter
0x0180 EVSYS Event System
0x01C0 CCL Configurable Custom Logic
0x0200 PORTMUX Port Multiplexer
0x0400 PORTA Port A Configuration
0x0420 PORTB Port B Configuration
0x0600 ADC0 Analog-to-Digital Converter
0x0640 ADC1 Analog-to-Digital Converter instance 1
0x0680 AC0 Analog Comparator 0
0x0688 AC1 Analog Comparator 1
0x0690 AC2 Analog Comparator 2
0x06A0 DAC0 Digital-to-Analog Converter 0
0x06A8 DAC1 Digital-to-Analog Converter 1
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...........continued
Base Address Name Description
0x06B0 DAC2 Digital-to-Analog Converter 2
0x0800 USART0 Universal Synchronous Asynchronous Receiver Transmitter
0x0810 TWI0 Two-Wire Interface
0x0820 SPI0 Serial Peripheral Interface
0x0A00 TCA0 Timer/Counter Type A instance 0
0x0A40 TCB0 Timer/Counter Type B instance 0
0x0A50 TCB1 Timer/Counter Type B 1
0x0A80 TCD0 Timer/Counter Type D instance 0
0x0F00 SYSCFG System Configuration
0x1000 NVMCTRL Nonvolatile Memory Controller
0x1100 SIGROW Signature Row
0x1280 FUSES Device-specific fuses
0x1300 USERROW User Row
7.2 Interrupt Vector Mapping
Each of the interrupt vectors is connected to one peripheral instance, as shown in the table below. A
peripheral can have one or more interrupt sources, see the Interrupt section in the Functional description
of the respective peripheral for more details on the available interrupt sources.
When the interrupt condition occurs, an Interrupt Flag (nameIF) is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt is enabled or disabled by writing to the corresponding Interrupt Enable bit (nameIE) in the
peripheral's Interrupt Control register (peripheral.INTCTRL).
The naming of the registers may vary slightly in some peripherals.
An interrupt request is generated when the corresponding interrupt is enabled and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS
register for details on how to clear interrupt flags.
Interrupts must be enabled globally for interrupt requests to be generated.
Table 7-2. Interrupt Vector Mapping
Vector Number Base Address Peripheral Source
0 0x00 RESET
1 0x02 NMI - Non-Maskable Interrupt
from CRC
2 0x04 VLM - Voltage Level Monitor
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...........continued
Vector Number Base Address Peripheral Source
3 0x06 PORTA - Port A
4 0x08 PORTB - Port B
5 0x0A PORTC - Port C
6 0x0C RTC - Real-Time Counter
7 0x0E PIT - Periodic Interrupt Timer (in
RTC peripheral)
8 0x10 TCA0 - Timer Counter Type A
13 0x1A TCB0 - Timer Counter Type B
14 0x1C TCB1 - Timer Counter Type B
15 0x1E TCD0 - Timer Counter Type D
17 0x22 AC0 – Analog Comparator
18 0x24 AC1 – Analog Comparator
19 0x26 AC2 – Analog Comparator
20 0x28 ADC0 – Analog-to-Digital
Converter/PTC
22 0x2C ADC1 – Analog-to-Digital
Converter
24 0x30 TWI0 - Two-Wire Interface/I2C
26 0x34 SPI0 - Serial Peripheral Interface
27 0x36 USART0 - Universal
Asynchronous Receiver-
Transmitter
30 0x3C NVM - Nonvolatile Memory
Related Links
9. NVMCTRL - Nonvolatile Memory Controller
16. PORT - I/O Pin Configuration
23. RTC - Real-Time Counter
25. SPI - Serial Peripheral Interface
24. USART - Universal Synchronous and Asynchronous Receiver and Transmitter
26. TWI - Two-Wire Interface
27. CRCSCAN - Cyclic Redundancy Check Memory Scan
20. TCA - 16-bit Timer/Counter Type A
21. TCB - 16-bit Timer/Counter Type B
22. TCD - 12-Bit Timer/Counter Type D
29. AC - Analog Comparator
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30. ADC - Analog-to-Digital Converter
7.3 System Configuration (SYSCFG)
The system configuration contains the revision ID of the part. The revision ID is readable from the CPU,
making it useful for implementing application changes between part revisions.
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© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 44
7.3.1 Register Summary - SYSCFG
Offset Name Bit Pos.
0x01 REVID 7:0 REVID[7:0]
7.3.2 Register Description - SYSCFG
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7.3.2.1 Device Revision ID Register
Name:  REVID
Offset:  0x01
Reset:  [revision ID]
Property:  -
This register is read-only and displays the device revision ID.
Bit 7 6 5 4 3 2 1 0
REVID[7:0]
Access R R R R R R R R
Reset
Bits 7:0 – REVID[7:0] Revision ID
These bits contain the device revision. 0x00 = A, 0x01 = B, and so on.
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Peripherals and Architecture
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 46
8. AVR CPU
8.1 Features
8-Bit, High-Performance AVR RISC CPU:
135 instructions
Hardware multiplier
32 8-Bit Registers Directly Connected to the Arithmetic Logic Unit (ALU)
Stack in RAM
Stack Pointer Accessible in I/O Memory Space
Direct Addressing of up to 64 KB of Unified Memory:
Entire Flash accessible with all LD/ST instructions
True 16/24-Bit Access to 16/24-Bit I/O Registers
Efficient Support for 8-, 16-, and 32-Bit Arithmetic
Configuration Change Protection for System Critical Features
8.2 Overview
All AVR devices use the 8-bit AVR CPU. The CPU is able to access memories, perform calculations,
control peripherals, and execute instructions in the program memory. Interrupt handling is described in a
separate section.
Related Links
6. Memories
9. NVMCTRL - Nonvolatile Memory Controller
13. CPUINT - CPU Interrupt Controller
8.3 Architecture
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with
separate buses for program and data. Instructions in the program memory are executed with single-level
pipelining. While one instruction is being executed, the next instruction is prefetched from the program
memory. This enables instructions to be executed on every clock cycle.
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R29 (YH1 R27 (XH1 R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1 R28 (YU R26 (XL) R24 R22 R20 R18 R16 R14 R12 R10 R8 R6 R4 R2 R0
Figure 8-1. AVR CPU Architecture
Register file
Flash Program
Memory
Data Memory
ALU
R0R1
R2R3
R4R5
R6R7
R8R9
R10R11
R12R13
R14R15
R16R17
R18R19
R20R21
R22R23
R24R25
R26 (XL)R27 (XH)
R28 (YL)R29 (YH)
R30 (ZL)R31 (ZH)
Stack
Pointer
Program
Counter
Instruction
Register
Instruction
Decode
STATUS
Register
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a
constant and a register. Also, single-register operations can be executed in the ALU. After an arithmetic
operation, the STATUS register is updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 8-bit general purpose working
registers all have single clock cycle access time allowing single-cycle arithmetic logic unit operation
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AVR CPU
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between registers or between a register and an immediate. Six of the 32 registers can be used as three
16-bit Address Pointers for program and data space addressing, enabling efficient address calculations.
The program memory bus is connected to Flash, and the first program memory Flash address is 0x0000.
The data memory space is divided into I/O registers, SRAM, EEPROM, and Flash.
All I/O Status and Control registers reside in the lowest 4 KB addresses of the data memory. This is
referred to as the I/O memory space. The lowest 64 addresses are accessed directly with single-cycle
IN/OUT instructions, or as the data space locations from 0x00 to 0x3F. These addresses can be accessed
using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The lowest 32 addresses can even be
accessed with single-cycle SBI/CBI instructions and SBIS/SBIC instructions. The rest is the extended
I/O memory space, ranging from 0x0040 to 0x0FFF. The I/O registers here must be accessed as data
space locations using load and store instructions.
Data addresses 0x1000 to 0x1800 are reserved for memory mapping of fuses, the NVM controller and
EEPROM. The addresses from 0x1800 to 0x7FFF are reserved for other memories, such as SRAM.
The Flash is mapped in the data space from 0x8000 and above. The Flash can be accessed with all load
and store instructions by using addresses above 0x8000. The LPM instruction accesses the Flash similar
to the code space, where the Flash starts at address 0x0000.
For a summary of all AVR instructions, refer to the Instruction Set Summary section. For details of all AVR
instructions, refer to http://www.microchip.com/design-centers/8-bit.
Related Links
9. NVMCTRL - Nonvolatile Memory Controller
6. Memories
34. Instruction Set Summary
8.4 Arithmetic Logic Unit (ALU)
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers, or between a
constant and a register. Also, single-register operations can be executed.
The ALU operates in direct connection with all 32 general purpose registers. Arithmetic operations
between general purpose registers or between a register and an immediate are executed in a single clock
cycle, and the result is stored in the register file. After an arithmetic or logic operation, the Status register
(CPU.SREG) is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and
16-bit arithmetic are supported, and the instruction set allows for efficient implementation of 32-bit
arithmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format.
8.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier
supports different variations of signed and unsigned integer and fractional numbers:
Multiplication of signed/unsigned integers
Multiplication of signed/unsigned fractional numbers
Multiplication of a signed integer with an unsigned integer
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
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AVR CPU
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8.5 Functional Description
8.5.1 Program Flow
After Reset, the CPU will execute instructions from the lowest address in the Flash program memory,
0x0000. The Program Counter (PC) addresses the next instruction to be fetched.
Program flow is supported by conditional and unconditional JUMP and CALL instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format, and a
limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack as a word pointer.
The stack is allocated in the general data SRAM, and consequently, the stack size is only limited by the
total SRAM size and the usage of the SRAM. After Reset, the Stack Pointer (SP) points to the highest
address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy
implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the
five different addressing modes supported by the AVR CPU.
8.5.2 Instruction Execution Timing
The AVR CPU is clocked by the CPU clock: CLK_CPU. No internal clock division is applied. The figure
below shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access register file concept. This is the basic pipelining concept enabling up to 1
MIPS/MHz performance with high efficiency.
Figure 8-2. The Parallel Instruction Fetches and Instruction Executions
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU
operation using two register operands is executed and the result is stored in the destination register.
Figure 8-3. Single Cycle ALU Operation
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
8.5.3 Status Register
The Status register (CPU.SREG) contains information about the result of the most recently executed
arithmetic or logic instruction. This information can be used for altering program flow in order to perform
conditional operations.
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CPU.SREG is updated after all ALU operations, as specified in the Instruction Set Summary. This will in
many cases remove the need for using the dedicated compare instructions, resulting in faster and more
compact code. CPU.SREG is not automatically stored/restored when entering/returning from an Interrupt
Service Routine. Maintaining the Status register between context switches must, therefore, be handled by
user-defined software. CPU.SREG is accessible in the I/O memory space.
Related Links
34. Instruction Set Summary
8.5.4 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. Also, it can be used
for storing temporary data. The Stack Pointer (SP) always points to the top of the stack. The SP is
defined by the Stack Pointer bits in the Stack Pointer register (CPU.SP). The CPU.SP is implemented as
two 8-bit registers that are accessible in the I/O memory space.
Data is pushed and popped from the stack using the PUSH and POP instructions. The stack grows from
higher to lower memory locations. This implies that pushing data onto the stack decreases the SP, and
popping data off the stack increases the SP. The Stack Pointer is automatically set to the highest address
of the internal SRAM after Reset. If the stack is changed, it must be set to point above address 0x2000,
and it must be defined before any subroutine calls are executed and before interrupts are enabled.
During interrupts or subroutine calls the return address is automatically pushed on the stack as a word
pointer and the SP is decremented by '2'. The return address consists of two bytes and the Least
Significant Byte is pushed on the stack first (at the higher address). As an example, a byte pointer return
address of 0x0006 is saved on the stack as 0x0003 (shifted one bit to the right), pointing to the fourth 16-
bit instruction word in the program memory. The return address is popped off the stack with RETI (when
returning from interrupts) and RET (when returning from subroutine calls) and the SP is incremented by
two.
The SP is decremented by '1' when data is pushed on the stack with the PUSH instruction, and
incremented by '1' when data is popped off the stack using the POP instruction.
To prevent corruption when updating the Stack Pointer from software, a write to SPL will automatically
disable interrupts for up to four instructions or until the next I/O memory write.
8.5.5 Register File
The register file consists of 32 8-bit general purpose working registers with single clock cycle access time.
The register file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit Address Register Pointers for data space addressing,
enabling efficient address calculations.
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AVR CPU
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 51
0 Addr Bu undmduany) 7 R27 R26 ‘e X | B B Z | Bu (Llamas!) 15
Figure 8-4. AVR CPU General Purpose Working Registers
...
...
70
R0
R1
R2
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
Addr.
0x00
0x01
0x02
0x0D
0x0E
0x0F
0x10
0x11
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
The register file is located in a separate address space and is, therefore, not accessible through
instructions operation on data memory.
8.5.5.1 The X-, Y-, and Z-Registers
Registers R26...R31 have added functions besides their general purpose usage.
These registers can form 16-bit Address Pointers for addressing data memory. These three address
registers are called the X-register, Y-register, and Z-register. Load and store instructions can use all X-,
Y-, and Z-registers, while the LPM instructions can only use the Z-register. Indirect calls and jumps
(ICALL and IJMP ) also use the Z-register.
Refer to the instruction set or Instruction Set Summary for more information about how the X-, Y-, and Z-
registers are used.
Figure 8-5. The X-, Y-, and Z-Registers
Bit (individually)
X-register
Bit (X-register)
7070
15 870
R27 R26
XH XL
Bit (individually)
Y-register
Bit (Y-register)
7070
15 870
R29 R28
YH YL
Bit (individually)
Z-register
Bit (Z-register)
7070
15 870
R31 R30
ZH ZL
The lowest register address holds the Least Significant Byte (LSB), and the highest register address
holds the Most Significant Byte (MSB). In the different addressing modes, these address registers
function as fixed displacement, automatic increment, and automatic decrement.
Related Links
34. Instruction Set Summary
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AVR CPU
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8.5.6 Accessing 16-Bit Registers
The AVR data bus has a width of 8 bits, and so accessing 16-bit registers requires atomic operations.
These registers must be byte accessed using two read or write operations. 16-bit registers are connected
to the 8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte
is then written into the temporary register. When the high byte of the 16-bit register is written, the
temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low
byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register
in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the
temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when
reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit
register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when
writing or reading 16-bit registers.
The temporary registers can be read and written directly from user software.
8.5.6.1 Accessing 24-Bit Registers
For 24-bit registers, the read and write access is done in the same way as described for 16-bit registers,
except there are two temporary registers for 24-bit registers. The Least Significant Byte must be written
first when doing a write, and read first when doing a read.
8.5.7 Configuration Change Protection (CCP)
System critical I/O register settings are protected from accidental modification. Flash self-programming
(via store to NVM controller) is protected from accidental execution. This is handled globally by the
Configuration Change Protection (CCP) register.
Changes to the protected I/O registers or bits, or execution of protected instructions, are only possible
after the CPU writes a signature to the CCP register. The different signatures are listed in the description
of the CCP register (CPU.CCP).
There are two modes of operation: one for protected I/O registers, and one for the protected self-
programming.
Related Links
8.7.1 CCP
8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
In order to write to registers protected by CCP, these steps are required:
1. The software writes the signature that enables change of protected I/O registers to the CCP bit field
in the CPU.CCP register.
2. Within four instructions, the software must write the appropriate data to the protected register.
Most protected registers also contain a write enable/change enable/lock bit. This bit must be written
to '1' in the same operation as the data are written.
The protected change is immediately disabled if the CPU performs write operations to the I/O
register or data memory, if load or store accesses to Flash, NVMCTRL, EEPROM are conducted,
or if the SLEEP instruction is executed.
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AVR CPU
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 53
8.5.7.2 Sequence for Execution of Self-Programming
In order to execute self-programming (the execution of writes to the NVM controller's command register),
the following steps are required:
1. The software temporarily enables self-programming by writing the SPM signature to the CCP
register (CPU.CCP).
2. Within four instructions, the software must execute the appropriate instruction. The protected
change is immediately disabled if the CPU performs accesses to the Flash, NVMCTRL, or
EEPROM, or if the SLEEP instruction is executed.
Once the correct signature is written by the CPU, interrupts will be ignored for the duration of the
configuration change enable period. Any interrupt request (including non-maskable interrupts) during the
CCP period will set the corresponding interrupt flag as normal, and the request is kept pending. After the
CCP period is completed, any pending interrupts are executed according to their level and priority.
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8.6 Register Summary - CPU
Offset Name Bit Pos.
0x04 CCP 7:0 CCP[7:0]
0x05
...
0x0C
Reserved
0x0D SP 7:0 SP[7:0]
15:8 SP[15:8]
0x0F SREG 7:0 I T H S V N Z C
8.7 Register Description
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AVR CPU
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8.7.1 Configuration Change Protection
Name:  CCP
Offset:  0x04
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
CCP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – CCP[7:0] Configuration Change Protection
Writing the correct signature to this bit field allows changing protected I/O registers or executing protected
instructions within the next four CPU instructions executed.
All interrupts are ignored during these cycles. After these cycles, interrupts will automatically be handled
again by the CPU, and any pending interrupts will be executed according to their level and priority.
When the protected I/O register signature is written, CCP[0] will read as '1' as long as the CCP feature is
enabled.
When the protected self-programming signature is written, CCP[1] will read as '1' as long as the CCP
feature is enabled.
CCP[7:2] will always read as zero.
Value Name Description
0x9D SPM Allow Self-Programming
0xD8 IOREG Un-protect protected I/O registers
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8.7.2 Stack Pointer
Name:  SP
Offset:  0x0D
Reset:  Top of stack
Property:  -
The CPU.SP holds the Stack Pointer (SP) that points to the top of the stack. After Reset, the Stack
Pointer points to the highest internal SRAM address.
Only the number of bits required to address the available data memory including external memory (up to
64 KB) is implemented for each device. Unused bits will always read as zero.
The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix
L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
To prevent corruption when updating the SP from software, a write to CPU.SPL will automatically disable
interrupts for the next four instructions or until the next I/O memory write.
Bit 15 14 13 12 11 10 9 8
SP[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset
Bit 7 6 5 4 3 2 1 0
SP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset
Bits 15:8 – SP[15:8] Stack Pointer High Byte
These bits hold the MSB of the 16-bit register.
Bits 7:0 – SP[7:0] Stack Pointer Low Byte
These bits hold the LSB of the 16-bit register.
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8.7.3 Status Register
Name:  SREG
Offset:  0x0F
Reset:  0x00
Property:  -
The Status register contains information about the result of the most recently executed arithmetic or logic
instruction. For details about the bits in this register and how they are affected by the different
instructions, see the Instruction Set Summary.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 – I Global Interrupt Enable
Writing a '1' to this bit enables interrupts on the device.
Writing a '0' to this bit disables interrupts on the device, independent of the individual interrupt enable
settings of the peripherals.
This bit is not cleared by hardware after an interrupt has occurred.
This bit can be set and cleared by software with the SEI and CLI instructions.
Changing the I flag through the I/O register results in a one-cycle Wait state on the access.
Bit 6 – T Bit Copy Storage
The bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination for the
operated bit.
A bit from a register in the register file can be copied into this bit by the BST instruction, and this bit can
be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
This bit indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic.
Bit 4 – S Sign Bit, S = N V
The sign bit (S) is always an exclusive or (xor) between the negative flag (N) and the two’s complement
overflow flag (V).
Bit 3 – V Two’s Complement Overflow Flag
The two’s complement overflow flag (V) supports two’s complement arithmetic.
Bit 2 – N Negative Flag
The negative flag (N) indicates a negative result in an arithmetic or logic operation.
Bit 1 – Z Zero Flag
The zero flag (Z) indicates a zero result in an arithmetic or logic operation.
Bit 0 – C Carry Flag
The carry flag (C) indicates a carry in an arithmetic or logic operation.
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AVR CPU
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9. NVMCTRL - Nonvolatile Memory Controller
9.1 Features
Unified Memory
In-System Programmable
Self-Programming and Boot Loader Support
Configurable Sections for Write Protection:
Boot section for boot loader code or application code
Application code section for application code
Application data section for application code or data storage
Signature Row for Factory-Programmed Data:
ID for each device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User Row for Application Data:
32 bytes in size
Can be read and written from software
Can be written from UPDI on locked device
Content is kept after chip erase
9.2 Overview
The NVM Controller (NVMCTRL) is the interface between the device, the Flash, and the EEPROM. The
Flash and EEPROM are reprogrammable memory blocks that retain their values even when not powered.
The Flash is mainly used for program storage and can be used for data storage. The EEPROM is used
for data storage and can be programmed while the CPU is running the program from the Flash.
9.2.1 Block Diagram
Figure 9-1. NVMCTRL Block Diagram
Flash
EEPROM
NVM Block
Signature Row
User Row
NVMCTRL
Program Memory Bus
Data Memory Bus
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NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 59
9.2.2 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 9-1. NVMCTRL System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections No -
Interrupts Yes CPUINT
Events No -
Debug Yes UPDI
Related Links
9.2.2.1 Clocks
9.2.2.5 Debug Operation
9.2.2.3 Interrupts
9.2.2.1 Clocks
This peripheral always runs on the CPU clock (CLK_CPU). It will request this clock also in sleep modes if
a write/erase is ongoing.
Related Links
10. CLKCTRL - Clock Controller
9.2.2.2 I/O Lines and Connections
Not applicable.
9.2.2.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
9.2.2.4 Events
Not applicable.
9.2.2.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging
mode will halt normal operation of the peripheral.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar,
improper operation or data loss may result during halted debugging.
Related Links
33. UPDI - Unified Program and Debug Interface
9.3 Functional Description
9.3.1 Memory Organization
9.3.1.1 Flash
The Flash is divided into a set of pages. A page is the basic unit addressed when programming the Flash.
It is only possible to write or erase a whole page at a time. One page consists of several words.
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NVMCTRL - Nonvolatile Memory Controller
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The Flash can be divided into three sections in blocks of 256 bytes for different security. The three
different sections are BOOT, Application Code (APPCODE), and Application Data (APPDATA).
Figure 9-2. Flash Sections
FLASHSTART: 0x8000
BOOTEND>0: 0x8000+BOOTEND*256
BOOT
APPEND>0: 0x8000+APPEND*256
APPLICATION
CODE
APPLICATION
DATA
Section Sizes
The sizes of these sections are set by the Boot Section End fuse (FUSE.BOOTEND) and Application
Code Section End fuse (FUSE.APPEND).
The fuses select the section sizes in blocks of 256 bytes. The BOOT section stretches from the start of
the Flash until BOOTEND. The APPCODE section runs from BOOTEND until APPEND. The remaining
area is the APPDATA section. If APPEND is written to 0, the APPCODE section runs from BOOTEND to
the end of Flash (removing the APPDATA section). If BOOTEND and APPEND are written to 0, the entire
Flash is regarded as BOOT section. APPEND should either be set to 0 or a value greater or equal than
BOOTEND.
Table 9-2. Setting Up Flash Sections
BOOTEND APPEND BOOT Section APPCODE Section APPDATA Section
0 0 0 to FLASHEND - -
> 0 0 0 to 256*BOOTEND 256*BOOTEND to
FLASHEND
-
> 0 ==
BOOTEND
0 to 256*BOOTEND - 256*BOOTEND to
FLASHEND
> 0 >
BOOTEND
0 to 256*BOOTEND 256*BOOTEND to
256*APPEND
256*APPEND to
FLASHEND
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Note: 
See also the BOOTEND and APPEND descriptions.
Interrupt vectors are by default located after the BOOT section. This can be changed in the interrupt
controller.
If FUSE.BOOTEND is written to 0x04 and FUSE.APPEND is written to 0x08, the first
4*256 bytes will be BOOT, the next 4*256 bytes will be APPCODE, and the remaining
Flash will be APPDATA.
Inter-Section Write Protection
Between the three Flash sections, a directional write protection is implemented:
The code in the BOOT section can write to APPCODE and APPDATA
The code in APPCODE can write to APPDATA
The code in APPDATA cannot write to Flash or EEPROM
Boot Section Lock and Application Code Section Write Protection
The two lockbits (APCWP and BOOTLOCK in NVMCTRL.CTRLB) can be set to lock further updates of
the respective APPCODE or BOOT section until the next Reset.
The CPU can never write to the BOOT section. NVMCTRL_CTRLB.BOOTLOCK prevents reads and
execution of code from the BOOT section.
9.3.1.2 EEPROM
The EEPROM is divided into a set of pages where one page consists of multiple bytes. The EEPROM
has byte granularity on erase/write. Within one page only the bytes marked to be updated will be erased/
written. The byte is marked by writing a new value to the page buffer for that address location.
9.3.1.3 User Row
The User Row is one extra page of EEPROM. This page can be used to store various data, such as
calibration/configuration data and serial numbers. This page is not erased by a chip erase. The User Row
is written as normal EEPROM, but in addition, it can be written through UPDI on a locked device.
9.3.2 Memory Access
9.3.2.1 Read
Reading of the Flash and EEPROM is done by using load instructions with an address according to the
memory map. Reading any of the arrays while a write or erase is in progress will result in a bus wait, and
the instruction will be suspended until the ongoing operation is complete.
9.3.2.2 Page Buffer Load
The page buffer is loaded by writing directly to the memories as defined in the memory map. Flash,
EEPROM, and User Row share the same page buffer so only one section can be programmed at a time.
The Least Significant bits (LSb) of the address are used to select where in the page buffer the data is
written. The resulting data will be a binary and operation between the new and the previous content of the
page buffer. The page buffer will automatically be erased (all bits set) after:
A device Reset
Any page write or erase operation
A Clear Page Buffer command
The device wakes up from any sleep mode
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 62
9.3.2.3 Programming
For page programming, filling the page buffer and writing the page buffer into Flash, User Row, and
EEPROM are two separate operations.
Before programming a Flash page with the data in the page buffer, the Flash page must be erased. The
page buffer is also erased when the device enters a sleep mode. Programming an unerased Flash page
will corrupt its content.
The Flash can either be written with the erase and write separately, or one command handling both:
Alternative 1:
Fill the page buffer
Write the page buffer to Flash with the Erase/Write Page command
Alternative 2:
Write to a location on the page to set up the address
Perform an Erase Page command
Fill the page buffer
Perform a Write Page command
The NVM command set supports both a single erase and write operation, and split Page Erase and Page
Write commands. This split commands enable shorter programming time for each command, and the
erase operations can be done during non-time-critical programming execution.
The EEPROM programming is similar, but only the bytes updated in the page buffer will be written or
erased in the EEPROM.
9.3.2.4 Commands
Reading of the Flash/EEPROM and writing of the page buffer is handled with normal load/store
instructions. Other operations, such as writing and erasing the memory arrays, are handled by commands
in the NVM.
To execute a command in the NVM:
1. Confirm that any previous operation is completed by reading the Busy Flags (EEBUSY and
FBUSY) in the NVMCTRL.STATUS register.
2. Write the NVM command unlock to the Configuration Change Protection register in the CPU
(CPU.CCP).
3. Write the desired command value to the CMD bits in the Control A register (NVMCTRL.CTRLA)
within the next four instructions.
9.3.2.4.1 Write Command
The Write command of the Flash controller writes the content of the page buffer to the Flash or EEPROM.
If the write is to the Flash, the CPU will stop executing code as long as the Flash is busy with the write
operation. If the write is to the EEPROM, the CPU can continue executing code while the operation is
ongoing.
The page buffer will be automatically cleared after the operation is finished.
9.3.2.4.2 Erase Command
The Erase command erases the current page. There must be one byte written in the page buffer for the
Erase command to take effect.
For erasing the Flash, first, write to one address in the desired page, then execute the command. The
whole page in the Flash will then be erased. The CPU will be halted while the erase is ongoing.
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 63
For the EEPROM, only the bytes written in the page buffer will be erased when the command is
executed. To erase a specific byte, write to its corresponding address before executing the command. To
erase a whole page all the bytes in the page buffer have to be updated before executing the command.
The CPU can continue running code while the operation is ongoing.
The page buffer will automatically be cleared after the operation is finished.
9.3.2.4.3 Erase-Write Operation
The Erase/Write command is a combination of the Erase and Write command, but without clearing the
page buffer after the Erase command: The erase/write operation first erases the selected page, then it
writes the content of the page buffer to the same page.
When executed on the Flash, the CPU will be halted when the operations are ongoing. When executed
on EEPROM, the CPU can continue executing code.
The page buffer will automatically be cleared after the operation is finished.
9.3.2.4.4 Page Buffer Clear Command
The Page Buffer Clear command clears the page buffer. The contents of the page buffer will be all 1’s
after the operation. The CPU will be halted when the operation executes (seven CPU cycles).
9.3.2.4.5 Chip Erase Command
The Chip Erase command erases the Flash and the EEPROM. The EEPROM is unaltered if the
EEPROM Save During Chip Erase (EESAVE) fuse in FUSE.SYSCFG0 is set. The Flash will not be
protected by Boot Section Lock (BOOTLOCK) or Application Code Section Write Protection (APCWP) in
NVMCTRL.CTRLB. The memory will be all 1’s after the operation.
9.3.2.4.6 EEPROM Erase Command
The EEPROM Erase command erases the EEPROM. The EEPROM will be all 1’s after the operation.
The CPU will be halted while the EEPROM is being erased.
9.3.2.4.7 Fuse Write Command
The Fuse Write command writes the fuses. It can only be used by the UPDI, the CPU cannot start this
command.
Follow this procedure to use this command:
Write the address of the fuse to the Address register (NVMCTRL.ADDR)
Write the data to be written to the fuse to the Data register (NVMCTRL.DATA)
Execute the Fuse Write command.
After the fuse is written, a Reset is required for the updated value to take effect.
For reading fuses, use a regular read on the memory location.
9.3.3 Preventing Flash/EEPROM Corruption
During periods of low VDD, the Flash program or EEPROM data can be corrupted if the supply voltage is
too low for the CPU and the Flash/EEPROM to operate properly. These issues are the same as for board
level systems using Flash/EEPROM, and the same design solutions should be applied.
A Flash/EEPROM corruption can be caused by two situations when the voltage is too low:
1. A regular write sequence to the Flash, which requires a minimum voltage to operate correctly.
2. The CPU itself can execute instructions incorrectly when the supply voltage is too low.
See the Electrical Characteristics chapter for Maximum Frequency vs. VDD.
Flash/EEPROM corruption can be avoided by these measures:
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 64
Keep the device in Reset during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-Out Detector (BOD).
The voltage level monitor in the BOD can be used to prevent starting a write to the EEPROM close to
the BOD level.
If the detection levels of the internal BOD don’t match the required detection level, an external low
VDD Reset protection circuit can be used. If a Reset occurs while a write operation is ongoing, the
write operation will be aborted.
Related Links
37.3 General Operating Ratings
17. BOD - Brown-out Detector
9.3.4 Interrupts
Table 9-3. Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 EEREADY NVM The EEPROM is ready for new write/erase operations.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of
the peripheral (NVMCTRL.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt
Enable register (NVMCTRL.INTEN).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt
flag is set. The interrupt request remains active until the interrupt flag is cleared. See the peripheral's
INTFLAGS register for details on how to clear interrupt flags.
9.3.5 Sleep Mode Operation
If there is no ongoing write operation, the NVMCTRL will enter sleep mode when the system enters sleep
mode.
If a write operation is ongoing when the system enters a sleep mode, the NVM block, the NVM Controller,
and the system clock will remain ON until the write is finished. This is valid for all sleep modes, including
Power-Down Sleep mode.
The EEPROM Ready interrupt will wake up the device only from Idle Sleep mode.
The page buffer is cleared when waking up from Sleep.
9.3.6 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves
the protected register unchanged.
The following registers are under CCP:
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 65
Table 9-4. NVMCTRL - Registers under Configuration Change Protection
Register Key
NVMCTRL.CTRLA SPM
Related Links
8.5.7.2 Sequence for Execution of Self-Programming
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 66
9.4 Register Summary - NVMCTRL
Offset Name Bit Pos.
0x00 CTRLA 7:0 CMD[2:0]
0x01 CTRLB 7:0 BOOTLOCK APCWP
0x02 STATUS 7:0 WRERROR EEBUSY FBUSY
0x03 INTCTRL 7:0 EEREADY
0x04 INTFLAGS 7:0 EEREADY
0x05 Reserved
0x06 DATA 7:0 DATA[7:0]
15:8 DATA[15:8]
0x08 ADDR 7:0 ADDR[7:0]
15:8 ADDR[15:8]
9.5 Register Description
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 67
9.5.1 Control A
Name:  CTRLA
Offset:  0x00
Reset:  0x00
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CMD[2:0]
Access R/W R/W R/W
Reset 0 0 0
Bits 2:0 – CMD[2:0] Command
Write this bit field to issue a command. The Configuration Change Protection key for self-programming
(SPM) has to be written within four instructions before this write.
Value Name Description
0x0 - No command
0x1 WP Write page buffer to memory (NVMCTRL.ADDR selects which memory)
0x2 ER Erase page (NVMCTRL.ADDR selects which memory)
0x3 ERWP Erase and write page (NVMCTRL.ADDR selects which memory)
0x4 PBC Page buffer clear
0x5 CHER Chip erase: erase Flash and EEPROM (unless EESAVE in FUSE.SYSCFG is '1')
0x6 EEER EEPROM Erase
0x7 WFU Write fuse (only accessible through UPDI)
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 68
9.5.2 Control B
Name:  CTRLB
Offset:  0x01
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
BOOTLOCK APCWP
Access R/W R/W
Reset 0 0
Bit 1 – BOOTLOCK Boot Section Lock
Writing a ’1’ to this bit locks the boot section from read and instruction fetch.
If this bit is ’1’, a read from the boot section will return ’0’. A fetch from the boot section will also return ‘0’
as instruction.
This bit can be written from the boot section only. It can only be cleared to ’0’ by a Reset.
This bit will take effect only when the boot section is left the first time after the bit is written.
Bit 0 – APCWP Application Code Section Write Protection
Writing a ’1’ to this bit protects the application code section from further writes.
This bit can only be written to ’1’. It is cleared to ’0’ only by Reset.
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 69
9.5.3 Status
Name:  STATUS
Offset:  0x02
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
WRERROR EEBUSY FBUSY
Access R R R
Reset 0 0 0
Bit 2 – WRERROR Write Error
This bit will read '1' when a write error has happened. A write error could be writing to different sections
before doing a page write or writing to a protected area. This bit is valid for the last operation.
Bit 1 – EEBUSY EEPROM Busy
This bit will read '1' when the EEPROM is busy with a command.
Bit 0 – FBUSY Flash Busy
This bit will read '1' when the Flash is busy with a command.
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 70
9.5.4 Interrupt Control
Name:  INTCTRL
Offset:  0x03
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
EEREADY
Access R/W
Reset 0
Bit 0 – EEREADY EEPROM Ready Interrupt
Writing a '1' to this bit enables the interrupt, which indicates that the EEPROM is ready for new write/
erase operations.
This is a level interrupt that will be triggered only when the EEREADY flag in the INTFLAGS register is set
to zero. Thus, the interrupt should not be enabled before triggering an NVM command, as the EEREADY
flag will not be set before the NVM command issued. The interrupt should be disabled in the interrupt
handler.
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 71
9.5.5 Interrupt Flags
Name:  INTFLAGS
Offset:  0x04
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
EEREADY
Access R/W
Reset 0
Bit 0 – EEREADY EEREADY Interrupt Flag
This flag is set continuously as long as the EEPROM is not busy. This flag is cleared by writing a '1' to it.
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 72
9.5.6 Data
Name:  DATA
Offset:  0x06
Reset:  0x00
Property:  -
The NVMCTRL.DATAL and NVMCTRL.DATAH register pair represents the 16-bit value,
NVMCTRL.DATA. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8]
(suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
DATA[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DATA[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:0 – DATA[15:0] Data Register
This register is used by the UPDI for fuse write operations.
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 73
9.5.7 Address
Name:  ADDR
Offset:  0x08
Reset:  0x00
Property:  -
The NVMCTRL.ADDRL and NVMCTRL.ADDRH register pair represents the 16-bit value,
NVMCTRL.ADDR. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8]
(suffix H) can be accessed at offset + 0x01.
Bit 15 14 13 12 11 10 9 8
ADDR[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ADDR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 15:0 – ADDR[15:0] Address
The Address register contains the address to the last memory location that has been updated.
ATtiny1614
NVMCTRL - Nonvolatile Memory Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 74
10. CLKCTRL - Clock Controller
10.1 Features
All clocks and clock sources are automatically enabled when requested by peripherals
Internal Oscillators:
16/20 MHz Oscillator (OSC20M)
32 KHz Ultra Low-Power Oscillator (OSCULP32K)
External Clock Options:
32.768 kHz Crystal Oscillator (XOSC32K)
External clock
Main Clock Features:
Safe run-time switching
Prescaler with 1x to 64x division in 12 different settings
10.2 Overview
The Clock Controller peripheral (CLKCTRL) controls, distributes, and prescales the clock signals from the
available oscillators. The CLKCTRL supports internal and external clock sources.
The CLKCTRL is based on an automatic clock request system, implemented in all peripherals on the
device. The peripherals will automatically request the clocks needed. If multiple clock sources are
available, the request is routed to the correct clock source.
The Main Clock (CLK_MAIN) is used by the CPU, RAM, and the I/O bus. The main clock source can be
selected and prescaled. Some peripherals can share the same clock source as the main clock, or run
asynchronously to the main clock domain.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 75
CPU CLKCPU CLK PER Main Clock Presca‘er CLKiMAIN xoscszx mom RTC ("her W WDT BOD TCD Peripherals mam A CLKiRTC CLKiwDT CLKiBOD CLKJCD g < u="" n="" 050mm="" ymcz="" _fl="" g?="" msm="" e="" x="" tclk="">
10.2.1 Block Diagram - CLKCTRL
Figure 10-1. CLKCTRL Block Diagram
CPURAMNVM TCDBOD
RTC
OSC20M
int. Oscillator
WDT
32.768 kHz
ext. Crystal Osc.
DIV32
TOSC2 TOSC1
RTC
CLKSEL
CLK_RTC
CLK_PER
CLK_MAIN
CLK_WDT CLK_BOD CLK_TCD
TCD
CLKCSEL
Main Clock Prescaler
Main Clock Switch
INT
PRESCALER
XOSC32K
SEL
CLK_CPU
Other
Peripherals
CLKOUT
OSC20M
XOSC32K
OSCULP32K
32 KHz ULP
Int. Oscillator
EXTCLK
The clock system consists of the main clock and other asynchronous clocks:
Main Clock
This clock is used by the CPU, RAM, Flash, the I/O bus, and all peripherals connected to the I/O bus.
It is always running in Active and Idle Sleep mode and can be running in Standby Sleep mode if
requested.
The main clock CLK_MAIN is prescaled and distributed by the clock controller:
CLK_CPU is used by the CPU, SRAM, and the NVMCTRL peripheral to access the nonvolatile
memory
CLK_PER is used by all peripherals that are not listed under asynchronous clocks.
Clocks running asynchronously to the main clock domain:
CLK_RTC is used by the RTC/PIT. It will be requested when the RTC/PIT is enabled. The clock
source for CLK_RTC should only be changed if the peripheral is disabled.
CLK_WDT is used by the WDT. It will be requested when the WDT is enabled.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 76
CLK_BOD is used by the BOD. It will be requested when the BOD is enabled in Sampled mode.
The clock source for the for the main clock domain is configured by writing to the Clock Select bits
(CLKSEL) in the Main Clock Control A register (CLKCTRL.MCLKCTRLA). The asynchronous clock
sources are configured by registers in the respective peripheral.
10.2.2 Signal Description
Signal Type Description
CLKOUT Digital output CLK_PER output
Related Links
5. I/O Multiplexing and Considerations
10.3 Functional Description
10.3.1 Sleep Mode Operation
When a clock source is not used/requested it will turn OFF. It is possible to request a clock source directly
by writing a '1' to the Run Standby bit (RUNSTDBY) in the respective oscillator's Control A register
(CLKCTRL.[osc]CTRLA). This will cause the oscillator to run constantly, except for Power-Down Sleep
mode. Additionally, when this bit is written to '1' the oscillator start-up time is eliminated when the clock
source is requested by a peripheral.
The main clock will always run in Active and Idle Sleep mode. In Standby Sleep mode, the main clock will
only run if any peripheral is requesting it, or the Run in Standby bit (RUNSTDBY) in the respective
oscillator's Control A register (CLKCTRL.[osc]CTRLA) is written to '1'.
In Power-Down Sleep mode, the main clock will stop after all NVM operations are completed.
10.3.2 Main Clock Selection and Prescaler
All internal oscillators can be used as the main clock source for CLK_MAIN. The main clock source is
selectable from software and can be safely changed during normal operation.
Built-in hardware protection prevents unsafe clock switching:
Upon selection of an external clock source, a switch to the chosen clock source will only occur if edges
are detected, indicating it is stable. Until a sufficient number of clock edges are detected, the switch will
not occur and it will not be possible to change to another clock source again without executing a Reset.
An ongoing clock source switch is indicated by the System Oscillator Changing flag (SOSC) in the Main
Clock Status register (CLKCTRL.MCLKSTATUS). The stability of the external clock sources is indicated
by the respective status flags (EXTS and XOSC32KS in CLKCTRL.MCLKSTATUS).
CAUTION
If an external clock source fails while used as CLK_MAIN source, only the WDT can provide a
mechanism to switch back via System Reset.
CLK_MAIN is fed into a prescaler before it is used by the peripherals (CLK_PER) in the device. The
prescaler divide CLK_MAIN by a factor from 1 to 64.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 77
osczoM ——> 32 kHz 05:: ——> 32 768 kHz crysta‘ esc.——> Exlemal clock ——> CLKiMAIN Main Clock Prescaler (Div 1, 2, 4, 8, 16, 32, 64, 6, 10, 24, 48) CLKiPER 4»
Figure 10-2. Main Clock and Prescaler
(Div 1, 2, 4, 8, 16, 32,
64, 6, 10, 24, 48)
OSC20M
32 kHz Osc.
32.768 kHz crystal Osc.
External clock
CLK_MAIN CLK_PER
Main Clock Prescaler
The Main Clock and Prescaler configuration registers (CLKCTRL.MCLKCTRLA,
CLKCTRL.MCLKCTRLB) are protected by the Configuration Change Protection Mechanism, employing a
timed write procedure for changing these registers.
Related Links
8.5.7 Configuration Change Protection (CCP)
10.3.3 Main Clock After Reset
After any Reset, CLK_MAIN is provided by the 16/20 MHz Oscillator (OSC20M) and with a prescaler
division factor of 6. Since the actual frequency of the OSC20M is determined by the Frequency Select
bits (FREQSEL) of the Oscillator Configuration fuse (FUSE.OSCCFG), these frequencies are possible
after Reset:
Table 10-1. Peripheral Clock Frequencies After Reset
CLK_MAIN
as Per FREQSEL in FUSE.OSCCFG
Resulting CLK_PER
16 MHz 2.66 MHz
20 MHz 3.3 MHz
See the OSC20M description for further details.
Related Links
10.3.4.1.1 16/20 MHz Oscillator (OSC20M)
10.3.4 Clock Sources
All internal clock sources are enabled automatically when they are requested by a peripheral. The crystal
oscillator, based on an external crystal, must be enabled by writing a '1' to the ENABLE bit in the 32 KHz
Crystal Oscillator Control A register (CLKCTRL.XOSC32KCTRLA) before it can serve as a clock source.
The respective Oscillator Status bits in the Main Clock Status register (CLKCTRL.MCLKSTATUS) indicate
whether the clock source is running and stable.
Related Links
6.10 Configuration and User Fuses (FUSE)
8.5.7 Configuration Change Protection (CCP)
10.3.4.1 Internal Oscillators
The internal oscillators do not require any external components to run. See the related links for accuracy
and electrical characteristics.
Related Links
37. Electrical Characteristics
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 78
10.3.4.1.1 16/20 MHz Oscillator (OSC20M)
This oscillator can operate at multiple frequencies, selected by the value of the Frequency Select bits
(FREQSEL) in the Oscillator Configuration Fuse (FUSE.OSCCFG). The center frequencies are:
16 MHz
20 MHz
After a system Reset, FUSE.OSCCFG determines the initial frequency of CLK_MAIN.
During Reset, the calibration values for the OSC20M are loaded from fuses. There are two different
calibration bit fields:
The Calibration bit field (CAL20M) in the Calibration A register (CLKCTRL.OSC20MCALIBA) enables
calibration around the current center frequency.
The Oscillator Temperature Coefficient Calibration bit field (TEMPCAL20M) in the Calibration B
register (CLKCTRL.OSC20MCALIBB) enables adjustment of the slope of the temperature drift
compensation.
For applications requiring more fine-tuned frequency setting than the oscillator calibration provides,
factory stored frequency error after calibrations are available.
The oscillator calibration can be locked by the Oscillator Lock (OSCLOCK) Fuse (FUSE.OSCCFG). When
this fuse is ‘1’, it is not possible to change the calibration. The calibration is locked if this oscillator is used
as the main clock source and the Lock Enable bit (LOCKEN) in the Control B register
(CLKCTRL.OSC20MCALIBB) is ‘1’.
The calibration bits are protected by the Configuration Change Protection Mechanism, requiring a timed
write procedure for changing the main clock and prescaler settings.
The start-up time of this oscillator is the analog start-up time plus four oscillator cycles. Refer to the
Electrical Characteristics section for the start-up time.
When changing the oscillator calibration value, the frequency may overshoot. If the oscillator is used as
the main clock (CLK_MAIN) it is recommended to change the main clock prescaler so that the main clock
frequency does not exceed ¼ of the maximum operation main clock frequency as described in the
General Operating Ratings section. The system clock prescaler can be changed back after the oscillator
calibration value has been updated.
Related Links
6.10 Configuration and User Fuses (FUSE)
10.3.5 Configuration Change Protection
37.3 General Operating Ratings
10.3.3 Main Clock After Reset
37.9 Oscillators and Clocks
OSC20M Stored Frequency Error Compensation
This oscillator can operate at multiple frequencies, selected by the value of the Frequency Select bits
(FREQSEL) in the Oscillator Configuration fuse (FUSE.OSCCFG) at Reset. As previously mentioned
appropriate calibration values are loaded to adjust to center frequency (OSC20M), and temperature drift
compensation (TEMPCAL20M), meeting the specifications defined in the internal oscillator
characteristics. For applications requiring wider operating range, the relative factory stored frequency
error after calibrations can be used. The four errors are measured at different settings and are available in
the signature row as signed byte values.
SIGROW.OSC16ERR3V is the frequency error from 16 MHz measured at 3V
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 79
SIGROW.OSC16ERR5V is the frequency error from 16 MHz measured at 5V
SIGROW.OSC20ERR3V is the frequency error from 20 MHz measured at 3V
SIGROW.OSC20ERR5V is the frequency error from 20 MHz measured at 5V
The error is stored as a compressed Q1.10 fixed point 8-bit value, in order not to lose resolution, where
the MSB is the sign bit and the seven LSBs the lower bits of the Q1.10.
BAUDact = BAUD +BAUD *
1024
The minimum legal BAUD register value is 0x40, the target BAUD register value should therefore not be
lower than 0x4A to ensure that the compensated BAUD value stays within the legal range, even for parts
with negative compensation values. The example code below demonstrates how to apply this value for
more accurate USART baud rate:
#include <assert.h>
/* Baud rate compensated with factory stored frequency error */
/* Asynchronous communication without Auto-baud (Sync Field) */
/* 16MHz Clock, 3V and 600 BAUD */
int8_t sigrow_val = SIGROW.OSC16ERR3V; // read signed error
int32_t baud_reg_val = 600; // ideal BAUD register value
assert (baud_reg_val >= 0x4A); // Verify legal min BAUD register
value with max neg comp
baud_reg_val *= (1024 + sigrow_val); // sum resolution + error
baud_reg_val /= 1024; // divide by resolution
USART0.BAUD = (int16_t) baud_reg_val; // set adjusted baud rate
Related Links
37.9 Oscillators and Clocks
10.3.4.1.2 32 KHz Oscillator (OSCULP32K)
The 32 KHz oscillator is optimized for Ultra Low-Power (ULP) operation. Power consumption is
decreased at the cost of decreased accuracy compared to an external crystal oscillator.
This oscillator provides the 1 KHz signal for the Real-Time Counter (RTC), the Watchdog Timer (WDT),
and the Brown-out Detector (BOD).
The start-up time of this oscillator is the oscillator start-up time plus four oscillator cycles. Refer to the
Electrical Characteristics chapter for the start-up time.
Related Links
17. BOD - Brown-out Detector
19. WDT - Watchdog Timer
23. RTC - Real-Time Counter
10.3.4.2 External Clock Sources
These external clock sources are available:
External Clock from pin EXTCLK
The TOSC1 and TOSC2 pins are dedicated to driving a 32.768 kHz Crystal Oscillator (XOSC32K).
Instead of a crystal oscillator, TOSC1 can be configured to accept an external clock source.
10.3.4.2.1 32.768 kHz Crystal Oscillator (XOSC32K)
This oscillator supports two input options: Either a crystal is connected to the pins TOSC1 and TOSC2, or
an external clock running at 32 KHz is connected to TOSC1. The input option must be configured by
writing the Source Select bit (SEL) in the XOSC32K Control A register (CLKCTRL.XOSC32KCTRLA).
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 80
The XOSC32K is enabled by writing a '1' to its ENABLE bit in CLKCTRL.XOSC32KCTRLA. When
enabled, the configuration of the GPIO pins used by the XOSC32K is overridden as TOSC1, TOSC2 pins.
The Enable bit needs to be set for the oscillator to start running when requested.
The start-up time of a given crystal oscillator can be accommodated by writing to the Crystal Start-up
Time bits (CSUT) in CLKCTRL.XOSC32KCTRLA.
When XOSC32K is configured to use an external clock on TOSC1, the start-up time is fixed to two cycles.
10.3.4.2.2 External Clock (EXTCLK)
The EXTCLK is taken directly from the pin. This GPIO pin is automatically configured for EXTCLK if any
peripheral is requesting this clock.
This clock source has a start-up time of two cycles when first requested.
10.3.5 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves
the protected register unchanged.
The following registers are under CCP:
Table 10-2. CLKCTRL - Registers Under Configuration Change Protection
Register Key
CLKCTRL.MCLKCTRLB IOREG
CLKCTRL.MCLKLOCK IOREG
CLKCTRL.XOSC32KCTRLA IOREG
CLKCTRL.MCLKCTRLA IOREG
CLKCTRL.OSC20MCTRLA IOREG
CLKCTRL.OSC20MCALIBA IOREG
CLKCTRL.OSC20MCALIBB IOREG
CLKCTRL.OSC32KCTRLA IOREG
Related Links
8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 81
10.4 Register Summary - CLKCTRL
Offset Name Bit Pos.
0x00 MCLKCTRLA 7:0 CLKOUT CLKSEL[1:0]
0x01 MCLKCTRLB 7:0 PDIV[3:0] PEN
0x02 MCLKLOCK 7:0 LOCKEN
0x03 MCLKSTATUS 7:0 EXTS XOSC32KS OSC32KS OSC20MS SOSC
0x04
...
0x0F
Reserved
0x10 OSC20MCTRLA 7:0 RUNSTDBY
0x11 OSC20MCALIBA 7:0 CAL20M[5:0]
0x12 OSC20MCALIBB 7:0 LOCK TEMPCAL20M[3:0]
0x13
...
0x17
Reserved
0x18 OSC32KCTRLA 7:0 RUNSTDBY
0x19
...
0x1B
Reserved
0x1C XOSC32KCTRLA 7:0 CSUT[1:0] SEL RUNSTDBY ENABLE
10.5 Register Description
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 82
10.5.1 Main Clock Control A
Name:  MCLKCTRLA
Offset:  0x00
Reset:  0x00
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CLKOUT CLKSEL[1:0]
Access R/W R/W R/W
Reset 0 0 0
Bit 7 – CLKOUT System Clock Out
When this bit is written to '1', the system clock is output to CLKOUT pin.
When the device is in a Sleep mode, there is no clock output unless a peripheral is using the system
clock.
Bits 1:0 – CLKSEL[1:0] Clock Select
This bit field selects the source for the Main Clock (CLK_MAIN).
Value Name Description
0x0 OSC20M 16/20 MHz internal oscillator
0x1 OSCULP32K 32 KHz internal ultra low-power oscillator
0x2 XOSC32K 32.768 kHz external crystal oscillator
0x3 EXTCLK External clock
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 83
10.5.2 Main Clock Control B
Name:  MCLKCTRLB
Offset:  0x01
Reset:  0x11
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
PDIV[3:0] PEN
Access R/W R/W R/W R/W R/W
Reset 1 0 0 0 1
Bits 4:1 – PDIV[3:0] Prescaler Division
If the Prescaler Enable (PEN) bit is written to ‘1’, these bits define the division ratio of the main clock
prescaler.
These bits can be written during run-time to vary the clock frequency of the system to suit the application
requirements.
The user software must ensure a correct configuration of input frequency (CLK_MAIN) and prescaler
settings, such that the resulting frequency of CLK_PER never exceeds the allowed maximum (see
Electrical Characteristics).
Value Description
Value Division
0x0 2
0x1 4
0x2 8
0x3 16
0x4 32
0x5 64
0x8 6
0x9 10
0xA 12
0xB 24
0xC 48
other Reserved
Bit 0 – PEN Prescaler Enable
This bit must be written '1' to enable the prescaler. When enabled, the division ratio is selected by the
PDIV bit field.
When this bit is written to '0', the main clock will pass through undivided (CLK_PER=CLK_MAIN),
regardless of the value of PDIV.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 84
10.5.3 Main Clock Lock
Name:  MCLKLOCK
Offset:  0x02
Reset:  Based on OSCLOCK in FUSE.OSCCFG
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCKEN
Access R/W
Reset x
Bit 0 – LOCKEN Lock Enable
Writing this bit to '1' will lock the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers, and, if
applicable, the calibration settings for the current main clock source from further software updates. Once
locked, the CLKCTRL.MCLKLOCK registers cannot be accessed until the next hardware Reset.
This provides protection for the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers and
calibration settings for the main clock source from unintentional modification by software.
At Reset, the LOCKEN bit is loaded based on the OSCLOCK bit in FUSE.OSCCFG.
Related Links
6.10 Configuration and User Fuses (FUSE)
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 85
10.5.4 Main Clock Status
Name:  MCLKSTATUS
Offset:  0x03
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
EXTS XOSC32KS OSC32KS OSC20MS SOSC
Access R R R R R
Reset 0 0 0 0 0
Bit 7 – EXTS External Clock Status
Value Description
0EXTCLK has not started
1EXTCLK has started
Bit 6 – XOSC32KS XOSC32K Status
The Status bit will only be available if the source is requested as the main clock or by another module. If
the oscillator RUNSTDBY bit is set but the oscillator is unused/not requested, this bit will be 0.
Value Description
0XOSC32K is not stable
1XOSC32K is stable
Bit 5 – OSC32KS OSCULP32K Status
The Status bit will only be available if the source is requested as the main clock or by another module. If
the oscillator RUNSTDBY bit is set but the oscillator is unused/not requested, this bit will be 0.
Value Description
0OSCULP32K is not stable
1OSCULP32K is stable
Bit 4 – OSC20MS OSC20M Status
The Status bit will only be available if the source is requested as the main clock or by another module. If
the oscillator RUNSTDBY bit is set but the oscillator is unused/not requested, this bit will be 0.
Value Description
0OSC20M is not stable
1OSC20M is stable
Bit 0 – SOSC Main Clock Oscillator Changing
Value Description
0The clock source for CLK_MAIN is not undergoing a switch
1The clock source for CLK_MAIN is undergoing a switch and will change as soon as the new
source is stable
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 86
10.5.5 16/20 MHz Oscillator Control A
Name:  OSC20MCTRLA
Offset:  0x10
Reset:  0x00
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
RUNSTDBY
Access R/W
Reset 0
Bit 1 – RUNSTDBY Run Standby
This bit forces the oscillator ON in all modes, even when unused by the system. In Standby Sleep mode
this can be used to ensure immediate wake-up and not waiting for oscillator start-up time.
When not requested by peripherals, no oscillator output is provided.
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up time
will be removed when this bit is set.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 87
10.5.6 16/20 MHz Oscillator Calibration A
Name:  OSC20MCALIBA
Offset:  0x11
Reset:  Based on FREQSEL in FUSE.OSCCFG
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
CAL20M[5:0]
Access R/W R/W R/W R/W R/W R/W
Reset x x x x x x
Bits 5:0 – CAL20M[5:0] Calibration
These bits change the frequency around the current center frequency of the OSC20M for fine-tuning.
At Reset, the factory calibrated values are loaded based on the FREQSEL bits in FUSE.OSCCFG.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 88
10.5.7 16/20 MHz Oscillator Calibration B
Name:  OSC20MCALIBB
Offset:  0x12
Reset:  Based on FUSE.OSCCFG
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCK TEMPCAL20M[3:0]
Access R R/W R/W R/W R/W
Reset x x x x x
Bit 7 – LOCK Oscillator Calibration Locked by Fuse
When this bit is set, the calibration settings in CLKCTRL.OSC20MCALIBA and
CLKCTRL.OSC20MCALIBB cannot be changed.
The reset value is loaded from the OSCLOCK bit in the Oscillator Configuration Fuse (FUSE.OSCCFG).
Bits 3:0 – TEMPCAL20M[3:0] Oscillator Temperature Coefficient Calibration
These bits tune the slope of the temperature compensation.
At Reset, the factory calibrated values are loaded based on the FREQSEL bits in FUSE.OSCCFG.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 89
10.5.8 32 KHz Oscillator Control A
Name:  OSC32KCTRLA
Offset:  0x18
Reset:  0x00
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
RUNSTDBY
Access R/W
Reset 0
Bit 1 – RUNSTDBY Run Standby
This bit forces the oscillator ON in all modes, even when unused by the system. In Standby Sleep mode
this can be used to ensure immediate wake-up and not waiting for the oscillator start-up time.
When not requested by peripherals, no oscillator output is provided.
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up time
will be removed when this bit is set.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 90
10.5.9 32.768 kHz Crystal Oscillator Control A
Name:  XOSC32KCTRLA
Offset:  0x1C
Reset:  0x00
Property:  Configuration Change Protection
The SEL and CSUT bits cannot be changed as long as the ENABLE bit is set or the XOSC32K Stable bit
(XOSC32KS) in CLKCTRL.MCLKSTATUS is high.
To change settings in a safe way: write a '0' to the ENABLE bit and wait until XOSC32KS is '0' before re-
enabling the XOSC32K with new settings.
Bit 7 6 5 4 3 2 1 0
CSUT[1:0] SEL RUNSTDBY ENABLE
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 5:4 – CSUT[1:0] Crystal Start-Up Time
These bits select the start-up time for the XOSC32K. It is write protected when the oscillator is enabled
(ENABLE=1).
If SEL=1, the start-up time will not be applied.
Value Name Description
0x0 1K 1k cycles
0x1 16K 16k cycles
0x2 32K 32k cycles
0x3 64K 64k cycles
Bit 2 – SEL Source Select
This bit selects the external source type. It is write protected when the oscillator is enabled (ENABLE=1).
Value Description
0External crystal
1External clock on TOSC1 pin
Bit 1 – RUNSTDBY Run Standby
Writing this bit to '1' starts the crystal oscillator and forces the oscillator ON in all modes, even when
unused by the system if the ENABLE bit is set. In Standby Sleep mode this can be used to ensure
immediate wake-up and not waiting for oscillator start-up time. When this bit is '0', the crystal oscillator is
only running when requested and the ENABLE bit is set.
The output of XOSC32K is not sent to other peripherals unless it is requested by one or more peripherals.
When the RUNSTDBY bit is set there will only be a delay of two to three crystal oscillator cycles after a
request until the oscillator output is received, if the initial crystal start-up time has already completed.
According to RUNSTBY bit, the oscillator will be turned ON all the time if the device is in Active, Idle, or
Standby Sleep mode, or only be enabled when requested.
This bit is I/O protected to prevent unintentional enabling of the oscillator.
Bit 0 – ENABLE Enable
When this bit is written to '1', the configuration of the respective input pins is overridden to TOSC1 and
TOSC2. Also, the Source Select bit (SEL) and Crystal Start-Up Time (CSUT) become read-only.
This bit is I/O protected to prevent unintentional enabling of the oscillator.
ATtiny1614
CLKCTRL - Clock Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 91
11. SLPCTRL - Sleep Controller
11.1 Features
Power management for adjusting power consumption and functions
Three sleep modes:
– Idle
– Standby
– Power-Down
Configurable Standby Sleep mode where peripherals can be configured as ON or OFF.
11.2 Overview
Sleep modes are used to shut down peripherals and clock domains in the device in order to save power.
The Sleep Controller (SLPCTRL) controls and handles the transitions between active and sleep mode.
There are in total four modes available:
One active mode in which the software is executed
Three sleep modes:
– Idle
– Standby
– Power-Down
All sleep modes are available and can be entered from active mode. In active mode, the CPU is
executing application code. When the device enters sleep mode, program execution is stopped and
interrupts or a reset is used to wake the device again. The application code decides which sleep mode to
enter and when.
Interrupts are used to wake the device from sleep. The available interrupt wake-up sources depend on
the configured sleep mode. When an interrupt occurs, the device will wake up and execute the interrupt
service routine before continuing normal program execution from the first instruction after the SLEEP
instruction. Any Reset will take the device out of a sleep mode.
The content of the register file, SRAM and registers are kept during sleep. If a Reset occurs during sleep,
the device will reset, start, and execute from the Reset vector.
ATtiny1614
SLPCTRL - Sleep Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 92
SLEEP \nstruclion Imerrupl Requesl SLPCTRL Sleep sme Inlerrum Reques: —> Peripheral
11.2.1 Block Diagram
Figure 11-1. Sleep Controller in System
SLPCTRL
SLEEP Instruction
Interrupt Request
Peripheral
Interrupt Request
Sleep State
CPU
11.2.2 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 11-1. SLPCTRL System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections No -
Interrupts No -
Events No -
Debug Yes UPDI
11.2.2.1 Clocks
This peripheral depends on the peripheral clock.
Related Links
10. CLKCTRL - Clock Controller
11.2.2.2 I/O Lines and Connections
Not applicable.
11.2.2.3 Interrupts
Not applicable.
11.2.2.4 Events
Not applicable.
11.2.2.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. The SLPCTRL is only affected
by a break in debug operation: If the SLPCTRL is in a sleep mode when a break occurs, the device will
wake up and the SLPCTRL will go to Active mode, even if there are no pending interrupt requests.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar,
improper operation or data loss may result during halted debugging.
ATtiny1614
SLPCTRL - Sleep Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 93
11.3 Functional Description
11.3.1 Initialization
To put the device into a sleep mode, follow these steps:
Configure and enable the interrupts that shall be able to wake the device from sleep. Also, enable
global interrupts.
WARNING
If there are no interrupts enabled when going to sleep, the device cannot wake up again.
Only a Reset will allow the device to continue operation.
Select the sleep mode to be entered and enable the Sleep Controller by writing to the Sleep Mode
bits (SMODE) and the Enable bit (SEN) in the Control A register (SLPCTRL.CTRLA). A SLEEP
instruction must be run to make the device actually go to sleep.
11.3.2 Operation
11.3.2.1 Sleep Modes
In addition to Active mode, there are three different sleep modes, with decreasing power consumption
and functionality.
Idle The CPU stops executing code, no peripherals are disabled.
All interrupt sources can wake-up the device.
Standby The user can configure peripherals to be enabled or not, using the respective RUNSTBY bit.
This means that the power consumption is highly dependent on what functionality is enabled,
and thus may vary between the Idle and Power-Down levels.
SleepWalking is available for the ADC module.
The wake-up sources are pin interrupts, TWI address match, UART Start-of-Frame interrupt
(if USART is enabled to run in Standby), ADC window interrupt (if PTC enabled to run in
Standby), RTC interrupt (if RTC enabled to run in Standby), and TCB interrupt.
Power-
Down
Only the WDT and the PIT (a component of the RTC) are active.
The only wake-up sources are the pin change interrupt and TWI address match.
Table 11-2. Sleep Mode Activity Overview
Group Peripheral Active in Sleep Mode
Clock Idle Standby Power-Down
Active Clock
Domain
CPU CLK_CPU
Peripherals CLK_PER X
RTC CLK_RTC X X*
ADC/PTC CLK_PER X X*
PIT (RTC) CLK_RTC X X X
WDT CLK_WDT X X X
ATtiny1614
SLPCTRL - Sleep Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 94
...........continued
Group Peripheral Active in Sleep Mode
Clock Idle Standby Power-Down
Oscillators Main Clock Source X X*
RTC Clock Source X X*
WDT Oscillator X X X
Wake-Up
Sources
INTn and Pin Change X X X
TWI Address Match X X X
Periodic Interrupt Timer X X X
UART Start-of-Frame X X*
ADC/PTC Window X X*
RTC Interrupt X X*
All other Interrupts X
Note: 
X means active. X* indicates that the RUNSTBY bit of the corresponding peripheral must be set to
enter the active state.
11.3.2.2 Wake-Up Time
The normal wake-up time for the device is six main clock cycles (CLK_PER), plus the time it takes to start
up the main clock source:
In Idle Sleep mode, the main clock source is kept running so it will not be any extra wake-up time.
In Standby Sleep mode, the main clock might be running so it depends on the peripheral
configuration.
In Power-Down Sleep mode, only the ULP 32 KHz oscillator and RTC clock may be running if it is
used by the BOD or WDT. All other clock sources will be OFF.
Table 11-3. Sleep Modes and Start-Up Time
Sleep Mode Start-Up Time
IDLE 6 CLK
Standby 6 CLK + OSC start-up
Power-Down 6 CLK + OSC start-up
The start-up time for the different clock sources is described in the Clock Controller (CLKCTRL) section.
In addition to the normal wake-up time, it is possible to make the device wait until the BOD is ready
before executing code. This is done by writing 0x3 to the BOD Operation mode in Active and Idle bits
(ACTIVE) in the BOD Configuration fuse (FUSE.BODCFG). If the BOD is ready before the normal wake-
up time, the total wake-up time will be the same. If the BOD takes longer than the normal wake-up time,
the wake-up time will be extended until the BOD is ready. This ensures correct supply voltage whenever
code is executed.
ATtiny1614
SLPCTRL - Sleep Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 95
11.3.3 Configuration Change Protection
Not applicable.
ATtiny1614
SLPCTRL - Sleep Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 96
11.4 Register Summary - SLPCTRL
Offset Name Bit Pos.
0x00 CTRLA 7:0 SMODE[1:0] SEN
11.5 Register Description
ATtiny1614
SLPCTRL - Sleep Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 97
11.5.1 Control A
Name:  CTRLA
Offset:  0x00
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
SMODE[1:0] SEN
Access R R R R R R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 2:1 – SMODE[1:0] Sleep Mode
Writing these bits selects the sleep mode entered when the Sleep Enable bit (SEN) is written to '1' and
the SLEEP instruction is executed.
Value Name Description
0x0 IDLE Idle Sleep mode enabled
0x1 STANDBY Standby Sleep mode enabled
0x2 PDOWN Power-Down Sleep mode enabled
other - Reserved
Bit 0 – SEN Sleep Enable
This bit must be written to '1' before the SLEEP instruction is executed to make the MCU enter the
selected sleep mode.
ATtiny1614
SLPCTRL - Sleep Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 98
RESET SOURCES V» X mep Reslsmr FILTER TCD pm overnde settings (Loaded lmm (uses) UPDI An other Peripherals
12. RSTCTRL - Reset Controller
12.1 Features
Reset the device and set it to an initial state
Reset Flag register for identifying the Reset source in the software
Multiple Reset sources:
Power supply Reset sources: Brown-out Detect (BOD), Power-on Reset (POR)
User Reset sources: External Reset pin (RESET), Watchdog Reset (WDT), Software Reset
(SW), and UPDI Reset
12.2 Overview
The Reset Controller (RSTCTRL) manages the Reset of the device. It issues a device Reset, sets the
device to its initial state, and allows the Reset source to be identified by the software.
12.2.1 Block Diagram
Figure 12-1. Reset System Overview
RESET SOURCES
POR
BOD
WDT
CPU (SW)
RESET CONTROLLER
UPDI
UPDI
All other
Peripherals
TCD pin
override settings
(Loaded from fuses)
RESET External Reset
FILTER
VDD
Pull-up
Resistor
12.2.2 Signal Description
Signal Description Type
RESET External Reset (active-low) Digital input
ATtiny1614
RSTCTRL - Reset Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 99
12.3 Functional Description
12.3.1 Initialization
The Reset Controller (RSTCTRL) is always enabled, but some of the Reset sources must be enabled
(either by fuses or by software) before they can request a Reset.
After any Reset, the Reset source that caused the Reset is found in the Reset Flag register
(RSTCTRL.RSTFR).
After a Power-on Reset, only the POR flag will be set.
The flags are kept until they are cleared by writing a '1' to them.
After Reset from any source, all registers that are loaded from fuses are reloaded.
12.3.2 Operation
12.3.2.1 Reset Sources
There are two kinds of sources for Resets:
Power supply Resets, which are caused by changes in the power supply voltage: Power-on Reset
(POR) and Brown-out Detector (BOD).
User Resets, which are issued by the application, by the debug operation, or by pin changes
(Software Reset, Watchdog Reset, UPDI Reset, and external Reset pin RESET).
12.3.2.1.1 Power-On Reset (POR)
A Power-on Reset (POR) is generated by an on-chip detection circuit. The POR is activated when the
VDD rises until it reaches the POR threshold voltage. The POR is always enabled and will also detect
when the VDD falls below the threshold voltage.
All volatile logic is reset on POR. All fuses are reloaded after the Reset is released.
12.3.2.1.2 Brown-Out Detector (BOD) Reset Source
The on-chip Brown-out Detection circuit will monitor the VDD level during operation by comparing it to a
fixed trigger level. The trigger level for the BOD can be selected by fuses. If BOD is unused in the
application, it is forced to a configured level in order to ensure safe operation during chip erase.
All logic is reset on BOD Reset, except the BOD configuration. All fuses are reloaded after the Reset is
released.
Related Links
17. BOD - Brown-out Detector
12.3.2.1.3 Software Reset
The software Reset makes it possible to issue a system Reset from software. The Reset is generated by
writing a '1' to the Software Reset Enable bit (SWRE) in the Software Reset register (RSTCTRL.SWRR).
The Reset will take place immediately after the bit is written and the device will be kept in reset until the
Reset sequence is completed. All logic is reset on software Reset, except UPDI and BOD configuration.
All fuses are reloaded after the Reset is released.
12.3.2.1.4 External Reset
The external Reset is enabled by fuse (see fuse map).
When enabled, the external Reset requests a Reset as long as the RESET pin is low. The device will stay
in Reset until RESET is high again. All logic is reset on external reset, except UPDI and BOD
configuration. All fuses are reloaded after the Reset is released.
ATtiny1614
RSTCTRL - Reset Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 100
Related Links
6.10 Configuration and User Fuses (FUSE)
12.3.2.1.5 Watchdog Reset
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. If the WDT is
not reset from software according to the programmed time-out period, a Watchdog Reset will be issued.
See the WDT documentation for further details.
All logic is reset on WDT Reset, except UPDI and BOD configuration. All fuses are reloaded after the
Reset is released.
Related Links
19. WDT - Watchdog Timer
12.3.2.1.6 Universal Program Debug Interface (UPDI) Reset
The UPDI contains a separate Reset source that is used to reset the device during external programming
and debugging. The Reset source is accessible only from external debuggers and programmers. All logic
is reset on UPDI Reset, except the UPDI itself and BOD configuration. All fuses are reloaded after the
Reset is released. See UPDI chapter on how to generate a UPDI Reset request.
Related Links
33. UPDI - Unified Program and Debug Interface
12.3.2.2 Reset Time
The Reset time can be split in two.
The first part is when any of the Reset sources are active. This part depends on the input to the Reset
sources. The external Reset is active as long as the RESET pin is low, the Power-on Reset (POR) and
Brown-out Detector (BOD) is active as long as the supply voltage is below the Reset source threshold.
When all the Reset sources are released, an internal Reset initialization of the device is done. This time
will be increased with the start-up time given by the start-up time fuse setting (SUT in FUSE.SYSCFG1).
The internal Reset initialization time will also increase if the CRCSCAN is configured to run at start-up
(CRCSRC in FUSE.SYSCFG0).
12.3.3 Sleep Mode Operation
The Reset Controller continues to operate in all active and sleep modes.
12.3.4 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves
the protected register unchanged.
The following registers are under CCP:
Table 12-1. RSTCTRL - Registers Under Configuration Change Protection
Register Key
RSTCTRL.SWRR IOREG
Related Links
ATtiny1614
RSTCTRL - Reset Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 101
8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
ATtiny1614
RSTCTRL - Reset Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 102
12.4 Register Summary - RSTCTRL
Offset Name Bit Pos.
0x00 RSTFR 7:0 UPDIRF SWRF WDRF EXTRF BORF PORF
0x01 SWRR 7:0 SWRE
12.5 Register Description
ATtiny1614
RSTCTRL - Reset Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 103
12.5.1 Reset Flag Register
Name:  RSTFR
Offset:  0x00
Reset:  0xXX
Property:  -
All flags are cleared by writing a '1' to them. They are also cleared by a Power-on Reset, with the
exception of the Power-On Reset Flag (PORF).
Bit 7 6 5 4 3 2 1 0
UPDIRF SWRF WDRF EXTRF BORF PORF
Access R R R/W R/W R/W R/W R/W R/W
Reset 0 0 x x x x x x
Bit 5 – UPDIRF UPDI Reset Flag
This bit is set if a UPDI Reset occurs.
Bit 4 – SWRF Software Reset Flag
This bit is set if a Software Reset occurs.
Bit 3 – WDRF Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs.
Bit 2 – EXTRF External Reset Flag
This bit is set if an External Reset occurs.
Bit 1 – BORF Brown-Out Reset Flag
This bit is set if a Brown-out Reset occurs.
Bit 0 – PORF Power-On Reset Flag
This bit is set if a Power-on Reset occurs.
This flag is only cleared by writing a '1' to it.
After a POR, only the POR flag is set and all other flags are cleared. No other flags can be set before a
full system boot is run after the POR.
ATtiny1614
RSTCTRL - Reset Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 104
12.5.2 Software Reset Register
Name:  SWRR
Offset:  0x01
Reset:  0x00
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
SWRE
Access R R R R R R R R/W
Reset 0 0 0 0 0 0 0 0
Bit 0 – SWRE Software Reset Enable
When this bit is written to '1', a software Reset will occur.
This bit will always read as '0'.
ATtiny1614
RSTCTRL - Reset Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 105
13. CPUINT - CPU Interrupt Controller
13.1 Features
Short and Predictable Interrupt Response Time
Separate Interrupt Configuration and Vector Address for Each Interrupt
Interrupt Prioritizing by Level and Vector Address
Non-Maskable Interrupts (NMI) for Critical Functions
Two Interrupt Priority Levels: 0 (normal) and 1 (high)
One of the interrupt requests can optionally be assigned as a priority level 1 interrupt
Optional round robin priority scheme for priority level 0 interrupts
Interrupt Vectors Optionally Placed in the Application Section or the Boot Loader Section
Selectable Compact Vector Table
13.2 Overview
An interrupt request signals a change of state inside a peripheral and can be used to alter program
execution. Peripherals can have one or more interrupts, and all are individually enabled and configured.
When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt
condition occurs.
The CPU Interrupt Controller (CPUINT) handles and prioritizes interrupt requests. When an interrupt is
enabled and the interrupt condition occurs, the CPUINT will receive the interrupt request. Based on the
interrupt's priority level and the priority level of any ongoing interrupts, the interrupt request is either
acknowledged or kept pending until it has priority. When an interrupt request is acknowledged by the
CPUINT, the Program Counter is set to point to the interrupt vector. The interrupt vector is normally a
jump to the interrupt handler (i.e., the software routine that handles the interrupt). After returning from the
interrupt handler, program execution continues from where it was before the interrupt occurred. One
instruction is always executed before any pending interrupt is served.
The CPUINT Status register (CPUINT.STATUS) contains state information that ensures that the CPUINT
returns to the correct interrupt level when the RETI (interrupt return) instruction is executed at the end of
an interrupt handler. Returning from an interrupt will return the CPUINT to the state it had before entering
the interrupt. CPUINT.STATUS is not saved automatically upon an interrupt request.
By default, all peripherals are priority level 0. It is possible to set one single interrupt vector to the higher
priority level 1. Interrupts are prioritized according to their priority level and their interrupt vector address.
Priority level 1 interrupts will interrupt level 0 interrupt handlers. Among priority level 0 interrupts, the
priority is determined from the interrupt vector address, where the lowest interrupt vector address has the
highest interrupt priority.
Optionally, a round robin scheduling scheme can be enabled for priority level 0 interrupts. This ensures
that all interrupts are serviced within a certain amount of time.
Interrupt generation must be globally enabled by writing a '1' to the Global Interrupt Enable bit (I) in the
CPU Status register (CPU.SREG). This bit is not cleared when an interrupt is acknowledged.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 106
13.2.1 Block Diagram
Figure 13-1. CPUINT Block Diagram
INT REQ
INT LEVEL
INT ACK
Peripheral 1
Peripheral n
Interrupt Controller
Sleep
Controller
CPU
Priority
Decoder
STATUS
CPU.SREG
INT REQ
INT REQ
Global
Interrupt
Enable
CPU "RETI"
CPU INT ACK
CPU INT REQ
Wake-up
LVL0PRI
LVL1VEC
13.2.2 Signal Description
Not applicable.
13.2.3 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 13-1. CPUINT System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections No -
Interrupts No -
Events No -
Debug Yes UPDI
Related Links
13.2.3.5 Debug Operation
13.2.3.1 Clocks
13.2.3.1 Clocks
This peripheral depends on the peripheral clock.
Related Links
10. CLKCTRL - Clock Controller
13.2.3.2 I/O Lines and Connections
Not applicable.
13.2.3.3 Interrupts
Not applicable.
13.2.3.4 Events
Not applicable.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 107
13.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging
mode will halt normal operation of the peripheral.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar,
improper operation or data loss may result during halted debugging.
Related Links
33. UPDI - Unified Program and Debug Interface
13.3 Functional Description
13.3.1 Initialization
An interrupt must be initialized in the following order:
1. Configure the CPUINT if the default configuration is not adequate (optional):
Vector handling is configured by writing to the respective bits (IVSEL and CVT) in the Control A
register (CPUINT.CTRLA).
Vector prioritizing by round robin is enabled by writing a '1' to the Round Robin Priority Enable
bit (LVL0RR) in CPUINT.CTRLA.
Select the priority level 1 vector by writing its address to the Interrupt Vector (LVL1VEC) in the
Level 1 Priority register (CPUINT.LVL1VEC).
2. Configure the interrupt conditions within the peripheral, and enable the peripheral's interrupt.
3. Enable interrupts globally by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status
register (CPU.SREG).
13.3.2 Operation
13.3.2.1 Enabling, Disabling, and Resetting
Global enabling of interrupts is done by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status
register (CPU.SREG). To disable interrupts globally, write a '0' to the I bit in CPU.SREG.
The desired interrupt lines must also be enabled in the respective peripheral, by writing to the peripheral's
Interrupt Control register (peripheral.INTCTRL).
Interrupt flags are not automatically cleared after the interrupt is executed. The respective INTFLAGS
register descriptions provide information on how to clear specific flags.
13.3.2.2 Interrupt Vector Locations
The interrupt vector placement is dependent on the value of Interrupt Vector Select bit (IVSEL) in the
Control A register (CPUINT.CTRLA). Refer to the IVSEL description in CPUINT.CTRLA for the possible
locations.
If the program never enables an interrupt source, the interrupt vectors are not used, and regular program
code can be placed at these locations.
13.3.2.3 Interrupt Response Time
The minimum interrupt response time for all enabled interrupts is three CPU clock cycles: one cycle to
finish the ongoing instruction, two cycles to store the Program Counter to the stack, and three cycles(1) to
jump to the interrupt handler (JMP).
After the Program Counter is pushed on the stack, the program vector for the interrupt is executed. See
Figure 13-2, first diagram.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 108
The jump to the interrupt handler takes three clock cycles(1). If an interrupt occurs during execution of a
multicycle instruction, this instruction is completed before the interrupt is served. See Figure 13-2, second
diagram.
If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is
increased by five clock cycles. In addition, the response time is increased by the start-up time from the
selected sleep mode. See Figure 13-2, third diagram.
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the
Program Counter. During these clock cycles, the Program Counter is popped from the stack and the
Stack Pointer is incremented.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 109
Single-Cycle Instruction W H H was was we: ”WW" 00“"‘5' PC ADDR Meow ‘Auuwz‘ 7 "\nstruction" \ mst "store PC" JMP mt req / § mt ack [ \ M c'k \ \ \ \ \ \ ProgramCounter PC _ IVECADDR -.\$VDER°.‘XNLVDE§ _ "\nstruction" i inst "store PC" JMP mtreq { § mack i \ S mm m m m m ProgramCoumer pg; :55; [gngcHAvaDsé "\nstruction" s‘eep "slare PC" JMP mt req J \\ WK EEK / \
Figure 13-2. Interrupt Execution of a Single-Cycle Instruction, Multicycle Instruction, and From
Sleep(1)
Single-Cycle Instruction
Multicycle Instruction
Sleep
Note: 
1. Devices with 8 KB of Flash or less use RJMP instead of JMP, which takes only two clock cycles.
13.3.2.4 Interrupt Priority
All interrupt vectors are assigned to one of three possible priority levels as shown in the table. An
interrupt request from a high priority source will interrupt any ongoing interrupt handler from a normal
priority source. When returning from the high priority interrupt handler, the execution of the normal priority
interrupt handler will resume.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 110
Table 13-2. Interrupt Priority Levels
Priority Level Source
Highest Non-Maskable Interrupt (NMI) Device dependent and statically
assigned
... High Priority (Level 1) One vector is optionally user
selectable as Level 1
Lowest Normal Priority (Level 0) The remaining interrupt vectors
13.3.2.5 Scheduling of Normal Priority Interrupts
13.3.2.5.1 Non-Maskable Interrupts (NMI)
An NMI will be executed regardless of the setting of the I bit in CPU.SREG, and it will never change the I
bit. No other interrupt can interrupt an NMI handler. If more than one NMI is requested at the same time,
priority is static according to the interrupt vector address, where the lowest address has the highest
priority.
Which interrupts are non-maskable is device-dependent and not subject to configuration. Non-maskable
interrupts must be enabled before they can be used. Refer to the Interrupt Vector Mapping of the device
for available NMI lines.
Related Links
7.2 Interrupt Vector Mapping
13.3.2.5.2 Static Scheduling
If several level 0 interrupt requests are pending at the same time, the one with the highest priority is
scheduled for execution first. The CPUINT.LVL0PRI register makes it possible to change the default
priority. The Reset value for CPUINT.LVL0PRI is zero, resulting in a default priority as shown in the
following figure. As the figure shows, IVEC0 has the highest priority, and IVECn has the lowest priority.
Figure 13-3. Static Scheduling when CPUINT.LVL0PRI is Zero
:
:
:
:
:
:
Lowest Priority
Highest Priority
IVEC 0
IVEC Y
IVEC Y+1
IVEC n
Lowest Address
Highest Address
IVEC 1
The default priority can be changed by writing to the CPUINT.LVL0PRI register. The value written to the
register will identify the vector number with the lowest priority. The next interrupt vector in IVEC will have
the highest priority, see the following figure. In this figure, the value Y has been written to
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 111
CPUINT.LVL0PRI, so that interrupt vector Y+1 has the highest priority. Note that in this case, the priorities
will "wrap" so that IVEC0 has lower priority than IVECn.
Refer to the Interrupt Vector Mapping of the device for available interrupt requests and their interrupt
vector number.
Figure 13-4. Static Scheduling when CPUINT.LVL0PRI is Different From Zero
:
:
:
:
:
:
IVEC 0
IVEC Y
IVEC Y+1
IVEC n
Lowest Priority
Highest Priority
IVEC 1
Lowest Address
Highest Address
Related Links
7.2 Interrupt Vector Mapping
13.3.2.5.3 Round Robin Scheduling
Static scheduling may cause starvation, i.e. some interrupts might never be serviced. To avoid this, the
CPUINT offers round robin scheduling for normal priority (LVL0) interrupts. In round robin scheduling,
CPUINT.LVL0PRI contains the number of the vector number in IVEC with the lowest priority. This register
is automatically updated by hardware with the interrupt vector number for the last acknowledged LVL0
interrupt. This interrupt vector will, therefore, have the lowest priority next time one or more LVL0
interrupts are pending. Figure 13-5 explains the new priority ordering after IVEC Y was the last interrupt
to be acknowledged, and after IVEC Y+1 was the last interrupt to be acknowledged.
Round robin scheduling for LVL0 interrupt requests is enabled by writing a ‘1’ to the Round Robin Priority
Enable bit (LVL0RR) in the Control A register (CPUINT.CTRLA).
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 112
IVEC v was ‘35! acknowledged IVEC YM was Izs| acknowledged
Figure 13-5. Round Robin Scheduling
:
:
:
:
:
:
:
:
:
:
:
:
IVEC Y was last acknowledged
interrupt
IVEC Y+1 was last acknowledged
interrupt
IVEC 0
IVEC Y
IVEC Y+1
IVEC n
IVEC Y+2
IVEC Y+1
IVEC Y
IVEC 0
IVEC n
Lowest Priority
Highest Priority Lowest Priority
Highest Priority
13.3.2.5.4 Compact Vector Table
The Compact Vector Table (CVT) is a feature to allow writing of compact code.
When CVT is enabled by writing a '1' to the CVT bit in the Control A register (CPUINT.CTRLA), the vector
table contains these three interrupt vectors:
1. The non-maskable interrupts (NMI) at vector address 1.
2. The priority level 1 (LVL1) interrupt at vector address 2.
3. All priority level 0 (LVL0) interrupts share vector address 3.
This feature is most suitable for applications using a small number of interrupt generators.
13.3.3 Events
Not applicable.
13.3.4 Sleep Mode Operation
Not applicable.
13.3.5 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves
the protected register unchanged.
The following registers are under CCP:
Table 13-3. INTCTRL - Registers under Configuration Change Protection
Register Key
IVSEL in CPUINT.CTRLA IOREG
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 113
...........continued
Register Key
CVT in CPUINT.CTRLA IOREG
Related Links
8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 114
13.4 Register Summary - CPUINT
Offset Name Bit Pos.
0x00 CTRLA 7:0 IVSEL CVT LVL0RR
0x01 STATUS 7:0 NMIEX LVL1EX LVL0EX
0x02 LVL0PRI 7:0 LVL0PRI[7:0]
0x03 LVL1VEC 7:0 LVL1VEC[7:0]
13.5 Register Description
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 115
13.5.1 Control A
Name:  CTRLA
Offset:  0x00
Reset:  0x00
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
IVSEL CVT LVL0RR
Access R/W R/W R/W
Reset 0 0 0
Bit 6 – IVSEL Interrupt Vector Select
If the boot section is defined, it will be placed before the application section. The actual start address of
the application section is determined by the BOOTEND fuse.
This bit is protected by the Configuration Change Protection mechanism.
Value Description
0Interrupt vectors are placed at the start of the application section of the Flash
1Interrupt vectors are placed at the start of the boot section of the Flash
Bit 5 – CVT Compact Vector Table
This bit is protected by the Configuration Change Protection mechanism.
Value Description
0Compact Vector Table function is disabled
1Compact Vector Table function is enabled
Bit 0 – LVL0RR Round Robin Priority Enable
This bit is not protected by the Configuration Change Protection mechanism.
Value Description
0Priority is fixed for priority level 0 interrupt requests: The lowest interrupt vector address has
the highest priority.
1Round Robin priority scheme is enabled for priority level 0 interrupt requests
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 116
13.5.2 Status
Name:  STATUS
Offset:  0x01
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
NMIEX LVL1EX LVL0EX
Access R R R
Reset 0 0 0
Bit 7 – NMIEX Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag is cleared when returning (RETI) from
the interrupt handler.
Bit 1 – LVL1EX Level 1 Interrupt Executing
This flag is set when a priority level 1 interrupt is executing, or when the interrupt handler has been
interrupted by an NMI. The flag is cleared when returning (RETI) from the interrupt handler.
Bit 0 – LVL0EX Level 0 Interrupt Executing
This flag is set when a priority level 0 interrupt is executing, or when the interrupt handler has been
interrupted by a priority level 1 interrupt or an NMI. The flag is cleared when returning (RETI) from the
interrupt handler.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 117
13.5.3 Interrupt Priority Level 0
Name:  LVL0PRI
Offset:  0x02
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
LVL0PRI[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – LVL0PRI[7:0] Interrupt Priority Level 0
When Round Robin is enabled (the LVL0RR bit in CPUINT.CTRLA is '1'), this bit field stores the vector of
the last acknowledged priority level 0 (LVL0) interrupt. The stored vector will have the lowest priority next
time one or more LVL0 interrupts are pending.
If Round Robin is disabled (the LVL0RR bit in CPUINT.CTRLA is '0'), the vector address-based priority
scheme (lowest address has the highest priority) is governing the priorities of LVL0 interrupt requests.
If a system Reset is asserted, the lowest interrupt vector address will have the highest priority within the
LVL0.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 118
13.5.4 Interrupt Vector with Priority Level 1
Name:  LVL1VEC
Offset:  0x03
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
LVL1VEC[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – LVL1VEC[7:0] Interrupt Vector with Priority Level 1
This bit field contains the number of the single vector with increased priority level 1 (LVL1).
If this bit field has the value 0x00, no vector has LVL1. Consequently, the LVL1 interrupt is disabled.
ATtiny1614
CPUINT - CPU Interrupt Controller
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 119
14. EVSYS - Event System
14.1 Features
System for Direct Peripheral-to-Peripheral Signaling
Peripherals can Directly Produce, Use, and React to Peripheral Events
Short Response Time
Up to Six Parallel Event Channels Available; Four Asynchronous and Two Synchronous
Channels can be Configured to Have One Triggering Peripheral Action and Multiple Peripheral Users
Peripherals can Directly Trigger and React to Events from Other Peripherals
Events can be Sent and/or Received by Most Peripherals, and by Software
Works in Active mode and Standby Sleep mode
14.2 Overview
The Event System (EVSYS) enables direct peripheral-to-peripheral signaling. It allows a change in one
peripheral (the event generator) to trigger actions in other peripherals (the event users) through event
channels, without using the CPU. It is designed to provide short and predictable response times between
peripherals, allowing for autonomous peripheral control and interaction, and also for the synchronized
timing of actions in several peripheral modules. It is thus a powerful tool for reducing the complexity, size,
and the execution time of the software.
A change of the event generator's state is referred to as an event and usually corresponds to one of the
peripheral's interrupt conditions. Events can be directly forwarded to other peripherals using the
dedicated event routing network. The routing of each channel is configured in software, including event
generation and use.
Only one trigger from an event generator peripheral can be routed on each channel, but multiple
channels can use the same generator source. Multiple peripherals can use events from the same
channel.
A channel path can be either asynchronous or synchronous to the main clock. The mode must be
selected based on the requirements of the application.
The Event System can directly connect analog and digital converters, analog comparators, I/O port pins,
the real-time counter, timer/counters, and the configurable custom logic peripheral. Events can also be
generated from software and the peripheral clock.
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 120
‘ Svnc event channe‘ "k" ‘Asvnc event channel '\" LH
14.2.1 Block Diagram
Figure 14-1. Block Diagram
Sync user x
Sync user 0
Sync event channel ”k”
Async event channel ”l”
Sync event channel 0
Async event channel 0
Sync source 0
Sync source 1
Sync source n
Async source 0
Async source 1
Async source m
SYNCSTROBE
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
To sync user
To async user
SYNCUSER
Async user 0
Async user y
ASYNCUSER
ASYNCCH
SYNCCH
ASYNCSTROBE
Figure 14-2. Example of Event Source, Generator, User, and Action
|
Event
Routing
Network Single
Conversion
Channel Sweep
Compare Match
Over-/Underflow
Error
Event Generator Event User
Event Source Event Action
Event Action Selection
Timer/Counter ADC
Note: 
1. For an overview of peripherals supporting events, refer the block diagram of the device.
2. For a list of event generators, refer to the Channel n Generator Selection registers
(EVSYS.SYNCCH and EVSYS.ASYNCCH).
3. For a list of event users, refer to the User Channel n Input Selection registers (EVSYS.SYNCUSER
and EVSYS.ASYNCUSER).
Related Links
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 121
14.5.4 SYNCCH
14.5.3 ASYNCCH
14.5.6 SYNCUSER
14.5.5 ASYNCUSER
14.2.2 Signal Description
Internal Event Signaling
The event signaling can happen either synchronously or asynchronously to the main clock (CLK_MAIN).
Depending on the underlying event, the event signal can be a pulse with a duration of one clock cycle, or
a level signal (similar to a status flag).
Event Output to Pin
Signal Type Description
EVOUT[2:0] Digital Output Event Output
Related Links
14.2.3.2 I/O Lines
10.2.1 Block Diagram - CLKCTRL
14.2.3 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 14-1. EVSYS System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections Yes PORTMUX
Interrupts No -
Events Yes EVSYS
Debug Yes UPDI
Related Links
14.2.3.1 Clocks
14.3.5 Debug Operation
14.2.3.1 Clocks
The EVSYS uses the peripheral clock for I/O registers and software events. When correctly set up, the
routing network can also be used in sleep modes without any clock. Software events will not work in
sleep modes where the peripheral clock is halted.
Related Links
10. CLKCTRL - Clock Controller
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 122
14.2.3.2 I/O Lines
The EVSYS can output three event channels asynchronously on pins. The output signals are called
EVOUT[2:0].
1. Configure which event channel (one of SYNCCH[1:0] or ASYNCCH[3:0]) is output on which
EVOUTn bit by writing to EVSYS.ASYNCUSER10, EVSYS.ASYNCUSER9, or
EVSYS.ASYNCUSER8, respectively.
2. Optional: configure the pin properties using the port peripheral.
3. Enable the pin output by writing '1' to the respective EVOUTn bit in the Control A register of the
PORTMUX peripheral (PORTMUX.CTRLA).
Related Links
15. PORTMUX - Port Multiplexer
16. PORT - I/O Pin Configuration
14.5.5 ASYNCUSER
14.3 Functional Description
14.3.1 Initialization
Before enabling events within the device, the event users multiplexer and event channels must be
configured.
Related Links
14.3.2.1 Event User Multiplexer Setup
14.3.2.2 Event System Channel
14.3.2 Operation
14.3.2.1 Event User Multiplexer Setup
The event user multiplexer selects the channel for an event user. Each event user has one dedicated
event user multiplexer. Each multiplexer is connected to the supported event channel outputs and can be
configured to select one of these channels.
Event users, which support asynchronous events, also support synchronous events. There are also event
users that support only synchronous events.
The event user multiplexers are configured by writing to the corresponding registers:
Event users supporting both synchronous and asynchronous events are configured by writing to the
respective asynchronous User Channel Input Selection n register (EVSYS.ASYNCUSERn).
The users of synchronous-only events are configured by writing to the respective Synchronous User
Channel Input Selection n register (EVSYS.SYNCUSERn).
The default setup of all user multiplexers is OFF.
14.3.2.2 Event System Channel
An event channel can be connected to one of the event generators. Event channels support either
asynchronous generators or synchronous generators.
The source for each asynchronous event channel is configured by writing to the respective Asynchronous
Channel n Input Selection register (EVSYS.ASYNCCHn).
The source for each synchronous event channel is configured by writing to the respective Synchronous
Channel n Input Selection register (EVSYS.SYNCCHn).
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 123
14.3.2.3 Event Generators
Each event channel can receive the events from several event generators. For details on event
generation, refer to the documentation of the corresponding peripheral.
For each event channel, there are several possible event generators, only one of which can be selected
at a time. The event generator trigger is selected for each channel by writing to the respective channel
registers (EVSYS.ASYNCCHn, EVSYS.SYNCCHn). By default, the channels are not connected to any
event generator.
14.3.2.4 Software Event
In a software event, the CPU will “strobe” an event channel by inverting the current value for one system
clock cycle.
A software event is triggered on a channel by writing a '1' to the respective Strobe bit in the appropriate
Channel Strobe register:
Software events on asynchronous channel l are initiated by writing a '1' to the ASYNCSTROBE[l] bit
in the Asynchronous Channel Strobe register (EVSYS.ASYNCSTROBE).
Software events on synchronous channel k are initiated by writing a '1' to the SYNCSTROBE[k] bit in
the Synchronous Channel Strobe register (EVSYS.SYNCSTROBE).
Software events are no different to those produced by event generator peripherals with respect to event
users: when the bit is written to '1', an event will be generated on the respective channel, and received
and processed by the event user.
14.3.3 Interrupts
Not applicable.
14.3.4 Sleep Mode Operation
When configured, the Event System will work in all sleep modes. One exception is software events that
require a system clock.
14.3.5 Debug Operation
This peripheral is unaffected by entering Debug mode.
Related Links
33. UPDI - Unified Program and Debug Interface
14.3.6 Synchronization
Asynchronous events are synchronized and handled by the compatible event users. Event user
peripherals not compatible with asynchronous events can only be configured to listen to synchronous
event channels.
14.3.7 Configuration Change Protection
Not applicable.
Related Links
8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 124
14.4 Register Summary - EVSYS
Offset Name Bit Pos.
0x00 ASYNCSTROBE 7:0 ASYNCSTROBE[7:0]
0x01 SYNCSTROBE 7:0 SYNCSTROBE[7:0]
0x02 ASYNCCH0 7:0 ASYNCCH[7:0]
0x03 ASYNCCH1 7:0 ASYNCCH[7:0]
0x04 ASYNCCH2 7:0 ASYNCCH[7:0]
0x05 ASYNCCH3 7:0 ASYNCCH[7:0]
0x06
...
0x09
Reserved
0x0A SYNCCH0 7:0 SYNCCH[7:0]
0x0B SYNCCH1 7:0 SYNCCH[7:0]
0x0C
...
0x11
Reserved
0x12 ASYNCUSER0 7:0 ASYNCUSER[7:0]
...
0x1E ASYNCUSER12 7:0 ASYNCUSER[7:0]
0x1F
...
0x21
Reserved
0x22 SYNCUSER0 7:0 SYNCUSER[7:0]
0x23 SYNCUSER1 7:0 SYNCUSER[7:0]
14.5 Register Description
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 125
14.5.1 Asynchronous Channel Strobe
Name:  ASYNCSTROBE
Offset:  0x00
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
ASYNCSTROBE[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – ASYNCSTROBE[7:0] Asynchronous Channel Strobe
If the Strobe register location is written, each event channel will be inverted for one system clock cycle
(i.e., a single event is generated).
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 126
14.5.2 Synchronous Channel Strobe
Name:  SYNCSTROBE
Offset:  0x01
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
SYNCSTROBE[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – SYNCSTROBE[7:0] Synchronous Channel Strobe
If the Strobe register location is written, each event channel will be inverted for one system clock cycle
(i.e., a single event is generated).
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 127
14.5.3 Asynchronous Channel n Generator Selection
Name:  ASYNCCH
Offset:  0x02 + n*0x01 [n=0..3]
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
ASYNCCH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – ASYNCCH[7:0] Asynchronous Channel Generator Selection
Table 14-2. Asynchronous Channel Generator Selection
Value ASYNCCH0 ASYNCCH1 ASYNCCH2 ASYNCCH3
0x00 OFF OFF OFF OFF
0x01 CCL_LUT0
0x02 CCL_LUT1
0x03 AC0_OUT
0x04 TCD0_CMPBCLR
0x05 TCD0_CMPASET
0x06 TCD0_CMPBSET
0x07 TCD0_PROGEV
0x08 RTC_OVF
0x09 RTC_CMP
0x0A PORTA_PIN0 PORTB_PIN0 - PIT_DIV8192
0x0B PORTA_PIN1 PORTB_PIN1 - PIT_DIV4096
0x0C PORTA_PIN2 PORTB_PIN2 - PIT_DIV2048
0x0D PORTA_PIN3 PORTB_PIN3 - PIT_DIV1024
0x0E PORTA_PIN4 PORTB_PIN4 - PIT_DIV512
0x0F PORTA_PIN5 PORTB_PIN5 - PIT_DIV256
0x10 PORTA_PIN6 PORTB_PIN6 AC1_OUT- PIT_DIV128
0x11 PORTA_PIN7 PORTB_PIN7 AC2_OUT- PIT_DIV64
0x12 UPDI AC1_OUT - AC1_OUT
0x13 AC1_OUT AC2_OUT - AC2_OUT
0x14 AC2_OUT - - -
Other - - - -
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 128
Note:  Not all pins of a port are actually available on devices with low pin counts. Check the Pinout
Diagram and/or the I/O Multiplexing table for details.
Related Links
4. Pinout
5. I/O Multiplexing and Considerations
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 129
14.5.4 Synchronous Channel n Generator Selection
Name:  SYNCCH
Offset:  0x0A + n*0x01 [n=0..1]
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
SYNCCH[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – SYNCCH[7:0] Synchronous Channel Generator Selection
Table 14-3. Synchronous Channel Generator Selection
Value SYNCCH0 SYNCCH1
0x00 OFF
0x01 TCB0
0x02 TCA0_OVF_LUNF
0x03 TCA0_HUNF
0x04 TCA0_CMP0
0x05 TCA0_CMP1
0x06 TCA0_CMP2
0x07 - -
0x08 - PORTB_PIN0
0x09 - PORTB_PIN1
0x0A - PORTB_PIN2
0x0B - PORTB_PIN3
0x0C - PORTB_PIN4
0x0D PORTA_PIN0 PORTB_PIN5
0x0E PORTA_PIN1 PORTB_PIN6
0x0F PORTA_PIN2 PORTB_PIN7
0x10 PORTA_PIN3 TCB1
0x11 PORTA_PIN4 -
0x12 PORTA_PIN5 -
0x13 PORTA_PIN6 -
0x14 PORTA_PIN7 -
0x15 TCB1 -
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 130
...........continued
Value SYNCCH0 SYNCCH1
Other - -
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 131
14.5.5 Asynchronous User Channel n Input Selection
Name:  ASYNCUSER
Offset:  0x12 + n*0x01 [n=0..12]
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
ASYNCUSER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – ASYNCUSER[7:0] Asynchronous User Channel Selection
Table 14-4. User Multiplexer Numbers
USERn User Multiplexer Description
n=0 TCB0 Timer/Counter B 0
n=1 ADC0 ADC 0
n=2 CCL_LUT0EV0 CCL LUT0 Event 0
n=3 CCL_LUT1EV0 CCL LUT1 Event 0
n=4 CCL_LUT0EV1 CCL LUT0 Event 1
n=5 CCL_LUT1EV1 CCL LUT1 Event 1
n=6 TCD0_EV0 Timer Counter D 0 Event 0
n=7 TCD0_EV1 Timer Counter D 0 Event 1
n=8 EVOUT0 Event OUT 0
n=9 EVOUT1 Event OUT 1
n=10 EVOUT2 Event OUT 2
n=11 TCB1 Timer/Counter B 1
n=12 ADC1 ADC 1
Value Description
0x0 OFF
0x1 SYNCCH0
0x2 SYNCCH1
0x3 ASYNCCH0
0x4 ASYNCCH1
0x5 ASYNCCH2
0x6 ASYNCCH3
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 132
14.5.6 Synchronous User Channel n Input Selection
Name:  SYNCUSER
Offset:  0x22 + n*0x01 [n=0..1]
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
SYNCUSER[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – SYNCUSER[7:0] Synchronous User Channel Selection
Table 14-5. User Multiplexer Numbers
USERn User Multiplexer Description
n=0 TCA0 Timer/Counter A
n=1 USART0 USART
Value Name
0x0 OFF
0x1 SYNCCH0
0x2 SYNCCH1
ATtiny1614
EVSYS - Event System
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 133
15. PORTMUX - Port Multiplexer
15.1 Overview
The Port Multiplexer (PORTMUX) can either enable or disable functionality of pins, or change between
default and alternative pin positions. This depends on the actual pin and property and is described in
detail in the PORTMUX register map.
For available pins and functionalities, refer to the Multiplexed Signals table.
Related Links
5. I/O Multiplexing and Considerations
ATtiny1614
PORTMUX - Port Multiplexer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 134
15.2 Register Summary - PORTMUX
Offset Name Bit Pos.
0x00 CTRLA 7:0 EVOUT1 EVOUT0
0x01 CTRLB 7:0 TWI0 USART0
0x02 CTRLC 7:0 TCA00
15.3 Register Description
ATtiny1614
PORTMUX - Port Multiplexer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 135
15.3.1 Control A
Name:  CTRLA
Offset:  0x00
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
EVOUT1 EVOUT0
Access R/W R/W
Reset 0 0
Bit 1 – EVOUT1 Event Output 1
Write this bit to '1' to enable event output 1.
Bit 0 – EVOUT0 Event Output 0
Write this bit to '1' to enable event output 0.
ATtiny1614
PORTMUX - Port Multiplexer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 136
15.3.2 Control B
Name:  CTRLB
Offset:  0x01
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
TWI0 USART0
Access R/W R/W
Reset 0 0
Bit 4 – TWI0 TWI 0 communication
Write this bit to '1' to select alternative communication pins for TWI 0.
Bit 0 – USART0 USART 0 communication
Write this bit to '1' to select alternative communication pins for USART 0.
ATtiny1614
PORTMUX - Port Multiplexer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 137
15.3.3 Control C
Name:  CTRLC
Offset:  0x02
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
TCA00
Access R/W
Reset 0
Bit 0 – TCA00 TCA0 Waveform output 0
Write this bit to '1' to select alternative output pin for TCA0 waveform output 0.
In Split mode, this bit controls output from low byte compare channel 0.
ATtiny1614
PORTMUX - Port Multiplexer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 138
16. PORT - I/O Pin Configuration
16.1 Features
General Purpose Input and Output Pins with Individual Configuration
Output Driver with Configurable Inverted I/O and Pull-up
Input with Interrupts and Events:
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Asynchronous Pin Change Sensing That Can Wake the Device From all Sleep Modes
Efficient and Safe Access to Port Pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Mapping of often-used PORT registers into bit-accessible I/O memory space (virtual ports)
16.2 Overview
The I/O pins of the device are controlled by instances of the Port Peripheral registers. This device has the
following instances of the I/O pin configuration (PORT): PORTA, PORTB.
Refer to the I/O multiplexing table to see which pins are controlled by what instance of port. The offsets of
the port instances and of the corresponding virtual port instances are listed in the Peripherals and
Architecture section.
Each of the port pins has a corresponding bit in the Data Direction (PORT.DIR) and Data Output Value
(PORT.OUT) registers to enable that pin as an output and to define the output state. For example, pin
PA3 is controlled by DIR[3] and OUT[3] of the PORTA instance.
The Data Input Value (PORT.IN) is set as the input value of a port pin with resynchronization to the main
clock. To reduce power consumption, these input synchronizers are not clocked if the Input Sense
Configuration bit field (ISC) in PORT.PINnCTRL is INPUT_DISABLE. The value of the pin can always be
read, whether the pin is configured as input or output.
The port supports synchronous and asynchronous input sensing with interrupts for selectable pin change
conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all
sleep modes, including the modes where no clocks are running.
All pin functions are configurable individually per pin. The pins have hardware read-modify-write (RMW)
functionality for a safe and correct change of drive value and/or pull resistor configuration. The direction
of one port pin can be changed without unintentionally changing the direction of any other pin.
The port pin configuration controls input and output selection of other device functions.
Related Links
5. I/O Multiplexing and Considerations
7. Peripherals and Architecture
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 139
||||||
16.2.1 Block Diagram
Figure 16-1. PORT Block Diagram
D
Q
R
D
Q
R
Synchronizer
DQ
R
DIRn
OUTn
INn
Pxn
DQ
R
Input Disable
Digital Input /
Asynchronous Event
Invert Enable
Pullup Enable
Input
Disable
Override
OUT Override
DIR
Override
Analog Input/Output
Synchronized
Input
Interrupt
Generator
Interrupt
16.2.2 Signal Description
Signal Type Description
Pxn I/O pin I/O pin n on PORTx
Related Links
5. I/O Multiplexing and Considerations
16.2.3 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 140
Table 16-1. PORT System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections No -
Interrupts Yes CPUINT
Events Yes EVSYS
Debug No -
Related Links
16.2.3.4 Events
16.2.3.1 Clocks
16.2.3.3 Interrupts
16.2.3.1 Clocks
This peripheral depends on the peripheral clock.
16.2.3.2 I/O Lines and Connections
Not applicable.
16.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
13. CPUINT - CPU Interrupt Controller
16.3.3 Interrupts
8.7.3 SREG
16.2.3.4 Events
The events of this peripheral are connected to the Event System.
Related Links
14. EVSYS - Event System
16.2.3.5 Debug Operation
This peripheral is unaffected by entering Debug mode.
16.3 Functional Description
16.3.1 Initialization
After Reset, all standard function device I/O pads are connected to the port with outputs tri-stated and
input buffers enabled, even if there is no clock running.
Power consumption can be reduced by disabling digital input buffers for all unused pins and for pins used
as analog inputs or outputs.
Specific pins, such as those used for connecting a debugger, may be configured differently, as required
by their special function.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 141
16.3.2 Operation
16.3.2.1 Basic Functions
Each I/O pin Pxn can be controlled by the registers in PORTx. Each pin group x has its own set of PORT
registers. The base address of the register set for pin n is at the byte address PORT + 0x10 + . The
index within that register set is n.
To use pin number n as an output only, write bit n of the PORTx.DIR register to '1'. This can be done by
writing bit n in the PORTx.DIRSET register to '1', which will avoid disturbing the configuration of other pins
in that group. The nth bit in the PORTx.OUT register must be written to the desired output value.
Similarly, writing a PORTx.OUTSET bit to '1' will set the corresponding bit in the PORTx.OUT register to
'1'. Writing a bit in PORTx.OUTCLR to '1' will clear that bit in PORTx.OUT to zero. Writing a bit in
PORTx.OUTTGL or PORTx.IN to '1' will toggle that bit in PORTx.OUT.
To use pin n as an input, bit n in the PORTx.DIR register must be written to '0' to disable the output driver.
This can be done by writing bit n in the PORTx.DIRCLR register to '1', which will avoid disturbing the
configuration of other pins in that group. The input value can be read from bit n in register PORTx.IN as
long as the ISC bit is not set to INPUT_DISABLE.
Writing a bit to '1' in PORTx.DIRTGL will toggle that bit in PORTx.DIR and toggle the direction of the
corresponding pin.
16.3.2.2 Virtual Ports
The Virtual PORT registers map the most frequently used regular PORT registers into the bit-accessible
I/O space. Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but
allows for memory-specific instructions, such as bit-manipulation instructions, which are not valid for the
extended I/O memory space where the regular PORT registers reside.
Table 16-2. Virtual Port Mapping
Regular PORT Register Mapped to Virtual PORT Register
PORT.DIR VPORT.DIR
PORT.OUT VPORT.OUT
PORT.IN VPORT.IN
PORT.INTFLAG VPORT.INTFLAG
Related Links
16.6 Register Summary - VPORT
5. I/O Multiplexing and Considerations
7. Peripherals and Architecture
16.3.2.3 Pin Configuration
The Pin n Configuration register (PORT.PINnCTRL) is used to configure inverted I/O, pullup, and input
sensing of a pin.
All input and output on the respective pin n can be inverted by writing a '1' to the Inverted I/O Enable bit
(INVEN) in PORT.PINnCTRL.
Toggling the INVEN bit causes an edge on the pin, which can be detected by all peripherals using this
pin, and is seen by interrupts or events if enabled.
Pullup of pin n is enabled by writing a '1' to the Pullup Enable bit (PULLUPEN) in PORT.PINnCTRL.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 142
Changes of the signal on a pin can trigger an interrupt. The exact conditions are defined by writing to the
Input/Sense bit field (ISC) in PORT.PINnCTRL.
When setting or changing interrupt settings, take these points into account:
If an INVEN bit is toggled in the same cycle as the interrupt setting, the edge caused by the inversion
toggling may not cause an interrupt request.
If an input is disabled while synchronizing an interrupt, that interrupt may be requested on re-
enabling the input, even if it is re-enabled with a different interrupt setting.
If the interrupt setting is changed while synchronizing an interrupt, that interrupt may not be
accepted.
Only a few pins support full asynchronous interrupt detection, see I/O Multiplexing and
Considerations. These limitations apply for waking the system from sleep:
Interrupt Type Fully Asynchronous Pins Other Pins
BOTHEDGES Will wake the system Will wake the system
RISING Will wake the system Will not wake the system
FALLING Will wake the system Will not wake the system
LEVEL Will wake the system Will wake the system
Related Links
5. I/O Multiplexing and Considerations
16.3.3 Interrupts
Table 16-3. Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 PORTx PORT A, B, C interrupt INTn in PORT.INTFLAGS is raised as configured by ISC bit in
PORT.PINnCTRL.
Each port pin n can be configured as an interrupt source. Each interrupt can be individually enabled or
disabled by writing to ISC in PORT.PINCTRL.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of
the peripheral (peripheral.INTFLAGS).
An interrupt request is generated when the corresponding interrupt is enabled and the interrupt flag is set.
The interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS
register for details on how to clear interrupt flags.
Asynchronous Sensing Pin Properties
Table 16-4. Behavior Comparison of Fully/Partly Asynchronous Sense Pin
Property Synchronous or Partly Asynchronous Sense
Support
Full Asynchronous Sense
Support
Minimum pulse-width
to trigger interrupt
Minimum one system clock cycle Less than a system clock
cycle
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 143
...........continued
Property Synchronous or Partly Asynchronous Sense
Support
Full Asynchronous Sense
Support
Waking the device
from sleep
From all interrupt sense configurations from sleep
modes with the main clock running. Only from
BOTHEDGES or LEVEL interrupt sense
configuration from sleep modes with the main
clock stopped.
From all interrupt sense
configurations from all sleep
modes
Interrupt 'dead time' No new interrupt for three cycles after the
previous
No limitation
Minimum wake-up
pulse length
Value on pad must be kept until the system clock
has restarted
No limitation
Related Links
8. AVR CPU
8.7.3 SREG
16.3.4 Events
All PORT pins are asynchronous event system generators. PORT has as many event generators as there
are PORT pins in the device. Each event system output from PORT is the value present on the
corresponding pin if the digital input driver is enabled. If a pin input driver is disabled, the corresponding
event system output is zero.
PORT has no event inputs.
16.3.5 Sleep Mode Operation
With the exception of interrupts and input synchronization, all pin configurations are independent of the
Sleep mode. Peripherals connected to the ports can be affected by Sleep modes, described in the
respective peripherals' documentation.
The port peripheral will always use the main clock. Input synchronization will halt when this clock stops.
16.3.6 Synchronization
Not applicable.
16.3.7 Configuration Change Protection
Not applicable.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 144
16.4 Register Summary - PORT
Offset Name Bit Pos.
0x00 DIR 7:0 DIR[7:0]
0x01 DIRSET 7:0 DIRSET[7:0]
0x02 DIRCLR 7:0 DIRCLR[7:0]
0x03 DIRTGL 7:0 DIRTGL[7:0]
0x04 OUT 7:0 OUT[7:0]
0x05 OUTSET 7:0 OUTSET[7:0]
0x06 OUTCLR 7:0 OUTCLR[7:0]
0x07 OUTTGL 7:0 OUTTGL[7:0]
0x08 IN 7:0 IN[7:0]
0x09 INTFLAGS 7:0 INT[7:0]
0x0A
...
0x0F
Reserved
0x10 PIN0CTRL 7:0 INVEN PULLUPEN ISC[2:0]
0x11 PIN1CTRL 7:0 INVEN PULLUPEN ISC[2:0]
0x12 PIN2CTRL 7:0 INVEN PULLUPEN ISC[2:0]
0x13 PIN3CTRL 7:0 INVEN PULLUPEN ISC[2:0]
0x14 PIN4CTRL 7:0 INVEN PULLUPEN ISC[2:0]
0x15 PIN5CTRL 7:0 INVEN PULLUPEN ISC[2:0]
0x16 PIN6CTRL 7:0 INVEN PULLUPEN ISC[2:0]
0x17 PIN7CTRL 7:0 INVEN PULLUPEN ISC[2:0]
16.5 Register Description - Ports
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 145
16.5.1 Data Direction
Name:  DIR
Offset:  0x00
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – DIR[7:0] Data Direction
This bit field selects the data direction for the individual pins n of the port.
Writing a '1' to PORT.DIR[n] configures and enables pin n as an output pin.
Writing a '0' to PORT.DIR[n] configures pin n as an input pin. It can be configured by writing to the ISC bit
in PORT.PINnCTRL.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 146
16.5.2 Data Direction Set
Name:  DIRSET
Offset:  0x01
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
DIRSET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – DIRSET[7:0] Data Direction Set
This bit field can be used instead of a read-modify-write to set individual pins as output.
Writing a '1' to DIRSET[n] will set the corresponding PORT.DIR[n] bit.
Reading this bit field will always return the value of PORT.DIR.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 147
16.5.3 Data Direction Clear
Name:  DIRCLR
Offset:  0x02
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
DIRCLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – DIRCLR[7:0] Data Direction Clear
This register can be used instead of a read-modify-write to configure individual pins as input.
Writing a '1' to DIRCLR[n] will clear the corresponding bit in PORT.DIR.
Reading this bit field will always return the value of PORT.DIR.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 148
16.5.4 Data Direction Toggle
Name:  DIRTGL
Offset:  0x03
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
DIRTGL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – DIRTGL[7:0] Data Direction Toggle
This bit field can be used instead of a read-modify-write to toggle the direction of individual pins.
Writing a '1' to DIRTGL[n] will toggle the corresponding bit in PORT.DIR.
Reading this bit field will always return the value of PORT.DIR.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 149
16.5.5 Output Value
Name:  OUT
Offset:  0x04
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
OUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – OUT[7:0] Output Value
This bit field defines the data output value for the individual pins n of the port.
If OUT[n] is written to '1', pin n is driven high.
If OUT[n] is written to '0', pin n is driven low.
In order to have any effect, the pin direction must be configured as output.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 150
16.5.6 Output Value Set
Name:  OUTSET
Offset:  0x05
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
OUTSET[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – OUTSET[7:0] Output Value Set
This bit field can be used instead of a read-modify-write to set the output value of individual pins to '1'.
Writing a '1' to OUTSET[n] will set the corresponding bit in PORT.OUT.
Reading this bit field will always return the value of PORT.OUT.
ATtiny1614
PORT - I/O Pin Configuration
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16.5.7 Output Value Clear
Name:  OUTCLR
Offset:  0x06
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
OUTCLR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – OUTCLR[7:0] Output Value Clear
This register can be used instead of a read-modify-write to clear the output value of individual pins to '0'.
Writing a '1' to OUTCLR[n] will clear the corresponding bit in PORT.OUT.
Reading this bit field will always return the value of PORT.OUT.
ATtiny1614
PORT - I/O Pin Configuration
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16.5.8 Output Value Toggle
Name:  OUTTGL
Offset:  0x07
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
OUTTGL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – OUTTGL[7:0] Output Value Toggle
This register can be used instead of a read-modify-write to toggle the output value of individual pins.
Writing a '1' to OUTTGL[n] will toggle the corresponding bit in PORT.OUT.
Reading this bit field will always return the value of PORT.OUT.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 153
16.5.9 Input Value
Name:  IN
Offset:  0x08
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
IN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – IN[7:0] Input Value
This register shows the value present on the pins if the digital input driver is enabled. IN[n] shows the
value of pin n of the port. The input is not sampled and cannot be read if the digital input buffers are
disabled.
Writing to a bit of PORT.IN will toggle the corresponding bit in PORT.OUT.
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PORT - I/O Pin Configuration
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16.5.10 Interrupt Flags
Name:  INTFLAGS
Offset:  0x09
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
INT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – INT[7:0] Interrupt Pin Flag
The INT Flag is set when a pin change/state matches the pin's input sense configuration.
Writing a '1' to a flag's bit location will clear the flag.
For enabling and executing the interrupt, refer to ISC bit description in PORT.PINnCTRL.
ATtiny1614
PORT - I/O Pin Configuration
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16.5.11 Pin n Control
Name:  PINCTRL
Offset:  0x10 + n*0x01 [n=0..7]
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
INVEN PULLUPEN ISC[2:0]
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 – INVEN Inverted I/O Enable
Value Description
0I/O on pin n not inverted
1I/O on pin n inverted
Bit 3 – PULLUPEN Pullup Enable
Value Description
0Pullup disabled for pin n
1Pullup enabled for pin n
Bits 2:0 – ISC[2:0] Input/Sense Configuration
These bits configure the input and sense configuration of pin n. The sense configuration determines how
a port interrupt can be triggered. If the input buffer is disabled, the input cannot be read in the IN register.
Value Name Description
0x0 INTDISABLE Interrupt disabled but input buffer enabled
0x1 BOTHEDGES Sense both edges
0x2 RISING Sense rising edge
0x3 FALLING Sense falling edge
0x4 INPUT_DISABLE Digital input buffer disabled
0x5 LEVEL Sense low level
other - Reserved
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PORT - I/O Pin Configuration
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16.6 Register Summary - VPORT
Offset Name Bit Pos.
0x00 DIR 7:0 DIR[7:0]
0x01 OUT 7:0 OUT[7:0]
0x02 IN 7:0 IN[7:0]
0x03 INTFLAGS 7:0 INT[7:0]
16.7 Register Description - Virtual Ports
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 157
16.7.1 Data Direction
Name:  DIR
Offset:  0x00
Reset:  0x00
Property:  -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for
memory-specific instructions, such as bit-manipulation instructions, which are not valid for the extended
I/O memory space where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
DIR[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – DIR[7:0] Data Direction
This bit field selects the data direction for the individual pins in the port.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 158
16.7.2 Output Value
Name:  OUT
Offset:  0x01
Reset:  0x00
Property:  -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for
memory-specific instructions, such as bit-manipulation instructions, which are not valid for the extended
I/O memory space where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
OUT[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – OUT[7:0] Output Value
This bit field selects the data output value for the individual pins in the port.
ATtiny1614
PORT - I/O Pin Configuration
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 159
16.7.3 Input Value
Name:  IN
Offset:  0x02
Reset:  0x00
Property:  -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for
memory-specific instructions, such as bit-manipulation instructions, which are not valid for the extended
I/O memory space where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
IN[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – IN[7:0] Input Value
This bit field holds the value present on the pins if the digital input buffer is enabled.
Writing to a bit of VPORT.IN will toggle the corresponding bit in VPORT.OUT.
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PORT - I/O Pin Configuration
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16.7.4 Interrupt Flag
Name:  INTFLAGS
Offset:  0x03
Reset:  0x00
Property:  -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for
memory-specific instructions, such as bit-manipulation instructions, which are not valid for the extended
I/O memory space where the regular PORT registers reside.
Bit 7 6 5 4 3 2 1 0
INT[7:0]
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 7:0 – INT[7:0] Interrupt Pin Flag
The INT flag is set when a pin change/state matches the pin's input sense configuration, and the pin is
configured as source for port interrupt.
Writing a '1' to this flag's bit location will clear the flag.
For enabling and executing the interrupt, refer to PORT_PINnCTRL.ISC.
ATtiny1614
PORT - I/O Pin Configuration
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17. BOD - Brown-out Detector
17.1 Features
Brown-out Detection monitors the power supply to avoid operation below a programmable level
There are three modes:
– Enabled
– Sampled
– Disabled
Separate selection of mode for Active and Sleep modes
Voltage Level Monitor (VLM) with Interrupt
Programmable VLM Level Relative to the BOD Level
17.2 Overview
The Brown-out Detector (BOD) peripheral monitors the power supply and compares the voltage with two
programmable threshold levels: The brown-out threshold level defines when to generate a Reset. A
Voltage Level Monitor (VLM) monitors the power supply and compares it to a threshold higher than the
BOD threshold. The VLM can then generate an interrupt request as an "early warning" when the supply
voltage is about to drop below the VLM threshold. The VLM threshold level is expressed as a percentage
above the BOD threshold level.
The BOD is mainly controlled by fuses. The mode used in Standby Sleep mode and Power-Down Sleep
mode can be altered in normal program execution. The VLM part of the BOD is controlled by I/O registers
as well.
When activated, the BOD can operate in Enabled mode, where the BOD is continuously active, and in
Sampled mode, where the BOD is activated briefly at a given period to check the supply voltage level.
ATtiny1614
BOD - Brown-out Detector
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17.2.1 Block Diagram
Figure 17-1. BOD Block Diagram
+
-
+
-
Bandgap
Bandgap
BOD Level
and
Calibration
VLM Interrupt Level
Brown-out
Detection
VDD
VLM Interrupt
Detection
17.2.2 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 17-1. BOD System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections No -
Interrupts Yes CPUINT
Events Yes EVSYS
Debug Yes UPDI
Related Links
17.2.2.1 Clocks
17.2.2.5 Debug Operation
17.2.2.3 Interrupts
17.2.2.4 Events
17.2.2.1 Clocks
The BOD uses the 32 KHz oscillator (OSCULP32K) as clock source for CLK_BOD.
ATtiny1614
BOD - Brown-out Detector
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17.2.2.2 I/O Lines and Connections
Not applicable.
17.2.2.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
13. CPUINT - CPU Interrupt Controller
8.7.3 SREG
17.3.2 Interrupts
17.2.2.4 Events
Not applicable.
17.2.2.5 Debug Operation
This peripheral is unaffected by entering Debug mode.
The VLM interrupt will not be executed if the CPU is halted in Debug mode.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar,
improper operation or data loss may result during halted debugging.
17.3 Functional Description
17.3.1 Initialization
The BOD settings are loaded from fuses during Reset. The BOD level and operating mode in Active and
Idle Sleep mode are set by fuses and cannot be changed by the CPU. The operating mode in Standby
and Power-Down Sleep mode is loaded from fuses and can be changed by software.
The Voltage Level Monitor function can be enabled by writing a '1' to the VLM Interrupt Enable bit
(VLMIE) in the Interrupt Control register (BOD.INTCTRL). The VLM interrupt is configured by writing the
VLM Configuration bits (VLMCFG) in BOD.INTCTRL. An interrupt is requested when the supply voltage
crosses the VLM threshold either from above, from below, or from any direction.
The VLM functionality will follow the BOD mode. If the BOD is turned OFF, the VLM will not be enabled,
even if the VLMIE is '1'. If the BOD is using Sampled mode, the VLM will also be sampled. When enabling
VLM interrupt, the interrupt flag will always be set if VLMCFG equals 0x2 and may be set if VLMCFG is
configured to 0x0 or 0x1.
The VLM threshold is defined by writing the VLM Level bits (VLMLVL) in the Control A register
(BOD.VLMCTRLA).
If the BOD/VLM is enabled in Sampled mode, only VLMCFG=0x1 (crossing threshold from above) in
BOD.INTCTRL will trigger an interrupt.
17.3.2 Interrupts
Table 17-2. Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 VLM Voltage Level Monitor Supply voltage crossing the VLM threshold as configured by
VLMCFG in BOD.INTCTRL
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BOD - Brown-out Detector
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When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of
the peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's
Interrupt Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt
flag is set. The interrupt request remains active until the interrupt flag is cleared. See the peripheral's
INTFLAGS register for details on how to clear interrupt flags.
Related Links
8. AVR CPU
8.7.3 SREG
17.3.3 Sleep Mode Operation
There are two separate fuses defining the BOD configuration in different sleep modes; One fuse defines
the mode used in Active mode and Idle Sleep mode (ACTIVE in FUSE.BODCFG) and is written to the
ACTIVE bits in the Control A register (BOD.CTRLA). The second fuse (SLEEP in FUSE.BODCFG)
selects the mode used in Standby Sleep mode and Power-Down Sleep mode and is loaded into the
SLEEP bits in the Control A register (BOD.CTRLA).
The operating mode in Active mode and Idle Sleep mode (i.e., ACTIVE in BOD.CTRLA) cannot be
altered by software. The operating mode in Standby Sleep mode and Power-Down Sleep mode can be
altered by writing to the SLEEP bits in the Control A register (BOD.CTRLA).
When the device is going into Standby Sleep mode or Power-Down Sleep mode, the BOD will change
operation mode as defined by SLEEP in BOD.CTRLA. When the device is waking up from Standby or
Power-Down Sleep mode, the BOD will operate in the mode defined by the ACTIVE bit field in
BOD.CTRLA.
17.3.4 Synchronization
Not applicable.
17.3.5 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves
the protected register unchanged.
The following registers are under CCP:
Table 17-3. Registers Under Configuration Change Protection
Register Key
SLEEP in BOD.CTRLA IOREG
Related Links
8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
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BOD - Brown-out Detector
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17.4 Register Summary - BOD
Offset Name Bit Pos.
0x00 CTRLA 7:0 SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
0x01 CTRLB 7:0 LVL[2:0]
0x02
...
0x07
Reserved
0x08 VLMCTRLA 7:0 VLMLVL[1:0]
0x09 INTCTRL 7:0 VLMCFG[1:0] VLMIE
0x0A INTFLAGS 7:0 VLMIF
0x0B STATUS 7:0 VLMS
17.5 Register Description
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BOD - Brown-out Detector
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17.5.1 Control A
Name:  CTRLA
Offset:  0x00
Reset:  Loaded from fuse
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
SAMPFREQ ACTIVE[1:0] SLEEP[1:0]
Access R R R R/W R/W
Reset x x x x x
Bit 4 – SAMPFREQ Sample Frequency
This bit selects the BOD sample frequency.
The Reset value is loaded from the SAMPFREQ bit in FUSE.BODCFG. This bit is under Configuration
Change Protection (CCP).
Value Description
0x0 Sample frequency is 1 kHz
0x1 Sample frequency is 125 Hz
Bits 3:2 – ACTIVE[1:0] Active
These bits select the BOD operation mode when the device is in Active or Idle mode.
The Reset value is loaded from the ACTIVE bits in FUSE.BODCFG.
Value Description
0x0 Disabled
0x1 Enabled
0x2 Sampled
0x3 Enabled with wake-up halted until BOD is ready
Bits 1:0 – SLEEP[1:0] Sleep
These bits select the BOD operation mode when the device is in Standby or Power-Down Sleep mode.
The Reset value is loaded from the SLEEP bits in FUSE.BODCFG.
These bits are under Configuration Change Protection (CCP).
Value Description
0x0 Disabled
0x1 Enabled
0x2 Sampled
0x3 Reserved
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BOD - Brown-out Detector
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17.5.2 Control B
Name:  CTRLB
Offset:  0x01
Reset:  Loaded from fuse
Property:  -
Bit 7 6 5 4 3 2 1 0
LVL[2:0]
Access R R R R R R R R
Reset 0 0 0 0 0 x x x
Bits 2:0 – LVL[2:0] BOD Level
These bits select the BOD threshold level.
The Reset value is loaded from the BOD Level bits (LVL) in the BOD Configuration Fuse
(FUSE.BODCFG).
Value Name Description
0x0 BODLEVEL0 1.8V
0x2 BODLEVEL2 2.6V
0x7 BODLEVEL7 4.2V
Note: 
Values in the description are typical values.
Refer to the BOD and POR Characteristics in Electrical Characteristics for maximum and minimum
values.
ATtiny1614
BOD - Brown-out Detector
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17.5.3 VLM Control A
Name:  VLMCTRLA
Offset:  0x08
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
VLMLVL[1:0]
Access R/W R/W
Reset 0 0
Bits 1:0 – VLMLVL[1:0] VLM Level
These bits select the VLM threshold relative to the BOD threshold (LVL in BOD.CTRLB).
Value Description
0x0 VLM threshold 5% above BOD threshold
0x1 VLM threshold 15% above BOD threshold
0x2 VLM threshold 25% above BOD threshold
other Reserved
ATtiny1614
BOD - Brown-out Detector
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17.5.4 Interrupt Control
Name:  INTCTRL
Offset:  0x09
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
VLMCFG[1:0] VLMIE
Access R/W R/W R/W
Reset 0 0 0
Bits 2:1 – VLMCFG[1:0] VLM Configuration
These bits select which incidents will trigger a VLM interrupt.
Value Description
0x0 Voltage crosses VLM threshold from above
0x1 Voltage crosses VLM threshold from below
0x2 Either direction is triggering an interrupt request
Other Reserved
Bit 0 – VLMIE VLM Interrupt Enable
Writing a '1' to this bit enables the VLM interrupt.
ATtiny1614
BOD - Brown-out Detector
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17.5.5 VLM Interrupt Flags
Name:  INTFLAGS
Offset:  0x0A
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
VLMIF
Access R/W
Reset 0
Bit 0 – VLMIF VLM Interrupt Flag
This flag is set when a trigger from the VLM is given, as configured by the VLMCFG bit in the
BOD.INTCTRL register. The flag is only updated when the BOD is enabled.
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BOD - Brown-out Detector
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17.5.6 VLM Status
Name:  STATUS
Offset:  0x0B
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
VLMS
Access R
Reset 0
Bit 0 – VLMS VLM Status
This bit is only valid when the BOD is enabled.
Value Description
0The voltage is above the VLM threshold level
1The voltage is below the VLM threshold level
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BOD - Brown-out Detector
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18. VREF - Voltage Reference
18.1 Features
Programmable Voltage Reference Sources:
One for each ADC peripheral
One for each AC and DAC peripheral
Each Reference Source Supports Five Different Voltages:
– 0.55V
– 1.1V
– 1.5V
– 2.5V
– 4.3V
18.2 Overview
The Voltage Reference (VREF) peripheral provides control registers for the voltage reference sources
used by several peripherals. The user can select the reference voltages for the ADC0 by writing to the
ADC0 Reference Select bit field (ADC0REFSEL) in the Control A register (VREF.CTRLA), and for both
AC0 and DAC0 by writing to the DAC0 and AC0 Reference Select bit field DAC0REFSEL in
VREF.CTRLA.
A voltage reference source is enabled automatically when requested by a peripheral. The user can
enable the reference voltage sources (and thus, override the automatic disabling of unused sources) by
writing to the respective Force Enable bit (ADC0REFEN, DAC0REFEN) in the Control B register
(VREF.CTRLB). This may be desirable to decrease start-up time, at the cost of increased power
consumption.
18.2.1 Block Diagram
Figure 18-1. VREF Block Diagram
Reference select
Bandgap Reference
Generator
Internal
Reference
BUF
1.1V
1.5V
2.5V
4.3V
0.55V
Reference enable
Reference request
Bandgap
enable
18.3 Functional Description
ATtiny1614
VREF - Voltage Reference
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 173
18.3.1 Initialization
The default configuration will enable the respective source when the ADC0, AC0, or DAC0 is requesting a
reference voltage. The default reference voltages are 0.55V but can be configured by writing to the
respective Reference Select bit field (ADC0REFSEL, DAC0REFSEL) in the Control A register
(VREF.CTRLA).
ATtiny1614
VREF - Voltage Reference
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 174
18.4 Register Summary - VREF
Offset Name Bit Pos.
0x00 CTRLA 7:0 ADC0REFSEL[2:0] DAC0REFSEL[2:0]
0x01 CTRLB 7:0 DAC2REFEN ADC1REFEN DAC1REFEN ADC0REFEN DAC0REFEN
0x02 CTRLC 7:0 ADC1REFSEL[2:0] DAC1REFSEL[2:0]
0x03 CTRLD 7:0 DAC2REFSEL[2:0]
18.5 Register Description
ATtiny1614
VREF - Voltage Reference
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 175
18.5.1 Control A
Name:  CTRLA
Offset:  0x00
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
ADC0REFSEL[2:0] DAC0REFSEL[2:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 6:4 – ADC0REFSEL[2:0] ADC0 Reference Select
These bits select the reference voltage for the ADC0.
Value Description
0x0 0.55V
0x1 1.1V
0x2 2.5V
0x3 4.3V
0x4 1.5V
other Reserved
Bits 2:0 – DAC0REFSEL[2:0] DAC0 and AC0 Reference Select
These bits select the reference voltage for the DAC0 and AC0.
Value Description
0x0 0.55V
0x1 1.1V
0x2 2.5V
0x3 4.3V
0x4 1.5V
other Reserved
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VREF - Voltage Reference
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18.5.2 Control B
Name:  CTRLB
Offset:  0x01
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
DAC2REFEN ADC1REFEN DAC1REFEN ADC0REFEN DAC0REFEN
Access R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 5 – DAC2REFEN DAC2 and AC2 Reference Force Enable
Writing a '1' to this bit forces the voltage reference for the DAC2 and AC2 to be running, even if it is not
requested.
Writing a '0' to this bit allows to automatic enable/disable the reference source when not requested.
Bit 4 – ADC1REFEN ADC1 Reference Force Enable
Writing a '1' to this bit forces the voltage reference for the ADC1 to be running, even if it is not requested.
Writing a '0' to this bit allows to automatic enable/disable the reference source when not requested.
Note:  Do not force the internal reference enabled (ADCnREFEN=1 in VREF.CTRLB) when the ADC is
using the external reference (REFSEL bits in ADC.CTRLC).
Bit 3 – DAC1REFEN DAC1 and AC1 Reference Force Enable
Writing a '1' to this bit forces the voltage reference for the DAC1 and AC1 to be running, even if it is not
requested.
Writing a '0' to this bit allows to automatic enable/disable the reference source when not requested.
Bit 1 – ADC0REFEN ADC0 Reference Force Enable
Writing a '1' to this bit forces the voltage reference for the ADC0 to be running, even if it is not requested.
Writing a '0' to this bit allows automatic enable/disable of the reference source by the peripheral.
Note:  Do not force the internal reference enabled (ADCnREFEN=1 in VREF.CTRLB) when the ADC is
using the external reference (REFSEL bits in ADC.CTRLC).
Bit 0 – DAC0REFEN DAC0 and AC0 Reference Force Enable
Writing a '1' to this bit forces the voltage reference for the DAC0 and AC0 to be running, even if it is not
requested.
Writing a '0' to this bit allows automatic enable/disable of the reference source by the peripheral.
ATtiny1614
VREF - Voltage Reference
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18.5.3 Control C
Name:  CTRLC
Offset:  0x02
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
ADC1REFSEL[2:0] DAC1REFSEL[2:0]
Access R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bits 6:4 – ADC1REFSEL[2:0] ADC1 Reference Select
These bits select the reference voltage for the ADC1.
Value Description
0x0 0.55V
0x1 1.1V
0x2 2.5V
0x3 4.3V
0x4 1.5V
other Reserved
Bits 2:0 – DAC1REFSEL[2:0] DAC1 and AC1 Reference Select
These bits select reference voltage for the DAC1 and AC1.
Value Description
0x0 0.55V
0x1 1.1V
0x2 2.5V
0x3 4.3V
0x4 1.5V
other Reserved
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VREF - Voltage Reference
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18.5.4 Control D
Name:  CTRLD
Offset:  0x03
Reset:  0x00
Property:  -
Bit 7 6 5 4 3 2 1 0
DAC2REFSEL[2:0]
Access R/W R/W R/W
Reset 0 0 0
Bits 2:0 – DAC2REFSEL[2:0] DAC2 and AC2 Reference Select
These bits select reference voltage for the DAC2 and AC2.
Value Description
0x0 0.55V
0x1 1.1V
0x2 2.5V
0x3 4.3V
0x4 1.5V
other Reserved
ATtiny1614
VREF - Voltage Reference
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 179
19. WDT - Watchdog Timer
19.1 Features
Issues a System Reset if the Watchdog Timer is not Cleared Before its Time-out Period
Operating Asynchronously from System Clock Using an Independent Oscillator
Using the 1 KHz Output of the 32 KHz Ultra Low-Power Oscillator (OSCULP32K)
11 Selectable Time-out Periods, from 8 ms to 8s
Two Operation modes:
Normal mode
Window mode
Configuration Lock to Prevent Unwanted Changes
Closed Period Timer Activation After First WDT Instruction for Easy Setup
19.2 Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It allows the
system to recover from situations such as runaway or deadlocked code, by issuing a Reset. When
enabled, the WDT is a constantly running timer with a predefined time-out period. If the WDT is not reset
within the time-out period, it will issue a system Reset. The WDT is reset by executing the WDR (Watchdog
Timer Reset) instruction in software.
The WDT has two modes of operation; Normal mode and Window mode. The settings in the Control A
register (WDT.CTRLA) determine the mode of operation.
A Window mode defines a time slot or "window" inside the time-out period during which the WDT must be
reset. If the WDT is reset outside this window, either too early or too late, a system Reset will be issued.
Compared to the Normal mode, the Window mode can catch situations where a code error causes
constant WDR execution.
When enabled, the WDT will run in Active mode and all Sleep modes. It is asynchronous (i.e., running
from a CPU independent clock source). For this reason, it will continue to operate and be able to issue a
system Reset even if the main clock fails.
The CCP mechanism ensures that the WDT settings cannot be changed by accident. For increased
safety, a configuration for locking the WDT settings is available.
Related Links
8.5.7 Configuration Change Protection (CCP)
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 180
% 39 .i.
19.2.1 Block Diagram
Figure 19-1. WDT Block Diagram
COUNT
=
=
"Inside closed window"
"Enable
open window
and clear count"
CLK_WDT
WDR
(instruction)
System
Reset
CTRLA
CTRLA
WINDOW
PERIOD
19.2.2 Signal Description
Not applicable.
19.2.3 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 19-1. WDT System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections No -
Interrupts No -
Events No -
Debug Yes UPDI
Related Links
19.2.3.1 Clocks
19.2.3.5 Debug Operation
19.2.3.1 Clocks
A 1 KHz Oscillator Clock (CLK_WDT_OSC) is sourced from the internal Ultra Low-Power Oscillator,
OSCULP32K. Due to the ultra low-power design, the oscillator is not very accurate, and so the exact
time-out period may vary from device to device. This variation must be kept in mind when designing
software that uses the WDT to ensure that the time-out periods used are valid for all devices.
The Counter Clock CLK_WDT_OSC is asynchronous to the system clock. Due to this asynchronicity,
writing to the WDT Control register will require synchronization between the clock domains.
19.2.3.2 I/O Lines and Connections
Not applicable.
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 181
19.2.3.3 Interrupts
Not applicable.
19.2.3.4 Events
Not applicable.
19.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging
mode will halt normal operation of the peripheral.
When halting the CPU in Debug mode, the WDT counter is reset.
When starting the CPU again and the WDT is operating in Window mode, the first closed window time-
out period will be disabled, and a Normal mode time-out period is executed.
Related Links
19.3.2.2 Window Mode
19.3 Functional Description
19.3.1 Initialization
The WDT is enabled when a non-zero value is written to the Period bits (PERIOD) in the Control A
register (WDT.CTRLA).
Optional: Write a non-zero value to the Window bits (WINDOW) in WDT.CTRLA to enable Window
mode operation.
All bits in the Control A register and the Lock bit (LOCK) in the STATUS register (WDT.STATUS) are
write-protected by the Configuration Change Protection mechanism.
The Reset value of WDT.CTRLA is defined by a fuse (FUSE.WDTCFG), so the WDT can be enabled at
boot time. If this is the case, the LOCK bit in WDT.STATUS is set at boot time.
Related Links
19.4 Register Summary - WDT
19.3.2 Operation
19.3.2.1 Normal Mode
In Normal mode operation, a single time-out period is set for the WDT. If the WDT is not reset from
software using the WDR any time before the time-out occurs, the WDT will issue a system Reset.
A new WDT time-out period will be started each time the WDT is reset by WDR.
There are 11 possible WDT time-out periods (TOWDT), selectable from 8 ms to 8s by writing to the Period
bit field (PERIOD) in the Control A register (WDT.CTRLA).
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 182
WDT Count A \
Figure 19-2. Normal Mode Operation
t [ms]
WDT Count
5 10 15 20 25 30 35
Timely WDT Reset (WDR)
TOWDT
WDT Timeout
System Reset
TO WDT = 16 ms
Here:
Normal mode is enabled as long as the WINDOW bit field in the Control A register (WDT.CTRLA) is 0x0.
Related Links
19.4 Register Summary - WDT
19.3.2.2 Window Mode
In Window mode operation, the WDT uses two different time-out periods; a closed Window Time-out
period (TOWDTW) and the normal time-out period (TOWDT):
The closed window time-out period defines a duration from 8 ms to 8s where the WDT cannot be
reset. If the WDT is reset during this period, the WDT will issue a system Reset.
The normal WDT time-out period, which is also 8 ms to 8s, defines the duration of the open period
during which the WDT can (and should) be reset. The open period will always follow the closed
period, so the total duration of the time-out period is the sum of the closed window and the open
window time-out periods.
When enabling Window mode or when going out of Debug mode, the first closed period is activated after
the first WDR instruction.
If a second WDR is issued while a previous WDR is being synchronized, the second one will be ignored.
Figure 19-3. Window Mode Operation
t [ms]
WDT Count
5 10 15 20 25 30 35
Timely WDT Reset (WDR)
Closed
TOWDTW
Open
TOWDT
System Reset
WDR too early:
TOWDTW =TOWDT = 8 ms
Here:
The Window mode is enabled by writing a non-zero value to the WINDOW bit field in the Control A
register (WDT.CTRLA), and disabled by writing WINDOW=0x0.
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 183
19.3.2.3 Configuration Protection and Lock
The WDT provides two security mechanisms to avoid unintentional changes to the WDT settings:
The first mechanism is the Configuration Change Protection mechanism, employing a timed write
procedure for changing the WDT control registers.
The second mechanism locks the configuration by writing a '1' to the LOCK bit in the STATUS register
(WDT.STATUS). When this bit is '1', the Control A register (WDT.CTRLA) cannot be changed.
Consequently, the WDT cannot be disabled from software.
LOCK in WDT.STATUS can only be written to '1'. It can only be cleared in Debug mode.
If the WDT configuration is loaded from fuses, LOCK is automatically set in WDT.STATUS.
Related Links
8.5.7 Configuration Change Protection (CCP)
19.3.3 Events
Not applicable.
19.3.4 Interrupts
Not applicable.
19.3.5 Sleep Mode Operation
The WDT will continue to operate in any sleep mode where the source clock is active.
19.3.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A
register (WDT.CTRLA) is synchronized when written. The Synchronization Busy flag (SYNCBUSY) in the
STATUS register (WDT.STATUS) indicates if there is an ongoing synchronization.
Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.
The following registers are synchronized when written:
PERIOD bits in Control A register (WDT.CTRLA)
Window Period bits (WINDOW) in WDT.CTRLA
The WDR instruction will need two to three cycles of the WDT clock in order to be synchronized. Issuing a
new WDR instruction while a WDR instruction is being synchronized will be ignored.
19.3.7 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
Attempting to write to a protected register without following the appropriate CCP unlock sequence leaves
the protected register unchanged.
The following registers are under CCP:
Table 19-2. WDT - Registers Under Configuration Change Protection
Register Key
WDT.CTRLA IOREG
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 184
...........continued
Register Key
LOCK bit in WDT.STATUS IOREG
List of bits/registers protected by CCP:
Period bits in Control A register (CTRLA.PERIOD)
Window Period bits in Control A register (CTRLA.WINDOW)
LOCK bit in STATUS register (STATUS.LOCK)
Related Links
8.5.7 Configuration Change Protection (CCP)
8.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
8.7.1 CCP
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 185
19.4 Register Summary - WDT
Offset Name Bit Pos.
0x00 CTRLA 7:0 WINDOW[3:0] PERIOD[3:0]
0x01 STATUS 7:0 LOCK SYNCBUSY
19.5 Register Description
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 186
19.5.1 Control A
Name:  CTRLA
Offset:  0x00
Reset:  From FUSE.WDTCFG
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
WINDOW[3:0] PERIOD[3:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset x x x x x x x x
Bits 7:4 – WINDOW[3:0] Window
Writing a non-zero value to these bits enables the Window mode, and selects the duration of the closed
period accordingly.
The bits are optionally lock-protected:
If LOCK bit in WDT.STATUS is '1', all bits are change-protected (Access = R)
If LOCK bit in WDT.STATUS is '0', all bits can be changed (Access = R/W)
Value Name Description
0x0 OFF -
0x1 8CLK 0.008s
0x2 16CLK 0.016s
0x3 32CLK 0.032s
0x4 64CLK 0.064s
0x5 128CLK 0.128s
0x6 256CLK 0.256s
0x7 512CLK 0.512s
0x8 1KCLK 1.024s
0x9 2KCLK 2.048s
0xA 4KCLK 4.096s
0xB 8KCLK 8.192s
other - Reserved
Bits 3:0 – PERIOD[3:0] Period
Writing a non-zero value to this bit enables the WDT, and selects the time-out period in Normal mode
accordingly. In Window mode, these bits select the duration of the open window.
The bits are optionally lock-protected:
If LOCK in WDT.STATUS is '1', all bits are change-protected (Access = R)
If LOCK in WDT.STATUS is '0', all bits can be changed (Access = R/W)
Value Name Description
0x0 OFF -
0x1 8CLK 0.008s
0x2 16CLK 0.016s
0x3 32CLK 0.032s
0x4 64CLK 0.064s
0x5 128CLK 0.128s
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 187
Value Name Description
0x6 256CLK 0.256s
0x7 512CLK 0.512s
0x8 1KCLK 1.0s
0x9 2KCLK 2.0s
0xA 4KCLK 4.1s
0xB 8KCLK 8.2s
other - Reserved
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 188
19.5.2 Status
Name:  STATUS
Offset:  0x01
Reset:  0x00
Property:  Configuration Change Protection
Bit 7 6 5 4 3 2 1 0
LOCK SYNCBUSY
Access R/W R
Reset 0 0
Bit 7 – LOCK Lock
Writing this bit to '1' write-protects the WDT.CTRLA register.
It is only possible to write this bit to '1'. This bit can be cleared in Debug mode only.
If the PERIOD bits in WDT.CTRLA are different from zero after boot code, the lock will automatically be
set.
This bit is under CCP.
Bit 0 – SYNCBUSY Synchronization Busy
This bit is set after writing to the WDT.CTRLA register while the data is being synchronized from the
system clock domain to the WDT clock domain.
This bit is cleared by the system after the synchronization is finished.
This bit is not under CCP.
Related Links
19.3.6 Synchronization
19.3.7 Configuration Change Protection
ATtiny1614
WDT - Watchdog Timer
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 189
20. TCA - 16-bit Timer/Counter Type A
20.1 Features
16-Bit Timer/Counter
Three Compare Channels
Double-Buffered Timer Period Setting
Double-Buffered Compare Channels
Waveform Generation:
Frequency generation
Single-slope PWM (pulse-width modulation)
Dual-slope PWM
Count on Event
Timer Overflow Interrupts/Events
One Compare Match per Compare Channel
Two 8-Bit Timer/Counters in Split Mode
20.2 Overview
The flexible 16-bit PWM Timer/Counter type A (TCA) provides accurate program execution timing,
frequency and waveform generation, and command execution.
A TCA consists of a base counter and a set of compare channels. The base counter can be used to count
clock cycles or events or let events control how it counts clock cycles. It has direction control and period
setting that can be used for timing. The compare channels can be used together with the base counter to
do compare match control, frequency generation, and pulse-width waveform modulation.
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at
each timer/counter clock or event input.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the
event system. The event system can also be used for direction control or to synchronize operations.
By default, the TCA is a 16-bit timer/counter. The timer/counter has a Split mode feature that splits it into
two 8-bit timer/counters with three compare channels each. In Split mode, each compare channel only
supports single-slope PWM waveform generation.
A block diagram of the 16-bit timer/counter with closely related peripheral modules (in grey) is shown in
the figure below.
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 190
mkm On. >>>
Figure 20-1. 16-bit Timer/Counter and Closely Related Peripherals
Counter
Control Logic
Timer Period
Timer/Counter
Base Counter Prescaler
Event
System
CLK_PER
PORTS
Comparator
Buffer
Compare Channel 2
Compare Channel 1
Compare Channel 0
Waveform
Generation
This device provides one instance of the TCA peripheral, TCA0.
20.2.1 Block Diagram
The figure below shows a detailed block diagram of the timer/counter.
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 191
Figure 20-2. Timer/Counter Block Diagram
Base Counter
Compare
(Unit x = {A,B,C})
Counter
=
CMPn
CMPnBUF
Waveform
Generation
BV
=
PERB
PER
CNT
BV
= 0
"count"
"clear"
"direction"
"load" Control Logi c
EVCTRL
CTRLA
OVF/UNF
(INT Req.)
TOP
"match" CMPn
(INT Req.)
Control Logi c
Clock Select
"ev"
UPDATE
BOTTOM
WOn Out
Event
Select
The counter register (TCAn.CNT), period registers with buffer (TCAn.PER and TCAn.PERBUF), and
compare registers with buffers (TCAn.CMPx and TCAn.CMPBUFx) are 16-bit registers. All buffer
registers have a buffer valid (BV) flag that indicates when the buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value
to determine whether the counter has reached TOP or BOTTOM.
The counter value is also compared to the TCAn.CMPx registers. These comparisons can be used to
generate interrupt requests. The Waveform Generator modes use these comparisons to set the waveform
period or pulse-width.
A prescaled peripheral clock and events from the event system can be used to control the counter.
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 192
CLK_PER 4» Prescaler Event System \ event
Figure 20-3. Timer/Counter Clock Logic
CKSEL
CNTEI
CLK_PER
event
Event SystemPrescaler
CNT
(Encoding)
EVACT
CLK_TCA
20.2.2 Signal Description
Signal Description(1) Type
WO[2:0] Digital output Waveform output
WO[5:3] Digital output Waveform output - Split mode only
Note: 
1. Refer to the I/O Multiplexing and Considerations section to see the availability of WOn on pins.
20.2.3 System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 20-1. TCA System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
I/O Lines and Connections Yes WO[5:0]
Interrupts Yes CPUINT
Events Yes EVSYS
Debug Yes UPDI
Related Links
20.2.3.1 Clocks
20.2.3.5 Debug Operation
20.2.3.3 Interrupts
20.2.3.4 Events
20.2.3.1 Clocks
This peripheral uses the system clock CLK_PER and has its own prescaler.
Related Links
10. CLKCTRL - Clock Controller
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 193
20.2.3.2 I/O Lines and Connections
Using the I/O lines of the peripheral requires configuration of the I/O pins.
Related Links
5. I/O Multiplexing and Considerations
16. PORT - I/O Pin Configuration
20.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
13. CPUINT - CPU Interrupt Controller
8.7.3 SREG
20.3.5 Interrupts
20.2.3.4 Events
The events of this peripheral are connected to the Event System.
Related Links
14. EVSYS - Event System
20.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging
mode will halt normal operation of the peripheral.
This peripheral can be forced to operate with halted CPU by writing a '1' to the Debug Run bit (DBGRUN)
in the Debug Control register of the peripheral (peripheral.DBGCTRL).
Related Links
33. UPDI - Unified Program and Debug Interface
20.3 Functional Description
20.3.1 Definitions
The following definitions are used throughout the documentation:
Table 20-2. Timer/Counter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes zero.
MAX The counter reaches MAXimum when it becomes all ones.
TOP The counter reaches TOP when it becomes equal to the highest value in the count
sequence.
UPDATE The update condition is met when the timer/counter reaches BOTTOM or TOP, depending on
the Waveform Generator mode.
CNT Counter register value.
CMP Compare register value.
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 194
In general, the term timer is used when the timer/counter is counting periodic clock ticks. The term
counter is used when the input signal has sporadic or irregular ticks.
20.3.2 Initialization
To start using the timer/counter in a basic mode, follow these steps:
Write a TOP value to the Period register (TCAn.PER)
Enable the peripheral by writing a '1' to the ENABLE bit in the Control A register (TCAn.CTRLA).
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bit
field (CLKSEL) in TCAn.CTRLA.
Optional: By writing a '1' to the Enable Count on Event Input bit (CNTEI) in the Event Control register
(TCAn.EVCTRL), event inputs are counted instead of clock ticks.
The counter value can be read from the Counter bit field (CNT) in the Counter register (TCAn.CNT).
20.3.3 Operation
20.3.3.1 Normal Operation
In normal operation, the counter is counting clock ticks in the direction selected by the Direction bit (DIR)
in the Control E register (TCAn.CTRLE), until it reaches TOP or BOTTOM. The clock ticks are from the
peripheral clock CLK_PER, optionally prescaled, depending on the Clock Select bit field (CLKSEL) in the
Control A register (TCAn.CTRLA).
When up-counting and TOP are reached, the counter will wrap to zero at the next clock tick. When down-
counting, the counter is reloaded with the Period register value (TCAn.PER) when BOTTOM is reached.
Figure 20-4. Normal Operation
CNT written
"update"
CNT
DIR
MAX
TOP
BOTTOM
It is possible to change the counter value in the Counter register (TCAn.CNT) when the counter is
running. The write access to TCAn.CNT has higher priority than count, clear, or reload, and will be
immediate. The direction of the counter can also be changed during normal operation by writing to DIR in
TCAn.CTRLE.
20.3.3.2 Double Buffering
The Period register value (TCAn.PER) and the Compare n register values (TCAn.CMPn) are all double-
buffered (TCAn.PERBUF and TCAn.CMPnBUF).
Each buffer register has a Buffer Valid flag (PERBV, CMPnBV) in the Control F register (TCAn.CTRLF),
which indicates that the buffer register contains a valid, i.e. new, value that can be copied into the
corresponding Period or Compare register. When the Period register and Compare n registers are used
for a compare operation, the BV flag is set when data is written to the buffer register and cleared on an
UPDATE condition. This is shown for a Compare register (CMPn) below.
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 195
"wri‘e enable" "data write“ than current CNT. man currem CNT
Figure 20-5. Period and Compare Double Buffering
UPDATE
"write enable" "data write"
CNT
"match"
EN
EN
CMPnBUF
CMPn
BV
=
Both the TCAn.CMPn and TCAn.CMPnBUF registers are available as I/O registers. This allows
initialization and bypassing of the buffer register and the double buffering function.
20.3.3.3 Changing the Period
The Counter period is changed by writing a new TOP value to the Period register (TCAn.PER).
No Buffering: If double buffering is not used, any period update is immediate.
Figure 20-6. Changing the Period Without Buffering
CNT
MAX
BOTTOM
Counter wrap-around
"update"
"write"
New TOP written to
PER that is higher
than current CNT.
New TOP written to
PER that is lower
than current CNT.
A counter wrap-around can occur in any mode of operation when up-counting without buffering. This is
due to the fact that the TCAn.CNT and TCAn.PER registers are continuously compared: if a new TOP
value is written to TCAn.PER that is lower than the current TCAn.CNT, the counter will wrap first, before a
compare match happens.
Figure 20-7. Unbuffered Dual-Slope Operation
Counter wrap-around
"update"
"write"
MAX
BOTTOM
CNT
New TOP written to
PER that is higher
than current CNT.
New TOP written to
PER that is lower
than current CNT.
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 196
man currenl CNT. than current CNT.
With Buffering: When double buffering is used, the buffer can be written at any time and still maintain
correct operation. The TCAn.PER is always updated on the UPDATE condition, as shown for dual-slope
operation in the figure below. This prevents wrap-around and the generation of odd waveforms.
Figure 20-8. Changing the Period Using Buffering
CNT
BOTTOM
MAX
"update"
"write"
New Period written to
PERB that is higher
than current CNT.
New Period written to
PERB that is lower
than current CNT.
New PER is updated
with PERB value.
20.3.3.4 Compare Channel
Each Compare Channel n continuously compares the counter value (TCAn.CNT) with the Compare n
register (TCAn.CMPn). If TCAn.CNT equals TCAn.CMPn, the comparator n signals a match. The match
will set the Compare Channel's Interrupt flag at the next timer clock cycle, and the optional interrupt is
generated.
The Compare n Buffer register (TCAn.CMPnBUF) provides double buffer capability equivalent to that for
the period buffer. The double buffering synchronizes the update of the TCAn.CMPn register with the
buffer value to either the TOP or BOTTOM of the counting sequence, according to the UPDATE condition.
The synchronization prevents the occurrence of odd-length, non-symmetrical pulses for glitch-free output.
20.3.3.4.1 Waveform Generation
The compare channels can be used for waveform generation on the corresponding port pins. To make
the waveform visible on the connected port pin, the following requirements must be met:
1. A Waveform Generation mode must be selected by writing the WGMODE bit field in TCAn.CTRLB.
2. The TCA is counting clock ticks, not events (CNTEI=0 in TCAn.EVCTRL).
3. The compare channels used must be enabled (CMPnEN=1 in TCAn.CTRLB). This will override the
corresponding port pin output register. An alternative pin can be selected by writing to the
respective TCA Waveform Output n bit (TCA0n) in the Control C register of the Port Multiplexer
(PORTMUX.CTRLC).
4. The direction for the associated port pin n must be configured as an output (PORTx.DIR[n]=1).
5. Optional: Enable inverted waveform output for the associated port pin n (INVEN=1 in PORTx.PINn).
20.3.3.4.2 Frequency (FRQ) Waveform Generation
For frequency generation, the period time (T) is controlled by a TCAn.CMPn register instead of the Period
register (TCAn.PER). The waveform generation output WG is toggled on each compare match between
the TCAn.CNT and TCAn.CMPn registers.
ATtiny1614
TCA - 16-bit Timer/Counter Type A
© 2019 Microchip Technology Inc. Preliminary Datasheet 40001995B-page 197
Figure 20-9. Frequency Waveform Generation
CNT
WG Output
MAX
TOP
BOTTOM
Period (T) Direction change CNT written
"update"
The waveform frequency (fFRQ) is defined by the following equation:
FRQ =fCLK_PER
2CMPn+1
where N represents the prescaler divider used (CLKSEL in TCAn.CTRLA), CMPn is the value of the
TCAn.CMPn register, and fCLK_PER is the system clock for the peripherals.
The maximum frequency of the waveform generated is half of the peripheral clock frequency (fCLK_PER/2)
when TCAn.CMPn is written to zero (0x0000) and no prescaling is used (N=1, CLKSEL=0x0 in
TCAn.CTRLA).
20.3.3.4.3 Single-Slope PWM Generation
For single-slope Pulse-Width Modulation (PWM) generation, the period (T) is controlled by TCAn.PER,
while the values of TCAn.CMPn control the duty-cycle of the WG output. The figure below shows how the
counter counts from BOTTOM to TOP and then restarts from BOTTOM. The waveform generator (WO)
output is set at TOP and cleared on the compare match between the TCAn.CNT and TCAn.CMPn
registers.
Figure 20-10. Single-Slope Pulse-Width Modulation
CNT
Output WOn
MAX
TOP
CMPn
BOTTOM
Period (T) CMPn=BOTTOM CMPn=TOP "update"
"match"