IRL40SC209 Datasheet by Infineon Technologies

View All Related Products | Download PDF Datasheet
@ DzFAK-‘er |RL4USCQUB D V.
IR MOSFET
StrongIRFET™
IRL40SC209
HEXFET® Power MOSFET
D
S
G
Application
Brushed Motor drive applications
BLDC Motor drive applications
Battery powered circuits
Half-bridge and full-bridge topologies
Synchronous rectifier applications
Resonant mode power supplies
OR-ing and redundant power switches
DC/DC and AC/DC converters
DC/AC Inverters
Benefits
Optimized for Logic Level Drive
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
Lead-Free*
RoHS Compliant, Halogen-Free
VDSS 40V
RDS(on) typ. 0.6m
max 0.8m
ID (Silicon Limited) 478A
ID (Package Limited) 300A
Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature
G D S
Gate Drain Source
1 2017-05-12
D2PAK-7Pin
IRL40SC209
D
G S
S S
S
S
Base Part Number Package Type Standard Pack Orderable Part Number
Form Quantity
IRL40SC209 D2PAK-7Pin Tape and Reel Left 800 IRL40SC209
2 4 6 8 10 12 14 16 18 20
VGS, Gate -to -Source Voltage (V)
0.0
1.0
2.0
3.0
4.0
5.0
RDS(on)
, Drain-to -Source On Resistance (m
)
ID = 100A
TJ = 25°C
TJ = 125°C
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
100
200
300
400
500
ID, Drain Current (A)
Limited By Package
S
Parameter Tsm Avalanche Characteristics EAS ermz‘ mm IAR EAR Thermal Resistance bol Parameter V55 V55 = 10V, ID Vss D Ves, ID VDs Gs VDS = 40V,VGS V55 (35 hflgJ/www mflneon,Com/‘echmcalrwnfo/aggnmes/an7994gdf
2 2017-05-12
IRL40SC209
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 300A. Note that
Current imitations arising from heating of the device leads may occur with some lead mounting arrangements.
(Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.146mH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 954A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 53A, VGS =10V.
Pulse drain current is limited to 1200A by source bonding technology.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques
refer to application note #AN-994: http://www.infineon.com/technical-info/appnotes/an-994.pdf
Absolute Maximum Rating
Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 478
A
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 338
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 300
IDM Pulsed Drain Current  1200
PD @TC = 25°C Maximum Power Dissipation 375 W
Linear Derating Factor 2.5 W/°C
VGS Gate-to-Source Voltage ± 20 V
TJ
TSTG
Operating Junction and
Storage Temperature Range
-55 to + 175 °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy  728 mJ
EAS (Thermally limited) Single Pulse Avalanche Energy  1404
IAR Avalanche Current See Fig 15, 16, 23a, 23b A
EAR Repetitive Avalanche Energy mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case  ––– 0.4
°C/W
RCS Case-to-Sink, Flat Greased Surface 0.50 –––
RJA Junction-to-Ambient ––– 62
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 40 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.031 ––– V/°C Reference to 25°C, ID = 5mA
RDS(on) ––– 0.6 0.8 m VGS = 10V, ID = 100A
––– 0.8 1.1 VGS = 4.5V, ID = 50A
VGS(th) Gate Threshold Voltage 1.0 ––– 2.4 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS = 40 V, VGS = 0V
––– ––– 150 VDS = 40V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Gate Resistance ––– 2.1 ––– 
Static Drain-to-Source On-Resistance
3 2017-05-12
IRL40SC209
D
S
G
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 244 ––– ––– S VDS = 10V, ID = 100A
Qg Total Gate Charge ––– 178 267 ID = 100A
Qgs Gate-to-Source Charge ––– 49 ––– VDS = 20V
Qgd Gate-to-Drain Charge ––– 88 ––– VGS = 4.5V
Qsync Total Gate Charge Sync. (Qg– Qgd) ––– 90 –––
td(on) Turn-On Delay Time ––– 63 –––
ns
VDD = 20V
tr Rise Time ––– 182 ––– ID = 30A
td(off) Turn-Off Delay Time ––– 182 ––– RG= 2.7
tf Fall Time ––– 138 ––– VGS = 4.5V
Ciss Input Capacitance ––– 15270 –––
pF
VGS = 0V
Coss Output Capacitance ––– 1960 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 1370 ––– ƒ = 1.0MHz, See Fig.7
Coss eff.(ER) Effective Output Capacitance (Energy Related) ––– 2305 ––– VGS = 0V, VDS = 0V to 32V
Coss eff.(TR) Output Capacitance (Time Related) ––– 2935 ––– VGS = 0V, VDS = 0V to 32V
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 478
A
MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 1200 integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.2 V TJ = 25°C,IS =100A,VGS = 0V
dv/dt Peak Diode Recovery dv/dt  ––– 2.2 ––– V/ns TJ = 175°C,IS = 100A,VDS = 40V
trr Reverse Recovery Time ––– 51 –––
ns TJ = 25°C VDD = 34V
––– 53 ––– TJ = 125°C IF = 100A,
Qrr Reverse Recovery Charge ––– 79 –––
nC TJ = 25°C di/dt = 100A/µs
––– 82 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 2.5 ––– A TJ = 25°C
nC
@ V
4 2017-05-12
IRL40SC209
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
Fig 4. Typical Output Characteristics
Fig 3. Typical Output Characteristics
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
6.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.25V
60µs PULSE WIDTH
Tj = 25°C
3.25V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
6.0V
5.0V
4.5V
4.0V
3.5V
BOTTOM 3.25V
60µs PULSE WIDTH
Tj = 175°C
3.25V
012345
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 10V
60µs PULSE WIDTH
-60 -20 20 60 100 140 180
TJ , Junction Temperature (°C)
0.6
1.0
1.4
1.8
2.2
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 100A
VGS = 10V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
100000
1000000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200 250 300 350 400 450
QG, Total Gate Charge (nC)
0
2
4
6
8
10
12
14
VGS, Gate-to-Source Voltage (V)
VDS= 32V
VDS= 20V
VDS= 8V
ID= 100A
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
0 fl. LlM‘TED av FIDS Tc : 25‘s T1 : 175%: VGS : 3.5V VGS : 4.5V VGS : 6.0V _\/GS : 8.0 A iii:
5 2017-05-12
IRL40SC209
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode Forward Voltage
Fig 13. Typical On-Resistance vs. Drain Current
Fig 11. Drain-to-Source Breakdown Voltage Fig 12. Typical Coss Stored Energy
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VSD, Source-to-Drain Voltage (V)
0.1
1
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-60 -20 20 60 100 140 180
TJ , Temperature ( °C )
40
42
44
46
48
50
52
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5.0mA
0.1 1 10
VDS, Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
DC
Limited by Package
0 10203040
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Energy (µJ)
050 100 150 200
ID, Drain Current (A)
0.4
0.8
1.2
1.6
2.0
RDS(on), Drain-to -Source On Resistance (
m)
VGS = 3.5V
VGS = 4.5V
VGS = 6.0V
VGS = 8.0V
VGS = 10V
@ \NGLE PULSE mes, 1, Duty Factor D : «1/12 pu‘sewxdlh‘ tav‘ assummg vs ava‘anch pu‘sewldm, tav‘ T
6 2017-05-12
IRL40SC209
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 16. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.infineon.com)
1.Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for every
part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not
exceeded.
3. Equation below based on circuit and waveforms shown in Figures
23a, 23b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage
increase during avalanche).
6. Iav = Allowable avalanche current.
7. T = Allowable rise in junction temperature, not to exceed Tjmax
(assumed as 25°C in Figure 14, 15).
t
av = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
Z
thJC(D, tav) = Transient thermal resistance, see Figures 14)
PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC
I
av = 2T/ [1.3·BV·Zth]
E
AS (AR) = PD (ave)·tav
Fig 15. Avalanche Current vs. Pulse Width
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.0001
0.001
0.01
0.1
1
Thermal Response ( Z
thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming j = 25°C and
Tstart = 150°C.
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart = 25°C (Single Pulse)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 100A
~\ ‘ \ . \\ \ \ — \ \ _ _ §\ >\ >:<\ ,v’="" ,="" id="" :="" 250m="" .="" ¢="" id="" :="" 1="" [ma="" _="" ,="" .="" _="" ’="" ’="" i="" .="" .="" .="" i="" i="" .="" .="" ,="" ,="" i="" ’="" ,="" ,="" i="">
7 2017-05-12
IRL40SC209
Fig 17. Threshold Voltage vs. Temperature
Fig 21. Typical Stored Charge vs. dif/dt
Fig 19. Typical Recovery Current vs. dif/dt Fig 20. Typical Stored Charge vs. dif/dt
0200 400 600 800
diF /dt (A/µs)
0
3
6
9
12
15
18
IRRM (A)
IF = 100A
VR = 34V
TJ = 25°C
TJ = 125°C
0200 400 600 800
diF /dt (A/µs)
0
3
6
9
12
15
18
21
IRRM (A)
IF = 60A
VR = 34V
TJ = 25°C
TJ = 125°C
-75 -25 25 75 125 175
TJ , Temperature ( °C )
0.0
0.5
1.0
1.5
2.0
2.5
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
0200 400 600 800
diF /dt (A/µs)
0
250
500
750
1000
1250
1500
QRR (nC)
IF = 60A
VR = 34V
TJ = 25°C
TJ = 125°C
Fig 18. Typical Recovery Current vs. dif/dt
0200 400 600 800
diF /dt (A/µs)
0
250
500
750
1000
QRR (nC)
IF = 100A
VR = 34V
TJ = 25°C
TJ = 125°C
(D Dm-lG-m nu] , , _<‘ w="" ‘="" h="" ww="" :1="" a="" cm="" um="" www;="" ,="" ‘="" .="" m="" sway="" .mmm="" ,="" .="" gmund="" pun:=""><' .="" musing;="" mm“="" (,3="" d“="" ‘spwww="" ,="" .="" curllnltmnsmvmev="" .fl="" fin-m="" w="" w="" mw="" v="" m="" te)="" t="" amm©="" cm="" w="" n="" w="" vm="" www.“="" :,="" um="" um.="" w="" avldx="" 'y="" \="" ‘v="" (d="" '—="" vim="" rs="" .="" m.="" mm="" w="" r="" vdal="" mm.“="" .="" r="" .="" dvwzv="" same="" lype="" as="" d="" u="" t="" _="" v="" vflmr="" 5w!="" emo-="" annm="" dice="" .="" \m="" mum="" w="" dulv="" am="" "a="" ,="" l4)="" mw="" mm="" -="" d="" u="" w="" device="" mm="" rm="" rifi="" i="" m="" w="" s="" 5-,;="" my="" w="" a="" ’="" v55="" :="" 5v="" var="" logic="" leve‘="" dewces="" #7="" 4»="" «="" a="" ]="" g5:="" 4l="" y="" ,="" v="" i="" ”a="" vus="" vns="" ,="" 90%="" v“="" ‘="" mn="" --:vm="" \="" 77="" \="" 111‘="" was="" «7%.="" mum”.="" v53="" \="" ‘="" \="" mum“.="" p._4="" 1;="" 1mm)="" i,="" mm}="" k="" d="" home;="" dut="" .="">
8 2017-05-12
IRL40SC209
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
Fig 23a. Unclamped Inductive Test Circuit
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
Fig 24a. Switching Time Test Circuit
Fig 25a. Gate Charge Test Circuit
tp
V
(BR)DSS
I
AS
Fig 23b. Unclamped Inductive Waveforms
Fig 24b. Switching Time Waveforms
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
Fig 25b. Gate Charge Waveform
VDD
m J# L,‘ w ,E[ 1 ‘ H: E z 1‘ Inf neon m u LIZ, p HWE HT E E H EJHEx L, EHL,HEL \T, , ,U ET E m E , w E \HE E EETH T ,EE\,L T \mExwa \w LExE TH T E EEH ,E T ,Txv EEETEET T xwawx, E E H \Eflfi
9 2017-05-12
IRL40SC209
D2Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches))
D2Pak - 7 Pin Part Marking Information
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
Y = YEAR
W = WEEK
P = LEADFREE
89
YWWP
17
PART NUMBER
F1324S-7P
@ Qualification Information IMPORTANT NOTICE no event www.infineon.com) WARNINGS n_ot
10 2017-05-12
IRL40SC209
Applicable version of JEDEC standard at the time of product release.
Qualification Information
Qualification Level
Industrial
(per JEDEC JESD47F)
Moisture Sensitivity Level
MSL1
(per JEDEC J-STD-020D)
RoHS Compliant Yes
D2PAK-7Pin
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2015
All Rights Reserved.
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any
information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third
party.
In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this
document and any applicable legal requirements, norms and standards concerning customer’s products and any use of
the product of Infineon Technologies in customer’s applications.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of
customer’s technical departments to evaluate the suitability of the product for the intended application and the
completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies office (www.infineon.com).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question
please contact your nearest Infineon Technologies office.
Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized
representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a
failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
Revision History
Date Comments
05/12/2017  Corrected package picture added “s” on pin number 4 - page 1.

Products related to this Datasheet

MOSFET N-CH 40V 478A D2PAK
MOSFET N-CH 40V 478A D2PAK
MOSFET N-CH 40V 478A D2PAK