NCP5623 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2008
October, 2008 Rev. 6
1Publication Order Number:
NCP5623/D
NCP5623
Triple Output I2C Controlled
RGB LED Driver
The NCP5623 mixed analog circuit is a triple output LED driver
dedicated to the RGB illumination or backlight LCD display.
Features
2.7 to 5.5 V Input Voltage Range
RGB Function Fully Supported
Programmable Integrated Gradual Dimming
90 mA Total LED Current Capability
Provides Three Independent LED Drives
Support I2C Protocol
This is a PbFree Device
Typical Applications
Multicolor Illuminations
Portable Back Light
Digital Cellular Phone Camera Photo Flash
LCD and Key Board Simultaneous Drive
D1
C2
GND
C1
GND
SDA
R1
62 k
GND
SCL
+Vbat
+Vcc
MCU
I2C Port
Vdet
12
IREF
10
SDA
9
SCL
11
GND
6
LED3 3
LED2 4
LED1 5
U1
NCP5623
Figure 1. Typical Multiple Color LED Driver
1 mF/6.3 V
1 mF/6.3 V
GND
Vbat
13
GND
2
IC NC NC IC
17814
+5 V
5
2
6
4
3
1
R
G
B
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Device Package Shipping
ORDERING INFORMATION
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
MARKING
DIAGRAM
5623 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
NCP5623DTBR2G TSSOP14
(PbFree)
2500 /
Tape & Reel
1
14 TSSOP14
CASE 948G
5623
ALYWG
G
1
14
(Note: Microdot may be in either location)
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Figure 2. Pin Assignments
TSSOP14
2
3
4
5
6
7
14
13
12
10
9
(Top View)
LED1
IC
GND
LED3
LED2
GND
NC
IC
Vbat
IREF
SDA
Vdet
NC
11 SCL
1
8
D1D2D3
C2
GND
GND
Vbat
C1
GND
SDA
R1
62 k
GND
DIGITAL CONTROL
PWM LED#1
CURRENT
NCP5623
Vbat
GND
SCL
PWM LED#2
PWM LED#3
FUNCTIONS
GND
GND
GND
GND
LED1
LED2
LED3
Vbat
Figure 3. Simplified Block Diagram
ANALOG
1 mF/6.3 V 1.0 mF/6.3 V
MIRRORS
13
6
10
9
11
1 7
3
4
5
2
8 14
12 IC NC NC IC
+5 V
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PIN ASSIGNMENT
Pin Name Type Description
1 IC This pin is internally connected. It must be left open.
2 GND POWER This pin is the GROUND signal for the analog and digital blocks and output current control. The
pin must be connected to the system ground, a ground plane being strongly recommended.
3 LED3 OUTPUT,
POWER
This pin sinks to ground and monitors the current flowing into the BLUE LED, intended to be
used in illumination application (Note 1). The Anode of the associated LED shall be connected
to the Vbat supply.
4 LED2 OUTPUT,
POWER
This pin sinks to ground and monitors the current flowing into the GREEN LED, intended to be
used in illumination application (Note 1). The Anode of the associated LED shall be connected
to the Vbat supply.
5 LED1 OUTPUT,
POWER
This pin sinks to ground and monitors the current flowing into the RED LED, intended to be
used in illumination application (Note 1). The anode of the associated LED shall be connected
to the Vbat supply.
6 GND ANALOG
GROUND
This pin copies the Analog Ground and shall be connected to the system ground plane.
7, 8 NC This pin must be left floating with no connection.
9 SDA INPUT,
DIGITAL
This pin carries the data provided by the I2C protocol. The content of the SDA byte is used to
program the mode of operation and to set up the output current.
10 IREF ANALOG This pin provides the reference current, based on the internal bandgap voltage reference, to
control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to
get the highest accuracy of the LED current. An external current mirror can be used to bias this
pin to dynamically set up the LED maximum current.
In no case shall the voltage at IREF pin be forced either higher or lower than the 600 mV
provided by the internal reference.
11 SCL INPUT,
DIGITAL
This pin carries the I2C clock to control the I2C communication. The SCL clock is associated
with the SDA signal.
12 Vdet INPUT This pin provides a DC bias to the internal circuit and must be connected to the same voltage
that the one applied to the Vbat pin 13.
13 Vbat POWER This pin is the input Battery voltage to supply the analog and digital blocks. The pin must be
decoupled to ground by a 1 mF or higher ceramic capacitor (Note 2).
14 IC This pin is internally connected. It must be left open.
1. The maximum current is 37 mA for each LED
2. Using low ESR ceramic capacitor, X5R type, is recommended.
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MAXIMUM RATINGS
Symbol Rating Value Unit
Vbat Power Supply (see Figure 4) 0.3 < Vbat < 7.0 V
SDA, SCL Digital Input Voltage 0.3 < V < Vbat V
ESD Human Body Model: R = 1500 W, C = 100 pF (Note 3)
Machine Model
2
200
kV
V
PD
RqJC
RqJA
Power Dissipation @ TA = +85°C (Note 4)
Thermal Resistance Junction to Case
Thermal Resistance Junction to Air
235
46
170
mW
°C/W
°C/W
TAOperating Ambient Temperature Range 40 to +85 °C
TJOperating Junction Temperature Range 40 to +125 °C
TJmax Maximum Junction Temperature +150 °C
Tstg Storage Temperature Range 65 to +150 °C
ILATCHUP Latchup current maximum rating per JEDEC standard: JESD78. ±100 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: JSTD020A.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22A114
Machine Model (MM) ±200 V per JEDEC standard: JESD22A115
4. The maximum package power dissipation limit must not be exceeded.
POWER SUPPLY SECTION:
(Typical values are referenced to TA = +25°C, Min & Max values are referenced 40°C to +85°C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin Symbol Rating Min Typ Max Unit
13 Vbat Power Supply 2.7 5.5 V
13 Istdb Stand By Current
3.0 V Vbat 4.2 V, ILED = 0 mA
0.8 1.0 mA
13 Iop Operating Current,
@ILED = 0 mA, 3.0 V Vbat 4.2 V
350 mA
3,4,5 ITOL RGB Output Current Tolerance
@Vbat = 3.6 V, ILED = 10 mA
25°C < TA < 85°C
±3 %
3,4,5 IMATCH RGB Output Current LED Matching
@Vbat = 3.6 V, ILED = 5.0 mA
±0.5 %
Fpwr Internal Clock Operating Frequency
40°C < TA < 85°C
0.8 1 1.2 MHz
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ANALOG SECTION:
(Typical values are referenced to TA = +25°C, Min & Max values are referenced 40°C to +85°C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin Symbol Rating Min Typ Max Unit
10 IREF Reference current @VREF = 600 mV
(Note 5, Note 8)
3 12.5 20 mA
10 VREF Reference Voltage (Note 5) 3% 600 +3% mV
ILEDR Reference Current (IREF) current ratio 2400
10 Rbias External Reference current Bias resistor (Note 6) 30 48 200 kW
3,4,5 FPWM Internal PWM Frequency (Note 7) 2.1 kHz
5. The external circuit must not force the IREF pin voltage either higher or lower than the 600 mV specified. The system is optimized with a
12.5 mA reference current.
6. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended.
7. This parameter, derived from the 1 MHz clock, is guaranteed by design, not tested in production.
DIGITAL PARAMETERS SECTION:
(Typical values are referenced to TA = +25°C, Min & Max values are referenced 40°C to +85°C ambient temperature, unless otherwise
noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin Symbol Rating Min Typ Max Unit
11 FSCL Input I2C clock frequency 400 kHz
9,11 VIH Positive going Input High Voltage Threshold,
SDA, SCL signals (Note 8)
1.6 Vbat V
9,11 VIL Negative going Input Low Voltage Threshold,
SDA, SCL signals (Note 8)
0 0.4 V
NOTE: Digital inputs undershoot 0.30 V to ground, Digital inputs overshoot < 0.30 V to Vbat
8. Test guaranteed by design and fully characterized, not implemented in production.
2.0 V
2.7 V
4.2 V
5.5 V
3.0 V
Power On Reset
NORMAL LiIon
Maximum Voltage Operation
OPERATION
No operation during POR
7.0 V Absolute Maximum Rating
Chip functionnal, but no parameter guaranteed
when Vbat is between 5.5 V & 7.0 V
The chip might be damaged or destroyed
Reserved for internal Reset
when Vbat is above 7.0 V
Figure 4. Understanding Integrated Circuit Voltage Limitations
Note: the internal POR sequence is 850 ms maximum long
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LED MAXIMUM CURRENT CALCULATION
The load current is derived from the 600 mV reference
voltage provided by the internal Band Gap associated to the
external resistor connected across IREF pin and Ground.
Note : due to the internal structure of this pin, no voltage,
either downward or upward, shall be forced at the IREF pin.
The reference current is multiplied by the constant
k = 2400 to yield the output load current. Since the reference
voltage is based on a temperature compensated Band Gap,
a tight tolerance resistor will provide a very accurate load
current. The resistor is calculated from the Ohm’s law (Rbias
= VREF/IREF) and a more practical equation can be arranged
to define the resistor value for a given maximum output
current ILEDmax:
Rbias = (VREF*k)/ILEDmax [ 1 ]
Rbias = (0.6*2400)/ILEDmax
Rbias = 1440/ILEDmax [ 2 ]
Since the IREF to ILEDmax ratio is very high, it is strongly
recommended to set up the reference current at 12.5 mA to
optimize the tolerance of the output current. Although it is
possible to use higher or lower value, as defined in the
analog section, a 48 kW / 1% resistor will provide the best
compromise, the dimming being performed by the
appropriate PWM registers.
On the other hand, care must be observed to avoid leakage
current flowing into either the IREF pin of the bias resistor
network.
Finally, for any desired ILED current, the curve provided
Figure 5 can be recalculated according to the equation:
ILED +
IREF @k
31 *n(eq. 1)
ILED +
VREF
Rbias
@2400
31 *n(eq. 2)
with: n = step value @ 1 n 31
with: Rbias = reference resistance
with: k = internal multiplier constant = 2400
Note: n=0 ILED is set to zero
n = 31 ILED is set to the same current as n = 30
LOAD CONNECTION
The primary function of the NCP5623 is to control three
LED arranged in the RGB color structure (reference
OSRAM LATB G66x). The brightness of each LED is
independently controlled by a set of dedicated PWM
structure embedded into the silicon chip. The maximum
current, identical for each LED, is programmable by means
of the I2C data byte. With 32 steps per PWM, the chip
provides 32768 colors hue in a standard display.
Moreover, a builtin gradual dimming provides a smooth
brightness transition for any current level, in both Upward
and Downward direction. The dimming function is
controlled by the I2C interface: see Table 2.
The NCP5623 chip is capable to drive the three LED
simultaneously, as depicted in Figure 1, but the load can be
arranged to accommodate several LED if necessary in the
application. Finally, the three current mirrors can be
connected in parallel to drive a single powerful LED, thus
yielding 90 mA current capability in a single LED.
I2C PROTOCOL
The NCP5623 is programmed by means of the standard
I2C protocol controlled by an external MCU. The
communication takes place with two serial bytes sharing the
same I2C frame:
Byte#1 ³ physical I2C address
Byte#2 ³ Selected internal registers & function
B7 B6 B5 B4 B3 B2 B1 B0
Byte#1 : I2C Physical Address, based 7 bits : % 011 1000 ³ $38 *
01 1 1 0 0 0 R/W
Byte#2 : DATA register
RLED2 RLED1 RLED0 BLED4 BLED3 BLED2 BLED1 BLED0
*Note: according to the I2C specifications, the physical address is based on 7 bits out of the SDA byte, the 8th bit representing the R/W command.
Since the NCP5623 is a receiver only, the R/W command is 0 and the hexadecimal byte send by the MCU is %0111 0000 = $70
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B[7:5] : Internal Register Selection:
B7 B6 B5 Function
0 0 0 Chip Shut Down ³ all LED current = zero
0 0 1 Set up the maximum Output LED Current
0 1 0 PWM1 : Red LED control
0 1 1 PWM2 : Green LED control
1 0 0 PWM3 : Blue LED control
1 0 1 Set the Upward Iend target
1 1 0 Set the Downward Iend target
1 1 1 Gradual Dimming Step Time and Run
The contain of bits B[4:0] depends upon the type of function selected by bits B[7:5] as depicted in Table 1
Table 1. Internal Register Bits Assigment
B7 B6 B5 B4 B3 B2 B1 B0 Comments
0 0 0 X X X X X Shut down
0 0 1 16 8 4 2 1 LED Current Step, see Figure 5 (Note 9)
0 1 0 BPWM16 BPWM8 BPWM4 BPWM2 BPWM1 Red PWM
0 1 1 BPWM16 BPWM8 BPWM4 BPWM2 BPWM1 Green PWM
1 0 0 BPWM16 BPWM8 BPWM4 BPWM2 BPWM1 Blue PWM
1 0 1 GDIM5
16
GDIM4
8
GDIM3
4
GDIM2
2
GDIM1
1
Set Gradual Dimming
Upward Iend Target (Note 10)
1 1 0 GDIM5
16
GDIM4
8
GDIM3
4
GDIM2
2
GDIM1
1
Set Gradual Dimming
Downward Iend Target (Note 10)
1 1 1 GDIM5
128 ms
GDIM4
64 ms
GDIM3
32 ms
GDIM2
16 ms
GDIM1
8 ms
Gradual Dimming
Time & run
9. The programmed current applies to the three LED simultaneously, the gradual dimming is not engaged
10.The bit values represent the steps count, not the ILED current: see equations 1 & 2, page 6, to derive the ILED value.
GRADUAL DIMMING
The purpose of that function is to gradually Increase or
Decrease the brightness of the backlight LED upon
command from the external MCU. The function is activated
and controlled by means of the I2C protocol.
In order to avoid arithmetic division functions at silicon
level, the period (either upward or downward) is equal to the
time defined for each step, multiplied by the number of
steps.
To operate such a function, the MCU will provide two
information:
1 – The target current level (either upward or downward)
2 – The time per step and run
When a new gradual dimming sequence is requested, the
output current increases, according to an exponential curve,
from the existing start value to the end value. The end current
value is defined by the contain of the Upward or Downward
registers, the width of each step is defined by the Time and
run register, the number of step being in the 1 to 31 range.
In the event of software error, the system checks that neither
the maximum output current (30 mA), nor the zero level are
forced out of their respective bounds. Similarly, software
errors shall not force the NCP5623 into an uncontrolled
mode of operation.
The dimming is built with 30 steps and the time delay
encoded into the second byte of the I2C transaction: see
Table 1.
When the gradual dimming is deactivated (B7 = B6 = 0,
B5 = 1), the output current is straightforwardly set up to the
level defined by the contain of the related register upon
acknowledge of the output current byte.
The gradual dimming sequence must be set up before a
new output current data byte is send to the NCP5623 . At this
point, the brightness sequence takes place when the new data
byte is acknowledged by the internal I2C decoder. Since the
six registers are loaded on independent byte flow associated
to the I2C address, any parameter of the NCP5623 chip can
be updated ahead of the next function as depicted in Table 2.
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Table 2. Basic Programming Sequences
I2C Address COMMAND Bits[7:0] Operation Note
$70 000X XXXX System Shut Down Bits[4:0] are irrelevant
$70 0010 0000
0011 1111
Set Up the ILED current ILED register
Bits[4:0] contain the ILED value as defined by the IREF value
$70 0100 0000
0101 1111
Set Up the RED PWM REDPWM
Bits[4:0] contain the PWM value
$70 0110 0000
0111 1111
Set Up the GREEN PWM GREENPWM
Bits[4:0] contain the PWM value
$70 1000 0000
1001 1111
Set Up the BLUE PWM BLUEPWM
Bits[4:0] contain the PWM value
$70 1010 0000
1011 1111
Set Up the IEND Upward UPWARD
Bits[4:0] contain the IEND value
$70 1100 0000
1101 1111
Set Up the IEND Downward DWNWRD
Bits[4:0] contain the IEND value
$70 1110 0001
1111 1111
Set Up the Gradual Dimming
time and run the sequence
GRAD
Bits[4:0] contain the TIME value
The number of step for a given sequence, depends upon
the start and end output current range: since the ILED value
is encoded in the Bits[4:0] binary scale, a maximum of 31
steps is achievable during a gradual dimming operation.
The number of steps will be automatically recalculated by
the chip according to the equation:
Nstep = | existing step position new step position |
As an example, assuming the previously programmed
step was 5 and the new one is 15, then we will have 10 steps
to run between the actual location to the end value. If the
timing was set at 16 ms, the total gradual dimming sequence
will be 160 ms.
To select the direction of the gradual dimming (either
Upward or Downward), one shall send the appropriate
register before to activate the sequence as depicted below:
1010 1111 ³ 1110 0011 ³ select an UPWARD sequence
with 24 ms/step, the end ILED current being
(IREF*2400)/(3115)
1100 0001 ³ 1110 0100 ³ select the DOWNWARD
sequence with 32 ms/step, the end ILED current being
(IREF*2400)/(311).
Table 3. Output Current Programmed Value (ILED = F(Step))
Step ILED (mA) Step ILED (mA) Step ILED (mA) Step ILED (mA)
0 / $00 09 / $09 1.25 18 / $12 2.12 27 $1B 6.90
1 / $01 0.92 10 / $0A 1.31 19 / $13 2.30 28 / $1C 9.20
2 / $02 0.95 11 / $0B 1.38 20 / $14 2.50 29 / $1D 13.80
3 / $03 0.98 12 / $0C 1.45 21 / $15 2.76 30 / $1E 27.60
4 / $04 1.02 13 / $0D 1.53 22 / $16 3.06 31 / $1F 27.60
5 / $05 1.06 14 / $0E 1.62 23 / $17 3.45
6 / $06 1.10 15 / $0F 1.72 24 / $18 3.94
7 / $07 1.15 16 / $10 1.84 25 / $19 4.60
8 / $08 1.20 17 / $11 1.97 26 / $1A 5.52
NOTE: The table assumes IREF = 11.5 mA
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Figure 5. Output Current Programmed Value ( ILED = F(Step) )
Step
352520151050
0
15
30
ILED (mA)
30
10
25
5
20
PWM OPERATION
The builtin PWM are fully independent and can be
programmed to any value during the normal operation of the
NCP5623 chip. The PWM operate with five bits, yielding a
32 steps range to cover the full modulation (0 to 100%) of
the associated LED:
PWM = $00 ³ the associated LED is fully OFF,
whatever be the programmed ILED value
PWM > $00 but < $1F ³ the brightness of the
associated LED is set depending upon the PWM
modulation value
PWM = $1F ³ the associated LED is fully ON, the
current being the one defined by the ILED value.
Each PWM is programmable, via the I2C port as depicted,
at any time under any sequence arrangement as requested by
the end system’s designer. The PWM does not change the
ILED value, but merely modulate the ON/OFF ratio of the
associated LED. Each step of the PWM represent 100/31 =
3.225% of the full range, the clock being 2.1 kHz (typical).
Figure 6. Basic RGB Application
D1
C2
GND
C1
GND
SDA
R1
62 k
GND
SCL
+Vbat
+Vcc
MCU
I2C Port
Vdet
12
IREF
10
SDA
9
SCL
11
GND
6
LED3 3
LED2 4
LED1 5
U1
NCP5623 1 mF/6.3 V
1 mF/6.3 V
GND
Vbat
13
GND
2
IC NC NC IC
17814
+5 V
5
2
6
4
3
1
R
G
B
LRTBG6T
MECHANICAL CASE OUTLINE on semiwnduflm" PACKAGE DIMENSIONS TSSOPEI 4 WE CASE 9486 ‘4 * ISSUE C \ I DATE 17 FEB 2016 ‘ SCALE 2” on K as; NOTES I DIMENSIONING AND TOLERANCING PER j ._.IIJIIJI104)® ANSWMSM 1982 2 CONTROLLING DIMENSION MILLIMETER 06- T U ® a DIMENSION A DOES NOT INCLUDE MOLD FLASH PROTRUSIONS 0R eAIE swans H H H H H H H N MOLD FLASH 0R GATE BURRS SHALL NOT EXCEED D I5 I0 006) PER SIDE A DIMENSION a DOES NOT INCLUDE INIERLEAD FLASH 0R PROTRUSION M INIERLEAD FLASH 0R PROTRUSION sHALL NOI EXCEED II 25 ID mm PER SIDE ’ 5 DIMENSION K DOES NOT INCLUDE DAMBAR E El N 7 PROIRUSION ALLOWABLE DAMEAR PROIRUSION SHALL BE D as (0 mm TOTAL F IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION DETAIL E 5 IERMINAL NUMEERS ARE SHOWN FOR H H H H H H H I K MILLIME'IERS INCHES L 4» K11; MIN MAX MIN MAx I I I Is sss T1 SECTION N-N n Efm o— /' _T—SEAIIIIG n 46L 4 H DETAILE E_5 usu Ins mm mm] assasc uuzsesc usu um mm mm In»; 020 0004 DUDE on»; am 0004 0006 Ins Inn 0007 cam Ins 025 0007 cam souasc uzszesc u‘W a“ a" a‘ GENERIC MARKING DIAGRAM‘ :I—ZXELzmwanw); nus nIs mm 0006 mm: SOLDERING FOOTPRINT ‘4 HHELUH xxxx H— 7.06 4H ALVW- o . I:| :I' I HHHHHHH : :l A s Assembl LocaIIon y |:| |:| L : WaIeI LoI v s Year E E w : WM Week :| El 0 65 . : Pb—Free Package L |:| EF P'TCH (Note. Micmam may be in ma locaIIonI ‘This information Is genenc PIssss IeIsI Io ”X T E X E T devIce dale sheeI IoI aclual pan markmg, o 36 “‘26 Pb—Flee IndiCaIcrI “G“ or miCrcdoI " ' DIMENSIONS MILLIMETERS may OI may n01 be presenl ON SsHIssIIIIsIsI m J IsssImIIs sI SsmIssmIsIsI cIHssIsIm IIIIIsIIss. LLC dba ON SsIIIssmIsIsI sI IIs sIhsIIIIsIIss II IIs Unwed SIsIss andJm sIHsI ssIIIIssI ON SsmIssmIsIsI IsssIss IHs .IsHI Is .mks smmss wIImIII mm. mssII Is my pIssssIs IssII ON SsIHIssIIIsIsI msAss m wsIIsmI. IssIsssIIsmI sI sIsIsIIss IsssIIIIs IHs sIIIIsIIIIIII nI IIs sIssIsm III s"Y ssIIsIIsI sIIssss ssss ON SsIIIsIIIIIsIsI sssssm sm IIsIIIIIIY sIIsIIs IIIIsI IIs sspIIssIIsI s. H W sIsIIIsIsI sIIssII sm ssssIIIsst .IIssIsms sIY sm sII IIsIIIIIIY IIsIIsIIs wIImII IImIsIIsn ssssIsI ssmswsIIIsI s. ImIssIIsI Ismssss ON SsmmmIsIsI Isss mI ssmsy s"Y IIssm was Is ssIsII Isms IIs IIsHs sIsIHsIs
TSSOP14 WB
CASE 948G
ISSUE C
DATE 17 FEB 2016
SCALE 2:1
1
14
*This information is generic. Please refer to
device data sheet for actual part marking.
PbFree indicator, “G” or microdot “ G”,
may or may not be present.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
LU
SEATING
PLANE
0.10 (0.004)
T
SECTION NN
DETAIL E
JJ1
K
K1
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
V
14X REFK
N
N
GENERIC
MARKING DIAGRAM*
XXXX
XXXX
ALYWG
G
1
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= PbFree Package
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
(Note: Microdot may be in either location)
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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