AK4497 Datasheet by AKM Semiconductor Inc.

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AsahiKASEI AKM C. A"
[AK4497]
016003187-E-00 2016/05
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1. General Description
The AK4497 is a new generation Premium 32-bit 2ch DAC with VELVET SOUNDTM technology,
achieving industry’s leading level low distortion characteristics and wide dynamic range. The AK4497
integrates a newly developed switched capacitor filter “OSR Doubler”, making it capable of supporting
wide range signals and achieving low out-of-band noise while realizing low power consumption.
Moreover, the AK4497 has six types of 32-bit digital filters, realizing simple and flexible sound tuning in
wide range of applications. The AK4497 accepts up to 768kHz PCM data and 22.4MHz DSD data, ideal
for a high-resolution audio source playback that are becoming widespread in network audios,
USB-DACs and Car Audio Systems.
Application: AV Receivers, CD/SACD player, Network Audios, USB DACs, USB Headphones, Sound
Plates/Bars, Measurement Equipment, Control Systems, Public Audios (PA), IC-Recorders,
Bluetooth Headphones, HD Audio/Voice Conference Systems
2. Features
THD+N: -116dB
DR, S/N: 131dB (2.6 Vrms Output)
128dB (2 Vrms Output)
256 Times Over Sampling
Sampling Rate: 8kHz 768kHz
32-bit 8x Digital Filter
- Short Delay Sharp Roll-off, GD=6.0/fs,
Ripple: 0.005dB, Attenuation: 100dB
- Short Delay Slow Roll-off, GD=5.0/fs
- Sharp Roll-off
- Slow Roll-off
- Low-dispersion Short Delay Filter
- Super Slow Roll-off
2.8MHz, 5.6MHz, 11.2MHz, 22.4MHz DSD Input Support
- Filter1 (fc=39kHz, 2.8MHz mode), Filter2 (fc=76kHz, 2.8MHz mode)
Digital De-emphasis for 32, 44.1, 48kHz sampling
Soft Mute
Digital Attenuator (255 levels and 0.5dB step + mute)
Mono Mode
External Digital Filter Interface
Audio I/F Format: 24/32 bit MSB justified, 16/20/24/32 bit LSB justified, I2S, DSD, TDM
Master Clock
8kHz ~ 32kHz: 256fs or 384fs or 512fs or 768fs or 1152fs
8kHz ~ 54kHz: 256fs or 384fs or 512fs or 768fs
8kHz ~ 108kHz: 256fs or 384fs
108kHz ~ 216kHz: 128fs or 192fs
~ 384kHz: 32fs or 48fs or 64fs or 96fs
~ 768kHz: 16fs or 32fs or 48fs or 64fs
Power Supply:
TVDD=AVDD= 3.0 3.6V (by Internal LDO), VDDL/R= 4.75 ~ 5.25V
TVDD=AVDD= 1.7 3.6V (by external supply), DVDD=1.7 1.98V,
VDDL/R= 4.75 5.25V
Digital Input Level: CMOS
Package: 64-pin TQFP
AK4497
Quality Oriented 32-Bit 2ch DAC
AsahiKASEl
[AK4497]
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3. Table of Contents
1. General Description ........................................................................................................................ 1
2. Features .......................................................................................................................................... 1
3. Table of Contents ............................................................................................................................ 2
4. Block Diagram ................................................................................................................................. 4
5. Pin Configurations and Functions ................................................................................................... 5
Pin Configurations .............................................................................................................................. 5
Pin Functions ..................................................................................................................................... 6
Handling of Unused Pin ..................................................................................................................... 8
6. Absolute Maximum Ratings .......................................................................................................... 10
7. Recommended Operating Conditions .......................................................................................... 10
8. Electrical Characteristics .............................................................................................................. 11
Analog Characteristics ..................................................................................................................... 11
DSD Mode ........................................................................................................................................ 13
Sharp Roll-Off Filter Characteristics ................................................................................................ 14
Slow Roll-Off Filter Characteristics .................................................................................................. 16
Short Delay Sharp Roll-Off Filter Characteristics ............................................................................ 18
Short Delay Slow Roll-Off Filter Characteristics .............................................................................. 20
Low-dispersion Short Delay Filter Characteristics ........................................................................... 22
DSD Filter Characteristics ................................................................................................................ 24
DC Characteristics ........................................................................................................................... 24
Switching Characteristics ................................................................................................................. 25
Timing Diagram ................................................................................................................................ 30
9. Functional Descriptions................................................................................................................. 35
D/A Conversion Mode (PCM Mode, DSD Mode, EXDP Mode) ...................................................... 37
D/A Conversion Mode Switching Timing ......................................................................................... 37
System Clock ................................................................................................................................... 39
Audio Interface Format .................................................................................................................... 49
Digital Filter ...................................................................................................................................... 61
De-emphasis Filter (PCM Mode) ..................................................................................................... 62
Output Volume (PCM Mode, DSD Mode, EXDF Mode) .................................................................. 62
Gain Adjustment Function (PCM Mode, DSD Mode, EXDF Mode) ................................................ 63
Zero Detection (PCM Mode, DSD Mode, EXDF Mode) .................................................................. 64
L/R Channel Output Signal Select, Phase Inversion Function (PCM Mode, DSD Mode, EXDF Mode)
.............................................................................................................................................................. 65
Sound Quality (PCM Mode, DSD Mode, EXDF Mode) ................................................................... 65
DSD Signal Full Scale (FS) Detection ............................................................................................. 66
Soft Mute Operation (PCM Mode, DSD Mode, EXDF Mode) ......................................................... 68
LDO .................................................................................................................................................. 69
Shutdown Switch .............................................................................................................................. 69
Over Current Protection for Analog Output Pins ............................................................................. 69
Power Up/Down Function ................................................................................................................ 70
Synchronize Function (PCM mode, EXDF mode) ........................................................................... 78
Register Control Interface ................................................................................................................ 80
Register Map .................................................................................................................................... 84
Register Definitions .......................................................................................................................... 86
10. Recommended External Circuits .................................................................................................. 95
11. Package ........................................................................................................................................ 99
Outline Dimensions ........................................................................................................................... 99
Material & Lead Finish ................................................................................................................... 100
Marking ........................................................................................................................................... 100
12. Ordering Guide ........................................................................................................................... 101
AsahiKASEI
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Ordering Guide ............................................................................................................................... 101
13. Revision History .......................................................................................................................... 101
IMPORTANT NOTICE ........................................................................................................................... 102
AsahiKASEI SMUTE'CSN
[AK4497]
016003187-E-00 2016/05
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4. Block Diagram
MCLK
SDATA/DINL/DSDL
SMUTE/CSN
SD/ CCLK/SCL
SLOW/CDTI/SDA
VSSR
VDDR
PDN
AVDD
SCF
SCF
Clock
Divider
DVSS
DVDD
SSLOW/WCK
ACKS/
CAD1
PSN
DIF0/
DZFL
DIF2/
CAD0
VSSL
VDDL
VCML
AOUTRN
VCMR
VREFHL
VREFLL
VREFLR
VREFHR
AVSS
AOUTLP
AOUTLN
AOUTRP
PCM
Data
Interface
DSD
Data
Interface
External
DF
Interface
Control
Register
Vref
LRCK/DINR/DSDR
DIF1/
DZFR
DATT
Soft Mute
Modulator
Volume bypass
DSDD bit 1
Normal path
DSDD bit 0
Oscillator
TVDD
TDM1
DCHAIN
LDO
LDOE
TDM0/DCLK
DEM0/DSDL
GAIN/DSDR
TDMO
INVR
TESTE
HLOAD
/I2C
EXTR
IREF
DSD
Filter
De-emphasis
&
Interpolator
MCLK Detection
Figure 1. Block Diagram
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[AK4497]
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5. Pin Configurations and Functions
Pin Configurations
Figure 2. Pin Configurations
The exposed pad on the bottom surface of the package must be connected to AVSS.
AsahiKASEl
[AK4497]
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Pin Functions
No.
Pin Name
I/O
Function
1
LDOE
I
Internal LDO Enable Pin. “L”: Disable, “H”: Enable
2
PDN
I
Power-Down Mode Pin
When at “L”, the AK4497 is in power-down mode and is held in reset. The
AK4497 must always be reset upon power-up.
3
BICK
I
Audio Serial Data Clock Pin in PCM Mode
BCK
I
Audio Serial Data Clock Pin
DCLK
I
DSD Clock Pin in DSD Mode (DSDPATH bit = “1”)
4
SDATA
I
Audio Serial Data Input Pin in PCM Mode
DINL
I
Lch Audio Serial Data Input Pin
DSDL
I
DSD Lch Data Input Pin in DSD Mode(DSDPATH bit = “1”)
5
LRCK
I
L/R Clock Pin in PCM Mode
DINR
I
Rch Audio Serial Data Input Pin
DSDR
I
DSD Rch Data Input Pin in DSD Mode(DSDPATH bit = “1”)
6
SSLOW
I
Digital Filter Select Pin in Pin Control Mode
WCK
I
Word Clock input pin
7
TDMO
O
Audio Serial Data Output in Daisy Chain mode (Internal pull-down pin)
8
SMUTE
I
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
CSN
I
Chip Select Pin in Register Control Mode
9
SD
I
Digital Filter Select Pin in Pin Control Mode
CCLK
I
Control Data Clock Pin in Register Control Mode
SCL
I
I2C=”H”: Control Data Clock Input Pin
10
SLOW
I
Digital Filter Select Pin in Pin Control Mode
CDTI
I
Control Data Input Pin in Register Control Mode
SDA
I/O
I2C=”H”: Control Data Input Pin
11
DIF0
I
Digital Input Format 0 Pin in Pin Control Mode
DZFL
O
Lch Zero Input Detect Pin in Register Control Mode (Internal pull-down pin)
12
DIF1
I
Digital Input Format 1 Pin in Pin Control Mode
DZFR
O
Rch Zero Input Detect Pin in Register Control Mode (Internal pull-down pin)
13
DIF2
I
Digital Input Format 2 Pin in Pin Control Mode
CAD0
I
Chip Address 0 Pin in Register Control Mode
14
PSN
I
Pin Control Mode or Register Control Mode select Pin (Internal pull-up pin)
“L”: Register Control Mode, “H”: Pin Control Mode
15
HLOAD
I
Heavy Load Mode Enable Pin in Pin Control Mode.
I2C
Resister Control Interface Pin in Register Control Mode.
16
DEM0
I
De-emphasis Enable 0 Pin in Pin Control Mode
DSDL
I
DSD Lch Data Input Pin in DSD Mode (DSDPATH bit =”0”)
17
GAIN
I
Output Gain Control Pin in Pin control mode (+2.5dB)
DSDR
I
DSD Rch Input Pin in DSD Mode (DSDPATH bit =”0”)
18
ACKS
I
Auto Setting Mode Select Pin in Pin control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CAD1
I
Chip Address 1 Pin in Register Control Mode
AsahiKASEl
[AK4497]
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No.
Pin Name
I/O
Function
19
TDM0
I
TDM Mode Select Pin in Pin Control Mode.
DCLK
I
DSD clock Pin in DSD Mode (DSDPATH bit = “0”)
20
TDM1
I
TDM Mode select Pin in Pin Control Mode.
21
DCHAIN
I
Daisy Chain Mode Select Pin in Pin Control Mode.
22
INVR
I
Rch Output Data Invert Enable Pin in Pin Control Mode.
23
TESTE
I
Test Mode Enable Pin. (Internal pull-down pin)
24-26
VREFHR
I
Rch High Level Voltage Reference Input Pin
27-29
VREFLR
I
Rch Low Level Voltage Reference Input Pin
30
VCMR
I
Right Channel Common Voltage Pin,
Normally connected to VREFLR with a 10uF electrolytic cap.
This pin is prohibited to connect other devices.
31,32
AOUTRN
O
Rch Negative Analog Output Pin
33,34
AOUTRP
O
Rch Positive Analog Output Pin
35-37
VDDR
-
Rch Analog Power Supply Pin
38-40
VSSR
-
Analog Ground Pin
41-43
VSSL
-
Analog Ground Pin
44-46
VDDL
-
Lch Analog Power Supply Pin
47,48
AOUTLP
O
Lch Positive Analog Output Pin
49,50
AOUTLN
O
Lch Negative Analog Output Pin
51
VCML
-
Left channel Common Voltage Pin
Normally connected to VREFLL with a 10uF electrolytic cap.
This pin is prohibited to connect other devices.
52-54
VREFLL
I
Lch Low Level Voltage Reference Input Pin
55-57
VREFHL
I
Lch High Level Voltage Reference Input Pin
58
EXTR
I
External Resistor Connect Pin
Rext=33kΩ(±0.1%) to AVSS
59
AVDD
-
(LDOE pin = “H”)
Analog Power Supply Pin, 3.0 3.6V
-
(LDOE pin = “L”)
Analog Power Supply Pin, 1.7 3.6V
60
AVSS
-
Analog Ground Pin
61
MCLK
I
Master Clock Input Pin
62
DVDD
O
(LDOE pin = “H”)
LDO Output Pin,
This pin should be connected to DVSS with 1.F.
This pin is prohibited to connect other devices.
-
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7 1.98V
63
DVSS
-
Digital Ground Pin
64
TVDD
-
(LDOE pin = “H”)
Digital Power Supply Pin, 3.0 3.6V
-
(LDOE pin = “L”)
Digital Power Supply Pin, 1.7 3.6V
Note 1. All input pins except internal pull-up/down pins must not be left floating.
Note 2. The AK4497 must be reset by PDN pin after changing Pin/Register control mode by the PSN pin.
Note 3. PCM mode, DSD mode and EXDF mode are controlled by register settings.
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Handling of Unused Pin
Unused I/O pins must be connected appropriately.
(1) Pin Control Mode (PCM mode only)
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
TESTE
Connect to DVSS or Open
(2) Resister Control Mode
1. PCM Mode
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
TESTE
Connect to DVSS or Open
TDMO, DZFL, DZFR
Open
2. DSD Mode
DSDPATH bit = 0
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
BICK, SDATA, LRCK, WCK, TDM1,
DCHAIN, INVR, TESTE
Connect to DVSS
TESTE
Connect to DVDD or Open
TDMO, DZFL, DZFR
Open
DSDPATH bit = 1
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
DEM0, GAIN, TDM0, WCK, TDM1,
DCHAIN, INVR
Connect to DVSS
TESTE
Connect to DVSS or Open
TDMO, DZFL, DZFR
Open
3. EXDF Mode
Classification
Pin Name
Status
Analog
AOUTLP, AOUTLN
Open
AOUTRP, AOUTRN
Open
Digital
DEM0, GAIN, TDM0, TDM1,
DCHAIN, INVR
Connect to DVSS
TESTE
Connect to DVSS or Open
TDMO, DZFL, DZFR
Open
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4. I2C-Bus Mode
Classification
Pin Name
Status
Digital
CSN
Connect to DVSS
Pull-up and Pull-down pins List
Classification
Pin Name
Status
pull-up pin (typ=100kΩ)
PSN
Connect to TVDD or Open
pull-down pin (typ=100kΩ)
TDMO, DZFL, DZFR, TESTE
Connect to DVSS or Open
AsahiKASEl
[AK4497]
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6. Absolute Maximum Ratings
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4)
Parameter
Symbol
Min.
Max.
Unit
Power
Supplies:
Digital I/O
Digital Core
Clock Interface
Analog
|AVSS DVSS| (Note 5)
TVDDam
DVDDam
AVDDam
VDDL/Ram
GND
0.3
0.3
0.3
0.3
-
4.0
2.5
4.0
6.0
0.3
V
V
V
V
V
Input Current, Any Pin Except Supplies
IIN
-
10
mA
Digital Input Voltage
VIND
0.3
TVDD+0.3
V
Ambient Temperature (Power supplied)
Ta
40
85
C
Storage Temperature
Tstg
65
150
C
Note 4. All voltages with respect to ground.
Note 5. AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. Connect
the exposed pad on the bottom surface of the package to AVSS.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS=VSSL=VSSR=VREFLL=VREFLR=0V; Note 4)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies
LDOE pin= L
Digital I/O
Clock Interface
Digital Core
Analog
LDOE pin= H
Digital I/O
Clock Interface
Analog
TVDD
AVDD
DVDD
VDDL/R
TVDD
AVDD
VDDL/R
DVDD
DVDD
1.7
4.75
3.0
3.0
4.75
1.8
1.8
1.8
5.0
3.3
3.3
5.0
3.6
3.6
1.98
5.25
3.6
3.6
5.25
V
V
V
V
V
V
V
Voltage Reference
(Note 7)
“H” voltage reference
“L” voltage reference
VREFHL/R
VREFLL/R
VDDL/R-0.5
-
-
VSSL/R
VDDL/R
-
V
V
Note 4. All voltages with respect to ground.
Note 6. The analog output voltage scales with the voltage of (VREFHL/R VREFLL/R).
Note 7. TVDD and AVDD must be connected to the same ground plane and powered up at the same time.
When not using the LDO (LDOE pin = L), all power supplies (DVDD (1.8V), TVDD and AVDD
(3.3V) and VDDL/R (5V)) should be powered up at the same time or sequentially in the order of
3.3V (TVDD, AVDD), 1.8V (DVDD) and 5V (VDDL/R).
Note 8. The internal LDO outputs DVDD (1.8V) when the LDOE pin = H. 3.3V (TVDD and AVDD) power
supplies must be powered up before or at the same time with 5V (VDDL/R) power supplies when
the LDOE pin = “H”.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
AsahiKASEl
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8. Electrical Characteristics
Analog Characteristics
(Ta=25C; LDOE pin = L, AVDD=TVDD=3.3V, DVDD=1.8V, AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; BICK=64fs; Signal Frequency = 1kHz;
Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 77;
SC[2:0] bit=000; 2Vrms output mode (GC[2:0] bit=“000” or GAIN pin=“L”); Heavy load drive
mode=off(HLOAD bit=”0” or HLOAD pin=”L”); unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Resolution
-
-
32
Bits
Dynamic Characteristics (Note 9)
THD+N
fs=44.1kHz
BW=20kHz
0dBFS
GC[2:0]= 000” or
GAIN= “L”
-
116
108
dB
GC[2:0]= 100” or
GAIN= “H”
-
113
-
60dBFS
-
65
-
dB
fs=96kHz
BW=40kHz
0dBFS
-
113
-
dB
60dBFS
-
62
-
dB
fs=192kHz
BW=40kHz
0dBFS
-
110
-
dB
60dBFS
-
-62
-
dB
BW=80kHz
60dBFS
-
-59
-
dB
Dynamic Range (60dBFS with A-weighted) (Note 10)
125
128
-
dB
S/N (A-weighted)
(Note 11)
GC[2:0]= 000” or GAIN= “L”
125
128
-
dB
GC[2:0]= 100” or GAIN= “H”
Stereo mode
-
131
-
dB
Mono mode
(Note 17)
-
133
-
Interchannel Isolation (1kHz)
110
120
-
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.15
0.3
dB
Gain Drift (Note 12)
-
20
-
ppm/C
Output
Voltage
GC[2:0] bits=000 or GAIN pin=L (Note 13)
2.65
2.8
2.95
Vpp
GC[2:0] bits=100 or GAIN pin=H (Note 14)
3.55
3.75
3.95
Vpp
Load
Resistance
(Note 15)
HLOAD bit=0 or HLOAD pin=L
8
10
-
k
HLOAD bit=1 or HLOAD pin=H
120
-
-
Load Capacitance (Note 15)
-
-
25
pF
Note 9. Measured by Audio Precision APx555. Averaging mode.
Note 10. 101dB at 16bit data and 118dB at 20bit data.
Note 11. S/N does not depend on the input data size.
Note 12. The voltage on (VREFH VREFL) is held +5V externally.
Note 13. The analog output voltage with 0dBFS input signal when GC[2:0] bits = 000 or the GAIN pin =
L is calculated by the following formula.
AOUTL/R (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFHL/R VREFLL/R)/5.
Note 14. The analog output voltage with 0dBFS input signal when GC[2:0] bits = 100 or the GAIN pin =
H is calculated by the following formula.
AOUTL/R (typ.@0dB) = (AOUT+) (AOUT) = 3.75Vpp (VREFHL/R VREFLL/R)/5.
Note 15. Regarding Load Resistance, AC load is 8k (min) with a DC cut capacitor when HLOAD bit = 0
or the HLOAD pin = L. DC load is 120 (min) without a DC cut capacitor if the HLOAD pin = H.
The load resistance value is with respect to ground. Analog characteristics are sensitive to
capacitive load that is connected to the output pin. Therefore the capacitive load must be
minimized.
Note 16. It is recommended to use a resistor with 0.1% absolute error for the output stage of the adding
circuit.
Note 17. This mode is shown in Figure 78.
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(Ta=25C; AVDD=TVDD=3.3V, DVDD=1.8V(@LDOE pin= “L”), AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; BICK=64fs; Signal Frequency = 1kHz;
Sampling Frequency = 44.1kHz; SC[2:0] bits= 000”); 2Vrms output mode (GC[2:0] bits= “000” or GAIN
pin = “L”); Heavy load drive mode=off (HLOAD bit= “0” or HLOAD pin= “L”); unless otherwise specified.)
Power Supplies
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL/R(total)
64
96
mA
VREFHL/R
1
1.5
mA
AVDD
-
1
1.5
mA
TVDD
LDOE pin = H”
fs= 44.1kHz
8
12
mA
fs= 96kHz
-
13
20
mA
fs = 192kHz
-
20
30
mA
LDOE pin = L”
1
1.5
mA
DVDD
LDOE pin = L”
fs= 44.1kHz
8
12
mA
fs= 96kHz
13
20
mA
fs = 192kHz
20
30
mA
Total Idd per channel (HLOAD pin = “H”)
fs=44.1kHz
45
72
mA/ch
Power down (PDN pin = “L”) (Note 18)
TVDD+AVDD+VDDL/R+DVDD
-
10
100
A
Note 18. In power down mode, the PSN pin = TVDD and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held to DVSS.
Note 19. The DVDD pin becomes an output pin when the LDOE pin = H”.
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DSD Mode
(Ta=25C; AVDD=TVDD=3.3V, DVDD=1.8V (@LDOE pin = L), AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Signal Frequency = 1kHz; Measurement bandwidth = 20Hz
~ 20kHz; External Circuit; Example circuit 3 (Figure 77); SC[2:0] bit=000; 2Vrms output mode (GC[2:0]
bits=“000” or GAIN pin=“L”); Heavy load drive mode=off(HLOAD bit=”0” or HLOAD pin= “L”); unless
otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Dynamic Characteristics
THD+N
(Note 20)
DSD dataStream: 2.8224MHz
0dBFS
-
116
-
dB
DSD dataStream: 5.6448MHz
0dBFS
-
116
-
dB
DSD dataStream: 11.2896MHz
0dBFS
-
116
-
dB
S/N
(A-weighted,
Normal path)
(Note 20)
DSD dataStream: 2.8224MHz
Digital0
(Note 23)
-
128
-
dB
DSD dataStream: 5.6448MHz
Digital0
(Note 23)
-
128
-
dB
DSD dataStream: 11.2896MHz
Digital0
(Note 23)
-
128
-
dB
DC Accuracy
Output Voltage (Normal path) (Note 13)
2.65
2.8
2.95
Vpp
Output Voltage (Volume Bypass) (Note 24)
2.38
2.5
2.63
Vpp
Note 20. Analog characteristics are not guaranteed when the DSD dataStream is 22.5782MHz.
Note 21. The peak level of DSD signal should be in the range of 25% ~ 75% Duty according to the
SACD format book (Scarlet Book).
Note 22. The output level is assumed as 0dB when a 1kHz 25% ~ 75% duty sine wave is input. Click
noise may occur if the input signal exceeds 0dB.
Note 23. Digital “0” is a digital zero code pattern (01101001) according to the SACD format book
(Scarlet Book).
Note 24. When DSDD bit = 1, the analog output voltage with 25 ~ 75% input duty is given by following
formula.
AOUTL/R (typ.@0dB) = (AOUTLP/RP) (AOUTLN/RN) = 2.5Vpp (VREFHL/R
VREFLL/R)/5.0.
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 14 -
Sharp Roll-Off Filter Characteristics
Sharp Roll-Off Filter Characteristics (fs=44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0” or SD pin = L”, SLOW bit=“0” or SLOW pin = L, SSLOQ bit = 0 or
SSLOW pin = L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
-
0
-
22.05
20.0
-
kHz
kHz
Passband (Note 26)
PB
0
20.0
kHz
Stopband (Note 26)
SB
24.1
kHz
Passband Ripple (Note 27)
PR
0.005
dB
Stopband Attenuation (Note 25)
SA
100
dB
Group Delay (Note 28)
GD
-
29.2
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
0.2
-
+0.1
dB
Sharp Roll-Off Filter Characteristics (fs=96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0” or SD pin = L”, SLOW bit=“0” or SLOW pin = L, SSLOW bit = 0 or
SSLOW pin = L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
0
-
48.0
43.5
-
kHz
kHz
Passband (Note 26)
PB
0
43.5
kHz
Stopband (Note 26)
SB
52.5
kHz
Passband Ripple (Note 27)
PR
0.005
dB
Stopband Attenuation (Note 25)
SA
100
dB
Group Delay (Note 28)
GD
-
29.2
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
0.6
-
+0.1
dB
Sharp Roll-Off Filter Characteristics (fs=192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0” or SD pin=L”, SLOW bit=“0” or SLOW pin=L, SSLOW bit=0 or SSLOW pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
96.0
87.0
-
kHz
kHz
Passband (Note 26)
PB
0
87.0
kHz
Stopband (Note 26)
SB
105
kHz
Passband Ripple (Note 27)
PR
0.005
dB
Stopband Attenuation (Note 25)
SA
100
dB
Group Delay (Note 28)
GD
-
29.2
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
2.0
-
+0.1
dB
Note 25. Frequency response refers to the output level (0dB) of a 1kHz, 0dB sine wave input.
Note 26. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@0.01dB),
SB=0.546×fs.
Note 27. The first stage of the Interpolator. This is a passband gain amplitude of the 4 times oversampling
filter.
Note 28. The calculating delay time which occurred by digital filtering. This time is from setting the
16/20/24/32 bit data of both channels to the output of analog signal.
AsahiKASEI Gain [dB 7120 7140 7160 7180 Gain [dB Total Frequency Response \ \ 0.005 0.004 0.003 0.002 D 001 70.001 70.002 70.003 70.004 70.005 48 96 144 192 Frequency lkHl Passhand Ripple (fs=44.1kHz) Frequency lkHz
[AK4497]
016003187-E-00 2016/05
- 15 -
Figure 3. Sharp Roll-off Filter Frequency Response
Figure 4. Sharp Roll-off Filter Passband Ripple
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 16 -
Slow Roll-Off Filter Characteristics
Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“0” or SD pin=L”, SLOW bit=“1” or SLOW pin=H, SSLOW bit=0 or SSLOW
pin=L”)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
-
0
-
-
21.0
8.0
-
kHz
kHz
Passband (Note 29)
PB
0
-
8.0
kHz
Stopband (Note 29)
SB
39.2
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
92
-
-
dB
Group Delay (Note 28)
GD
-
6.5
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
5.0
-
+0.1
dB
Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“0” or SD pin=L”, SLOW bit=“1” or SLOW pin=H, SSLOW bit=0 or SSLOW
pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
PB
0
-
-
45.6
17.6
-
kHz
kHz
Passband (Note 29)
PB
0
-
17.6
kHz
Stopband (Note 29)
SB
85.4
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
92
-
-
dB
Group Delay (Note 28)
GD
-
6.5
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
3.8
-
+0.1
dB
Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“0” or SD pin=L, SLOW bit=“1” or SLOW pin=H, SSLOW bit=0 or SSLOW
pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
91.2
35.2
-
kHz
kHz
Passband (Note 29)
PB
0
-
35.2
kHz
Stopband (Note 29)
SB
170.7
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.5
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
5.0
-
+0.1
dB
Note 29. The passband and stopband frequencies scale with fs. For example, PB = 0.1836 × fs
(@0.01dB), SB = 0.8889 × fs.
AsahiKASEI Total Frequency Response 0 48 96 144 192 Frequency [kHz Passband Ripple (fs=44.1kHz) 0.01 0.005 Gain [dB 70.005 4101 w w w \ Frequency lkHz
[AK4497]
016003187-E-00 2016/05
- 17 -
Figure 5. Slow Roll-off Filter Frequency Response
Figure 6. Slow Roll-off Filter Passband Ripple
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 18 -
Short Delay Sharp Roll-Off Filter Characteristics
Short Delay Sharp Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=H”, SLOW bit=“0” or SLOW bit=L, SSLOW bit=0 or SSLOW
pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
22.05
20.0
-
kHz
kHz
Passband (Note 30)
PB
0
-
20.0
kHz
Stopband (Note 30)
SB
24.1
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
2.0
-
+0.1
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=H”, SLOW bit=“0” or SLOW bit=L, SSLOW bit=0 or SSLOW
pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
48.0
43.5
-
kHz
kHz
Passband (Note 30)
PB
0
-
43.5
kHz
Stopband (Note 30)
SB
52.5
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
6.0
-
+0.1
dB
Short Delay Sharp Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1” or SD pin=H”, SLOW bit=“0” or SLOW bit=L, SSLOW bit=0 or SSLOW pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
96.0
87.0
-
kHz
kHz
Passband (Note 30)
PB
0
-
87.0
kHz
Stopband (Note 30)
SB
104.9
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
6.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
2.0
-
+0.1
dB
Note 30. The passband and stopband frequencies scale with fs. For example, PB=0.4535×fs (@0.01dB),
SB=0.546×fs.
AsahiKASEI Total Frequency Response Gain IdB 0 48 96 144 192 Frequency lkHl Fassband Ripple (fs=44.1kHz) Gain [dB Frequency lkHz
[AK4497]
016003187-E-00 2016/05
- 19 -
Figure 7. Short delay Sharp Roll-off Filter Frequency Response
Figure 8. Short delay Sharp Roll-off Filter Passband Ripple
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 20 -
Short Delay Slow Roll-Off Filter Characteristics
Short Delay Slow Roll-Off Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Normal Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=H”, SLOW bit=“1 or SLOW pin=H, SSLOW bit=0 or SSLOW
pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
21.0
8.0
-
kHz
kHz
Passband (Note 30)
PB
0
-
8.0
kHz
Stopband (Note 30)
SB
39.2
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.007
dB
Stopband Attenuation (Note 25)
SA
92
-
dB
Group Delay (Note 28)
GD
-
5.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
5.0
-
+0.1
dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Double Speed
Mode; DEM=OFF; SD bit=“1” or SD pin=H”, SLOW bit=“1 or SLOW pin=H, SSLOW bit=0 or SSLOW
pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
45.6
17.6
-
kHz
kHz
Passband (Note 30)
PB
0
-
17.6
kHz
Stopband (Note 30)
SB
85.4
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
5.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
3.8
-
+0.1
dB
Short Delay Slow Roll-Off Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.75 5.25V, AVDD= TVDD=1.7 3.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=“1” or SD pin=H, SLOW bit=“1 or SLOW pin=H, SSLOW bit=0 or SSLOW
pin=L)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.01dB
6.0dB
-
-
0
-
-
91.2
35.2
-
kHz
kHz
Passband (Note 30)
PB
0
-
35.2
kHz
Stopband (Note 30)
SB
170.7
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.005
dB
Stopband Attenuation (Note 25)
SA
100
-
-
dB
Group Delay (Note 28)
GD
-
5.0
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
5.0
-
+0.1
dB
Note 31. The passband and stopband frequencies scale with fs. For example, PB = 0.1836 × fs
(@0.01dB), SB = 0.8866 × fs.
AsahiKASEI Total Frequency Response E \ \ E ,100 A u U 7120 7140 7160 . . n 7180 w w w 0 48 96 144 192 Frequency [kHz] Passband Ripple (fs=44.1kHz) 0.01 0.005 Gain [dB 70.005 4101 w w w \ Frequency lkHz
[AK4497]
016003187-E-00 2016/05
- 21 -
Figure 9. Short Delay Slow Roll-off Filter Frequency Response
Figure 10. Short Delay Slow Roll-off Filter Passband Ripple
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 22 -
Low-dispersion Short Delay Filter Characteristics
Low-dispersion Short Delay Filter Characteristics (fs = 44.1kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; Normal Speed Mode
DEM=OFF; SD bit=1 or SD pin =“H, SLOW bit=0 or SLOW pin=“L, SSLOW bit=1 or SSLOW
pin=H)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.05dB
6.0dB
PB
-
0
-
-
22.5
18.4
-
kHz
kHz
Passband (Note 32)
PB
0
-
18.4
kHz
Stopband (Note 32)
SB
25.7
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.05
dB
Stopband Attenuation (Note 25)
SA
80
-
-
dB
Group Delay (Note 28)
GD
-
10.0
-
1/fs
Group Delay Distortion
ΔGD
-
±0.035
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 20.0kHz
0.8
-
+0.1
dB
Low-dispersion Short Delay Filter Characteristics (fs = 96kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; Double Speed Mode;
DEM=OFF; SD bit=1 or SD pin =“H”, SLOW bit=0 or SLOW pin=“L, SSLOW bit=1 or SSLOW
pin=H)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.05dB
6.0dB
PB
0
-
-
48.0
40.1
-
kHz
kHz
Passband (Note 32)
PB
0
-
40.1
kHz
Stopband (Note 32)
SB
55.9
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.05
dB
Stopband Attenuation (Note 25)
SA
80
-
-
dB
Group Delay (Note 28)
GD
-
10.0
-
1/fs
Group Delay Distortion
ΔGD
±0.035
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 40.0kHz
0.6
-
+0.1
dB
Low-dispersion Short Delay Filter Characteristics (fs = 192kHz)
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; Quad Speed Mode;
DEM=OFF; SD bit=1 or SD pin =“H”, SLOW bit=0 or SLOW pin=“L, SSLOW bit=1 or SSLOW
pin=H)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Digital Filter
Frequency Response
(Note 25)
0.05dB
6.0dB
-
-
0
-
-
98.0
80.2
-
kHz
kHz
Passband (Note 32)
PB
0
-
80.2
kHz
Stopband (Note 32)
SB
111.8
-
-
kHz
Passband Ripple (Note 27)
PR
-
-
0.05
dB
Stopband Attenuation (Note 25)
SA
80
-
-
dB
Group Delay (Note 28)
GD
-
10.0
-
1/fs
Group Delay Distortion
ΔGD
-
±0.035
-
1/fs
Digital Filter + SCF (Note 25)
Frequency Response: 0 80.0kHz
2.0
-
+0.1
dB
Note 32. The passband and stopband frequencies scale with fs. For example, PB = 0.418 × fs
(@0.05dB), SB = 0.582 × fs.
AsahiKASEI Total Frequency Response \ \ 40 60 100 7120 7140 7160 7180 0.05 0.04 0.03 0.02 0.01 Gain [dB 70.01 70.02 70.03 70.04 70.05 Frequency/kHz 48 96 144 192 Frequency [kHz] Passband Ripple (fs=44.1kHz) \ w w 5 10 15 20
[AK4497]
016003187-E-00 2016/05
- 23 -
Figure 11. Low Dispersion Short Delay Filter Frequency Response
Figure 12. Low Dispersion Short Delay Filter Passband Ripple
AsahiKASEl H»
[AK4497]
016003187-E-00 2016/05
- 24 -
DSD Filter Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; fs=44.1kHz; DP
bit=“1”, DSDF bit = “0”, DSDSEL[1:0] bits = 00”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response (Note 34)
Frequency Response
(Note 35)
20kHz
-0.77
dB
50kHz
-5.25
dB
100kHz
-18.80
dB
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V; fs=44.1kHz; DP
bit=“1”, DSDF bit=“1”, DSDSEL[1:0] bits= 00”)
Parameter
Min.
Typ.
Max.
Unit
Digital Filter Response (Note 34)
Frequency Response
(Note 35)
20kHz
-0.19
dB
100kHz
-5.29
dB
150kHz
-15.57
dB
Note 33. The peak level of DSD signal should be in the range of 25% ~ 75% duty according to the SACD
format book (Scarlet Book).
Note 34. The frequency response refers to the output level of 0dB when a 1kHz 25%~75% duty sine wave
is input.
Note 35. The frequency (20k, 100k and 200kHz) will be doubled when the sampling speed is 128fs
(DSDSEL[1:0] bits = 01) and it will be quadrupled when the sampling speed is 256fs
(DSDSEL[1:0] bits = 10).
DC Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
AVDD=TVDD= 1.7 3.0V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
80%TVDD
-
-
-
-
20%TVDD
V
V
AVDD=TVDD= 3.0V 3.6V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
70%TVDD
-
-
-
-
30%TVDD
V
V
High-Level Output Voltage
(TDMO, DZFL, DZFR pins: Iout=-100µA)
Low-Level Output Voltage
(except SDA pin: Iout= 100µA)
(SDA pin, 2.0V TVDD 3.6V: Iout= 3mA)
(SDA pin, 1.7V TVDD 2.0V: Iout= 3mA)
VOH
VOL
VOL
VOL
TVDD0.5
-
-
-
-
-
-
-
0.5
0.4
20%TVDD
V
V
V
V
Input Leakage Current (Note 36)
Iin
-
-
10
A
Note 36. The TESTE, TDMO, DIF0 and DIF1 pins have internal pull-down and the PSN pin has internal
pull-up devices. Therefore the TESTE, TDMO, DIF0, DIF1 and PSN pins are not included in this
specification.
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 25 -
Switching Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V, CL=20pF)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
2.048
40
9.155
9.155
-
-
-
-
49.152
60
-
-
MHz
%
nsec
nsec
LRCK Clock Timing (Note 37)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
fsd
fsq
fso
fsh
Duty
8
54
108
-
-
45
-
-
-
384
768
-
54
108
216
-
-
55
kHz
kHz
kHz
kHz
kHz
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
fsd
fsq
tLRH
tLRL
8
54
108
1/128fs
1/128fs
-
-
-
-
-
54
108
216
-
-
kHz
kHz
kHz
nsec
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
fsn
fsd
tLRH
tLRL
8
54
1/256fs
1/256fs
-
-
-
-
54
108
-
-
kHz
kHz
nsec
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time
fsn
tLRH
tLRL
8
1/512fs
1/512fs
-
-
-
54
-
-
kHz
nsec
nsec
Note 37. The MCLK frequency must be changed while the AK4497 is in reset state by setting the PDN pin
= “L” or RSTN bit = “0”.
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 26 -
(Ta=-40~85C; VDDL/R=4.755.25V, AVDD=TVDD=1.73.6V, DVDD=1.7~1.98V, CL=20pF, PSN pin=
L, AFSD bit= "1")
Parameter
Symbol
Min.
Typ.
Max.
Unit
Master Clock Timing (FS Auto Detect Mode)
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
7.68
40
9.155
9.155
-
-
-
-
49.152
60
-
-
MHz
%
nsec
nsec
LRCK Clock Timing (FS Auto Detect Mode) (Note 38)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
Duty Cycle
fsn
fsd
fsq
fso
fsh
Duty
30
88.2
176.4
-
-
45
-
-
-
384
768
-
54
108
216
-
-
55
kHz
kHz
kHz
kHz
kHz
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
fsd
fsq
tLRH
tLRL
30
88.2
176.4
1/128fs
1/128fs
-
-
-
-
-
54
108
216
-
-
kHz
kHz
kHz
nsec
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
Double Speed Mode
High time
Low time
fsn
fsd
tLRH
tLRL
30
-
1/256fs
1/256fs
-
-
-
-
54
108
-
-
kHz
kHz
nsec
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
High time
Low time
fsn
tLRH
tLRL
30
1/512fs
1/512fs
-
-
-
54
-
-
kHz
nsec
nsec
Note 38. Normal operation is not guaranteed if a frequency not shown above is input to the LRCK when
the AK4497 is in Sampling Frequency Auto Detect Mode.
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 27 -
Parameter
Symbol
Min.
Typ.
Max.
Unit
PCM Audio Interface Timing
Normal Mode (TDM[1:0] bits = “00”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
BICK Pulse Width Low
BICK Pulse Width High
BICK to LRCK Edge (Note 39)
LRCK Edge to BICK (Note 39)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/256fsn
1/128fsd
1/64fsq
1/64fso
1/64fsh
9
9
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM128 mode (TDM[1:0] bits = “01”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK to LRCK Edge (Note 39)
LRCK Edge to BICK (Note 39)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/128fsd
1/128fsq
14
14
14
14
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM256 mode (TDM[1:0] bits = “10”)
BICK Period
Normal Speed Mode
Double Speed Mode (Note 40)
BICK Pulse Width Low
BICK Pulse Width High
BICK to LRCK Edge (Note 39)
LRCK Edge to BICK “ (Note 39)
TDMO Setup time BICK “
TDMO Hold time BICK “ (Note 42)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tBSS
tBSH
tSDH
tSDS
1/256fsn
1/256fsd
14
14
14
14
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
TDM512 mode (TDM[1:0] bits = “11”)
BICK Period
Normal Speed Mode (Note 41)
BICK Pulse Width Low
BICK Pulse Width High
BICK to LRCK Edge (Note 39)
LRCK Edge to BICK (Note 39)
TDMO Setup time BICK “
TDMO Hold time BICK “ (Note 42)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tBSS
tBSH
tSDH
tSDS
1/512fsn
14
14
14
14
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Note 39. BICK rising edge must not occur at the same time as LRCK edge.
Note 40. Daisy Chain Mode, fsd (max) = 96 kHz if TVDD < 3.0V.
Note 41. Daisy Chain Mode, fsn (max) = 48 kHz if TVDD < 3.0V.
Note 42. LDOE pin = “L”, tBSH (min) = 4 nsec if TVDD > 2.6V.
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 28 -
Parameter
Symbol
Min.
Typ.
Max.
Unit
PCM Audio Interface Timing
External Digital Filter Mode
BCK Period
BCK Pulse Width Low
BCK Pulse Width High
BCK “” to WCK Edge
WCK Period
WCK Edge to BCK “
WCK Pulse Width Low
WCK Pulse Width High
DINL/R Hold Time
DINL/R Setup Time
tB
tBL
tBH
tBW
tWCK
tWB
tWCKL
tWCKH
tDH
tDS
27
10
10
5
1.3
5
54
54
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
usec
nsec
nsec
nsec
nsec
nsec
DSD Audio Interface Timing
Sampling Frequency
fs
30
48
kHz
(64fs mode, DSDSEL [1:0] bits = “00”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 43)
tDCK
tDCKL
tDCKH
tDDD
-
144
144
20
1/64fs
-
-
-
-
-
-
20
nsec
nsec
nsec
nsec
(128fs mode, DSDSEL [1:0] bits = “01”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 43)
tDCK
tDCKL
tDCKH
tDDD
-
72
72
10
1/128fs
-
-
-
-
-
-
10
nsec
nsec
nsec
nsec
(256fs mode, DSDSEL [1:0] bits = “10”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R (Note 43)
tDCK
tDCKL
tDCKH
tDDD
-
36
36
5
1/256fs
-
-
-
-
-
-
5
nsec
nsec
nsec
nsec
(512fs mode, DSDSEL [1:0] bit = “11”)
DCLK Period
DCLK Pulse Width Low
DCLK Pulse Width High
DSDL/R Setup Time
DSDL/R Hold Time
tDCK
tDCKL
tDCKH
tDDS
tDDH
-
18
18
5
5
1/512fs
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
Note 43. DSD data transmitting device must meet this time. “tDDD is defined from DCLK “↓” until
DSDL/R edge when DCKB bit = 0 (default), tDDD is defined from DCLK “↑” until DSDL/R
edge when DCKB bit = 1. If the audio data format is in phase modulation mode, tDDD is
defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
Note 44. The AK4497 does not support Phase Modulation Mode in DSD512fs Mode.
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 29 -
Parameter
Symbol
Min.
Typ.
Max.
Unit
Control Interface Timing (3-wire IF mode):
CCLK Period
CCLK Pulse Width Low
CCLK Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN ” to CCLK “
CCLK “to CSN
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 45)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
usec
usec
usec
usec
usec
usec
usec
usec
usec
usec
nsec
pF
Power-down & Reset Timing (Note 46)
PDN Accept Pulse Width
PDN Reject Pulse Width
tAPD
tRPD
150
-
-
-
-
30
nsec
nsec
Note 45. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 46. The AK4497 should be reset by bringing the PDN pin “L” upon power-up.
Note 47. I2C -bus is a trademark of NXP B.V.
AsahiKASEI IBCKH [BCKL
[AK4497]
016003187-E-00 2016/05
- 30 -
Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tLRL
tLRH
tBCK
tBCKL
VIH
tBCKH
BICK
VIL
tWCK
tWCKL
VIH
tWCKH
WCK
VIL
tB
tBL
VIH
tBH
BCK
VIL
Figure 13. Clock Timing
[AK4497]
016003187-E-00 2016/05
- 31 -
tLRB
LRCK
VIH
BICK
VIL
TDMO
50%TVDD
tBSS
VIH
VIL
tBLR
tSDS
SDATA
VIH
VIL
tSDH
tBSH
Figure 14. Audio Interface Timing (PCM Mode)
tWB
WCK
VIH
BCK
VIL
tDS
VIH
DINL
DINR
VIL
tDH
VIH
VIL
tBW
Figure 15. Audio Interface Timing (External Digital Filter I/F Mode)
[AK4497]
016003187-E-00 2016/05
- 32 -
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
tDCKH
tDCKL
tDCK
tDDD
VIH
DSDL
DSDR
VIL
DSD Audio Interface Timing (DSD64fs, 128fs, 256fs Mode)
VIH
DCLK
VIL
VIH
DSDL
DSDR
VIL
tDCKH
tDCKL
tDCK
tDDH
tDDS
DSD Audio Interface Timing (DSD512fs Mode)
Figure 16. Audio Interface Timing (DSD Normal Mode, DCKB bit = “0”)
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
tDCKH
tDCKL
tDCK
tDDD
tDDD
VIH
DSDL
DSDR
VIL
tDDD
Figure 17. Audio Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)
[AK4497]
016003187-E-00 2016/05
- 33 -
tCSS
CSN
VIH
CCLK
VIL
VIH
CDTI
VIL
VIH
VIL
C1
C0
R/W
A4
tCCKL
tCCKH
tCDS
tCDH
tCCK
Figure 18. WRITE Command Input Timing
CSN
VIH
CCLK
VIL
VIH
CDTI
VIL
VIH
VIL
D3
D2
D1
D0
tCSW
tCSH
Figure 19. WRITE Data Input Timing
AsahiKASEI
[AK4497]
016003187-E-00 2016/05
- 34 -
tHIGH
SCL
SDA
VIH
tLOW
tBUF
tHD:STA
tR
tF
tHD:DAT
tSU:DAT
tSU:STA
Stop
Start
Start
Stop
tSU:STO
VIL
VIH
VIL
tSP
Figure 20. I2C Bus Mode Timing
tAPD
tRPD
PDN VIL
Figure 21. Power Down & Reset Timing
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 35 -
9. Functional Descriptions
Each function of the AK4497 is controlled by Pins (pin control mode) and Registers (register control
mode) (Table 1). Select the control mode by setting the PSN pin. The AK4497 must be powered down
when changing the PSN pin setting. There is a possibility of malfunction if the device is not powered down
when changing the control mode since the previous setting is not initialized. Register settings are invalid
in pin control mode, and pin settings are invalid in register control mode.
Table 2 shows available functions of each control mode and Table 3 shows available functions in
PCM/DSD/EXDF mode.
Table 1. Pin/Register Control Mode Select
PSN pin
Control Mode
L
Register Control Mode
H
Pin Control Mode
Table 2. Function List @Pin/Register Control Mode
Function
Pin Control Mode
Register Control
Mode
DSD/EXDF Mode Select
-
Y
System Clock Setting Select
Y
Y
Audio Format Select
Y
Y
TDM Mode
Y
Y
Digital Filter Select
Y
Y
De-emphasis Filter Select
Y
Y
Digital Attenuator
-
Y
Zero Detection
-
Y
Mono Mode
-
Y
Output signal select
(Monaural, Channel select)
-
Y
Output signal polarity select
(Invert)
Y
Y
Sound Color Select
-
Y
DSD Full Scale Detect
-
Y
Soft Mute
Y
Y
Register Reset
-
Y
Synchronization
-
Y
Resistor Control
-
Y
Gain Control
Y
Y
Heavy Load Mode
Y
Y
(Y: Available, -: Not available)
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 36 -
Table 3. Function List of PCM/EXDF/DSD mode @Register Control Mode
Function
Default
Add
Bit
PCM
EXDF
DSD
PCM/DSD/EXDF Mode Select
PCM mode
00H
02H
EXDF
DP
Y
Y
Y
System clock setting @DSD mode
512fs
02H
DCKS
-
-
Y
System clock setting @EXDF mode
16fs(fs=44.1kHz)
00H
ECS
-
Y
-
Digital Filter select @DSD mode
39kHz filter
09H
DSDF
-
-
Y
Digital Filter select @PCM mode
Short delay
sharp roll off
filter
01-02-05H
SD
SLOW
SSLOW
Y
-
-
De-emphasis Response
OFF
01H
DEM[1:0]
Y
-
-
Path select @ DSD mode
Normal Path
06H
DSDD
-
-
Y
Audio Data Interface Format
@ PCM Mode
32bit MSB
00H
DIF[2:0]
Y
-
-
Audio Data Interface Format
@ EXDF Mode
32bit LSB
00H
DIF[2:0]
-
Y
-
TDM Interface Format
Normal Mode
0AH
TDM[1:0]
Y
-
-
Daisy Chain
Normal Mode
0BH
DCHAIN
Y
-
-
Attenuation Level
0dB
03-04H
ATT[7:0]
Y
Y
Y
Data Zero Detect Enable
Disable
01H
DZFE
Y
Y
Y
Inverting Enable of DZF
“H” active
02H
DZFB
Y
Y
Y
Mono/Stereo mode select
Stereo
02H
MONO
Y
Y
Y
Data Invert mode select
OFF
05H
INVL/R
Y
Y
Y
The data selection of L channel and
R channel
R channel
02H
SELLR
Y
Y
Y
Sound Color Select
Off
08H
SC[2:0]
Y
Y
Y
DSD Mute Function @ Full scale
Detected
Disable
06H
DDM
-
-
Y
Soft Mute Enable
Normal
Operation
01H
SMUTE
Y
Y
Y
RSTN
Reset
00H
RSTN
Y
Y
Y
Synchronization
Enable
07H
SYNCE
Y
Y
-
(Y: Available, N/A: Not available)
AsahiKASEI s.— PCM or EXDF Mode PCM or EXDF Data / DSD Data DSD Mode
[AK4497]
016003187-E-00 2016/05
- 37 -
D/A Conversion Mode (PCM Mode, DSD Mode, EXDP Mode)
The AK4497 can perform D/A conversion for either PCM data or DSD data. The DP bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from the #16, #17 and #19 pins if DSDPATH
bit = 0 and DSD data can be input from the #3, #4, and #5 pins if DSDPATH bit = 1. The AK4497 must
be reset by setting RSTN bit = 0 when PSM/DSD mode is changed by DP bit or when DSD signal input
pins are changed by DSDPATH bit. It takes about 2 ~ 3/fs to change the mode. Wait 4/fs or more to
change RSTN bit after changing these settings.
When the AK4497 is in pin control mode, PCM mode is only available. External digital filter I/F can be
selected by setting DP bit = 0 and EXDF bit = 1. When using an external digital filter (EXDF I/F mode),
data is input to each MCLK, BCK, WCK, DINL and DINR pin. EXDF bit controls the modes. When
switching internal and external digital filters by EXDF bit, the AK4497 must be reset by RSTN bit. A Digital
filter switching takes 2~3k/fs. The AK4497 is in DSD mode when DP bit = 1 and EXDF bit 1.
Table 4. PCM/DSD/EXDF Mode Control
DP bit
EXDF bit
DSDPATH
bit
D/A Conv.
Mode
Pin Assignment
#3 pin
#4 pin
#5 pin
#16 pin
#17 pin
#19 pin
0
(default)
0
(default)
x
PCM
BICK
SDATA
LRCK
Not Use
Not Use
Not Use
1
x
0
(default)
DSD
Not Use
Not Use
Not Use
DSDL
DSDR
DCLK
1
x
1
DSD
DCLK
DSDL
DSDR
Not Use
Not Use
Not Use
0
1
x
EXDF
BCK
DINL
DINR
Not Use
Not Use
Not Use
(x: Do not care)
D/A Conversion Mode Switching Timing
Figure 22 and Figure 23 show switching timing of PCM/EXDF and DSD modes. To prevent noise caused
by excessive input, DSD signal should be input 4/fs after setting RSTN bit = 0 until the device is
completely reset internally when the conversion mode is changed to DSD mode from PCM/ESDF mode.
DSD signal should be stopped 4/fs after setting RSTN bit = 0until the device is completely reset
internally when the conversion mode is changed to PCM/EXDE from DSD mode.
RSTN bit
D/A Data
D/A Mode
4/fs
0
PCM or EXDF Data
DSD Data
PCM or EXDF Mode
DSD Mode
Figure 22. D/A Mode Switching Timing (from PCM/EXDF to DSD)
AsahiKASEI POM or EXDF Mode POM or EXDF Mode X PCM or EXDF Mode /—
[AK4497]
016003187-E-00 2016/05
- 38 -
RSTN bit
D/A Data
D/A Mode
4/fs
DSD Data
PCM Data or EXDF Data
DSD Mode
PCM or EXDF Mode
4/fs
0
Figure 23. D/A Mode Switching Timing (from DSD/PCM or EXDF)
Figure 24 shows switching timing of PCM and EXDF modes. Set EXDF bit 4/fs after setting RSTN bit =
0 until the device is completely reset internally when changing the conversion mode.
RSTN bit
D/A Data
D/A Mode
4/fs
PCM or EXDF Data
PCM or EXDF Data
PCM or EXDF Mode
PCM or EXDF Mode
0
Figure 24. D/A Mode Switching Timing (PCM EXDF)
AsahiKASEI
[AK4497]
016003187-E-00 2016/05
- 39 -
System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4497, are MCLK, BICK and LRCK. MCLK, BICK
and LRCK should be synchronized but the phase is not critical. The MCLK is used to operate the digital
interpolation filter, the delta-sigma modulator and SCF.
There are Manual Setting Mode, Auto Setting Mode and Fs Auto Detection mode for MCLK frequency
setting. In manual setting mode (ACKS pin=L or ACKS bit=0), MCLK frequency is set automatically but
the sampling speed (LRCK frequency) is set by DFS[2:0] bits (Table 6). Sampling frequency is fixed to
normal speed mode in pin control mode (PSN pin = H), and it is set by DFS[2:0] bits in register control
mode (PSN pin = L). In register control mode, the AK4497 is in manual setting mode when power-down
is released (PDN pin = L H).
In auto setting mode (ACKS pin = “H” or ACKS bit=“1”), sampling speed and MCLK frequency are
detected automatically (Table 7, Table 11) and then the initial master clock is set to the appropriate
frequency (Table 8, Table 15, Table 16).
In FS auto detect mode (AFSD bit= 1), sampling speed is automatically detected (Table 7, Table 11)
and the initial master clock is set to the appropriate frequency. In this mode, ACKS bit and DFS[2:0] bits
settings are invalid. Fs auto detect mode is not supported by pin control mode.
The AK4497 is automatically placed in power-down state when MCLK is stopped for more than 1us
during a normal operation (PDN pin =H), and the analog output becomes Hi-z state. When MCLK is
input again, the AK4497 exits power-down state and starts operation. The AK4497 is in power-down
mode until MCLK BICK and LRCK are supplied and the analog output is floating state.
Table 5. System Clock Setting Mode @Register Control Mode
AFSD bit
ACKS bit
Mode
0
0
Manual setting Mode
(default)
1
Auto setting Mode
1
x
FS Auto Detect Mode
(x: Do not care)
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 40 -
(1) Pin Control Mode (PSN pin = “H”)
(1)-1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 6).
DFS1-0 bits are fixed to 00. In this mode, quad speed and double speed modes are not available.
Table 6. System Clock Example (Manual Setting Mode @Pin Control Mode)
LRCK
MCLK (MHz)
BICK
fs
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
64fs
32.0kHz
N/A
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
2.0480MHz
44.1kHz
N/A
N/A
11.2896
16.9344
22.5792
33.8688
N/A
2.8224MHz
48.0kHz
N/A
N/A
12.2880
18.4320
24.5760
36.8640
N/A
3.0720MHz
(N/A: Not available)
(1)-2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically (Table 7).
MCLK of corresponded frequency to each sampling speed mode should be input externally (Table 8).
Table 7. Sampling Speed (Auto Setting Mode @Pin Control Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512fs/256fs
768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 8. System Clock Example (Auto Setting Mode @Pin Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
Fs
32fs
48fs
64fs
96fs
128fs
192fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
22.5792
33.8688
Quad
192.0kHz
N/A
N/A
N/A
N/A
24.5760
36.8640
384kHz
N/A
N/A
24.576
36.864
N/A
N/A
Oct
768kHz
24.576
36.864
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 41 -
Table 9. System Clock Example 2 (Auto Setting Mode @Pin Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
Fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0kHz
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
Normal
44.1kHz
11.2896
16.9344
22.5792
33.8688
N/A
N/A
48.0kHz
12.2880
18.4320
24.5760
36.8640
N/A
N/A
88.2kHz
22.5792
33.8688
N/A
N/A
N/A
N/A
Double
96.0kHz
24.5760
36.8640
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 8kHz~96kHz (Table 10).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 10. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS pin
MCLK
DR,S/N
(A-weighted)
L
256fs/384fs/512fs/768fs
128dB
H
256fs/384fs
125dB
H
512fs/768fs
128dB
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 42 -
(2) Register Control Mode (PSN pin = “L”)
(2)-1. Manual Setting Mode (AFSD bit=“0”, ACKS bit=“0”)
MCLK frequency is detected automatically and the sampling speed is set by DFS[2:0] bits (Table 11). The
MCLK frequency corresponding to each sampling speed that should be provided externally (Table 12,
Table 14). The AK4497 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When DFS2-0
bits are changed, the AK4497 should be reset by RSTN bit.
Table 11. Sampling Speed (Manual Setting Mode @Register Control Mode)
DFS2
bit
DFS1
bit
DFS0
bit
Sampling Rate (fs)
0
0
0
Normal Speed Mode
8kHz 54kHz
(default)
0
0
1
Double Speed Mode
54kHz 108kHz
0
1
0
Quad Speed Mode
120kHz 216kHz
0
1
1
Quad Speed Mode
120kHz 216kHz
1
0
0
Oct Speed Mode
384kHz
1
0
1
Hex Speed Mode
768kHz
1
1
0
Oct Speed Mode
384kHz
1
1
1
Hex Speed Mode
768kHz
Table 12. System Clock Example 1 (Manual Setting Mode @Register Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
Fs
16fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
N/A
24.5760
384kHz
N/A
12.288
18.432
24.576
36.864
N/A
Oct
768kHz
12.288
24.576
36.864
49.152
N/A
N/A
Hex
(N/A: Not available)
Table 13. System Clock Example 2 (Manual Setting Mode @Register Control Mode)
LRCK
MCLK(MHz)
Sampling
Speed
fs
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
Normal
44.1kHz
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
48.0kHz
N/A
12.2880
18.4320
24.5760
36.8640
N/A
N/A
88.2kHz
N/A
22.5792
33.8688
45.1584
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760
36.8640
49.152
N/A
N/A
N/A
176.4kHz
33.8688
45.1584
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
49.152
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 43 -
(2)-2. Auto Setting Mode (AFSD bit= “0”, ACKS bit = “1”)
MCLK frequency and the sampling speed are detected automatically (Table 14) and DFS[2:0] bits are
ignored. The MCLK frequency corresponding to each sampling speed should be provided externally
(Table 15, Table 16).
Table 14. Sampling Speed (Auto Setting Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512fs/256fs
768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
Table 15. System Clock Example (Auto Setting Mode)
LRCK
MCLK(MHz)
Sampling Speed
fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
24.5760
384kHz
N/A
N/A
24.576
36.864
N/A
Oct
768kHz
24.576
36.864
N/A
N/A
N/A
Hex
(N/A: Not available)
Table 16. System Clock Example (Auto Setting Mode)
LRCK
MCLK(MHz)
Sampling Speed
fs
192fs
256fs
384fs
512fs
768fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840
24.5760
36.8640
Normal
44.1kHz
N/A
11.2896
16.9344
22.5792
33.8688
N/A
48.0kHz
N/A
12.2880
18.4320
24.5760
36.8640
N/A
88.2kHz
N/A
22.5792
33.8688
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760
36.8640
N/A
N/A
N/A
176.4kHz
33.8688
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
When MCLK= 256fs/384fs, auto setting mode supports sampling rate from 8kHz to 96kHz (Table 14).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 17. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS bit
MCLK
DR, S/N
(A-weighted)
0
256fs/384fs/512fs/768fs
128dB
1
256fs/384fs
125dB
1
512fs/768fs
128dB
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 44 -
(2)-3. Sampling Frequency (FS) Auto Detect Mode (AFSD bit= “1”)
MCLK frequency and the sampling rate is detected automatically (Table 14). In this mode, DFS[2:0] bits
and ACKS bit settings are invalid. The MCLK frequency corresponding to each sampling speed should
be provided externally (Table 18, Table 19). Internal operation sequence in FS auto detect mode is
shown in Figure 25.
Table 18. System Clock Example 1 @PCM Mode
LRCK
MCLK(MHz)
Sampling
Speed
Fs
16fs
32fs
48fs
64fs
96fs
128fs
32.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
Normal
44.1kHz
N/A
N/A
N/A
N/A
N/A
N/A
48.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
88.2kHz
N/A
N/A
N/A
N/A
N/A
N/A
Double
96.0kHz
N/A
N/A
N/A
N/A
N/A
N/A
176.4kHz
N/A
N/A
N/A
N/A
N/A
22.5792
Quad
192.0kHz
N/A
N/A
N/A
N/A
N/A
24.5760
384kHz
N/A
12.288
18.432
24.576
36.864
N/A
Oct
768kHz
12.288
24.576
36.864
49.152
N/A
N/A
Hex
(N/A: Not available)
Table 19. System Clock Example 2 @PCM Mode
LRCK
MCLK(MHz)
Sampling
Speed
fs
192fs
256fs
384fs
512fs
768fs
1024fs
1152fs
32.0kHz
N/A
8.1920
12.2880
16.3840
24.5760
32.768
36.8640
Normal
44.1kHz
N/A
11.2896
16.9344
22.5792
33.8688
N/A
N/A
48.0kHz
N/A
12.2880
18.4320
24.5760
36.8640
N/A
N/A
88.2kHz
N/A
22.5792
33.8688
45.1584
N/A
N/A
N/A
Double
96.0kHz
N/A
24.5760
36.8640
49.152
N/A
N/A
N/A
176.4kHz
33.8688
45.1584
N/A
N/A
N/A
N/A
N/A
Quad
192.0kHz
36.8640
49.152
N/A
N/A
N/A
N/A
N/A
384kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
768kHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hex
(N/A: Not available)
AsahiKASEI Power Up Mode FS AmoDelect Mode
[AK4497]
016003187-E-00 2016/05
- 45 -
(2)-4. FS Auto Detect Mode Enable
Figure 25 and Figure 26 show system timing when switching to FS Auto Detect Mode.
<Switching to FS Auto Detect Mode>
AFSD bit
8~9/fs
ClockSetting
Mode
Manual or Auto SettingMode
FS AutoDetect Mode
(2)
Internal
ClockSetting
ClockSetting Fix
(3)
RSTN bit
(1)
Internal OSC
Power Up
InternalState
(DigitalCore)
Normal Operation
Normal Operation
2~3/fs
3~4/fs
0
2~3/fs
Figure 25. Switching to FS AutoDetect Mode
Notes:
(1) Digital block of the AK4497 should be reset when changing the clock setting mode. Refer to
Figure 57 and Figure 58 for power up sequence.
(2) The internal oscillator starts operation by setting AFSD bit= “1”. It takes 10us (max.) until the
internal oscillator is stabilized.
(3) FS auto detect mode starts in 8/fs ~ 9/fs after setting AFSD bit= “1”. Internal operation rate will be
stabilized in 2/fs ~ 3/fs. Digital block should be reset state until the internal operation rate is
stabilized.
AsahiKASEI E 3~4/fs 3 L—ui Power UD :\ Mode FSAutoDeleclMode >§< manual="" or="" autosettinq="" mode="">
[AK4497]
016003187-E-00 2016/05
- 46 -
<Switching to Other Clock Setting Mode from FS Auto Detect Mode>
RSTN bit
AFSD bit
ClockSetting
Mode
FSAutoDetectMode
Manual or Autosetting Mode
Internal OSC
Power Up
3~4/fs
2~3/fs
InternalState
(DigitalCore)
Normal Operation
Normal Operation
0
(1)
4/fs
Figure 26. Switching from FS AutoDetect Mode
Note:
(1) FS auto detect mode ends by setting AFSD bit = “0” and the internal oscillator will stop operation.
AsahiKASEl DSDD Mode
[AK4497]
016003187-E-00 2016/05
- 47 -
[2] DSD Mode
The AK4497 has a DSD playback function. The external clocks that are required in DSD mode are MCLK
and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of
MCLK is set by DCKS bit (Table 20).
The AK4497 is automatically placed in power-down state when MCLK is stopped during a normal
operation (PDN pin =H), and the analog output becomes Hi-z state. When the reset is released (PDN
pin = L H), the AK4497 is in power-down state until MCLK and DCLK are input.
Table 20. System Clock (DSD Mode, fs=32kHz, 44.1kHz, 48kHz)
DCKS bit
MCLK Frequency
DCLK Frequency
0
512fs
64fs/128fs/256fs
(default)
1
768fs
64fs/128fs/256fs
The AK4497 supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs), 11.2896MHz (256fs)
and 22.5792MHz (512fs). The data sampling speed is selected by DSDSEL[1:0] bits (Table 21).
Table 21. DSD Data Stream Select
DSDSEL1
DSDSEL0
DSD Data Stream
fs=32kHz
fs=44.1kHz
fs=48kHz
0
0
2.048MHz
2.8224MHz
3.072MHz
(default)
0
1
4.096MHz
5.6448MHz
6.144MHz
1
0
8.192MHz
11.2896MHz
12.288MHz
1
1
16.284MHz
22.5792MHz
24.576MHz
The AK4497 has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit (Table 22). When setting DSDD bit = 1, the output volume control and zero detect functions
are not available.
Table 22. DSD Playback Path Select
DSDD
Mode
0
Normal Path
(default)
1
Volume Bypass
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 48 -
[3] External Digital Filter Mode (EXDF mode)
The external clocks that are required in EXDF mode are MCLK, BCK and WCK. The BCK and MCLK
clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each sampling
speed are shown in Table 23. ECS bit selects WCK frequency from 384kHz and 768kHz. DW indicates
the number of BCK in one WCK cycle.
All circuits except the internal LDO are automatically placed in power-down state when MCLK edge is not
detected for more than 1us during a normal operation (PDN pin =H), and the analog output becomes
Hi-Z state. The power-down state is released and the AK4497 starts operation by inputting MCLK again.
In this case, register settings are not initialized.
When the reset is released (PDN pin = L H), the AK4497 is in power-down state until MCLK, BCK
and WCK are input.
Table 23. System Clock Example (EXDF mode)
Sampling
Speed[kHz]
MCLK&BCK [MHz]
WCK
ECS
128fs
192fs
256fs
384fs
512fs
768fs
44.1(30~48)
N/A
N/A
N/A
N/A
22.5792
33.8688
16fs
0
(default)
32
48
DW
44.1(30~48)
N/A
N/A
11.2896
16.9344
22.5792
33.8688
8fs
1
32
48
64
96
DW
96(54~96)
N/A
N/A
24.576
36.864
N/A
N/A
8fs
0
32
48
DW
96(54~96)
12.288
18.432
24.576
36.864
N/A
N/A
4fs
1
32
48
64
96
DW
192(108~192)
24.576
36.864
N/A
N/A
N/A
N/A
4fs
0
32
48
DW
192(108~192)
24.576
36.864
N/A
N/A
N/A
N/A
2fs
1
64
96
DW
AsahiKASEI
[AK4497]
016003187-E-00 2016/05
- 49 -
Audio Interface Format
[1] PCM mode
(1) Input Data Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported and
selected by the DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table
24. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of
BICK. Mode 2 can be used for 20-bit and 16-bit MSB justified formats by zeroing the unused LSBs.
Normal Mode (TDM[1:0] bits = “00” or TDM1-0 pins = LL)
2ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Eight data formats are supported
and selected by the DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in
Table 24. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge
of BICK. Mode 6 can be used for 24-bit, 20-bit and 16-bit MSB justified formats by zeroing the unused
LSBs.
TDM128 Mode (TDM[1:0] bits = “01” or TDM1-0 pins = LH)
4ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 25). BICK is fixed to 128fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 24. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM256 Mode (TDM[1:0] bits =“10” or TDM1-0 pins =“HL)
8ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 25). BICK is fixed to 256fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 24. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
TDM512 Mode (TDM[1:0] bits = “11” or TDM1-0 pins = HH)
16ch Data is shifted in via the SDATA pin using BICK and LRCK inputs. Data slot can be selected by
SDS[2:0] bits (Table 25). BICK is fixed to 512fs. Six data formats are supported and selected by the
DIF2-0 pins (Pin control mode) or DIF[2:0] bits (Register control mode) as shown in Table 24. In all
formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 50 -
Table 24. Audio Interface Format
Mode
TDM1
bit
TDM0
bit
DIF2
bit
DIF1
bit
DIF0
bit
SDATA Format
LRCK
BICK
Figure
Normal
(Note 48)
0
0
0
0
0
0
16-bit LSB justified
H/L
32fs
Figure 27
1
0
0
1
20-bit LSB justified
H/L
40fs
Figure 28
2
0
1
0
24-bit MSB justified
H/L
48fs
Figure 29
3
0
1
1
16-bit I2S Compatible
L/H
32fs
Figure 30
24-bit I2S Compatible
L/H
48fs
4
1
0
0
24-bit LSB justified
H/L
48fs
Figure 28
5
1
0
1
32-bit LSB justified
H/L
64fs
Figure 31
6
1
1
0
32-bit MSB justified
H/L
64fs
Figure 32
(default)
7
1
1
1
32-bit I2S Compatible
L/H
64fs
Figure 33
TDM128
8
0
1
0
1
0
24-bit MSB justified
H/L
128fs
Figure 34
9
0
1
1
24-bit I2S Compatible
L/H
128fs
Figure 35
10
1
0
0
24-bit LSB justified
H/L
128fs
Figure 36
11
1
0
1
32-bit LSB justified
H/L
128fs
Figure 34
12
1
1
0
32-bit MSB justified
H/L
128fs
Figure 34
13
1
1
1
32-bit I2S Compatible
L/H
128fs
Figure 35
TDM256
14
1
0
0
1
0
24-bit MSB justified
H/L
256fs
Figure 37
15
0
1
1
24-bit I2S Compatible
L/H
256fs
Figure 38
16
1
0
0
24-bit LSB justified
H/L
256fs
Figure 39
17
1
0
1
32-bit LSB justified
H/L
256fs
Figure 37
18
1
1
0
32-bit MSB justified
H/L
256fs
Figure 37
19
1
1
1
32-bit I2S Compatible
L/H
256fs
Figure 38
TDM512
20
1
1
0
1
0
24-bit MSB justified
H/L
512fs
Figure 40
21
0
1
1
24-bit I2S Compatible
L/H
512fs
Figure 41
22
1
0
0
24-bit LSB justified
H/L
512fs
Figure 42
23
1
0
1
32-bit LSB justified
H/L
512fs
Figure 40
24
1
1
0
32-bit MSB justified
H/L
512fs
Figure 40
25
1
1
1
32-bit I2S Compatible
L/H
512fs
Figure 41
Note 48. BICK more than setting bit must be input to each channel. In the LRCK column, H/L indicates that
L channel data can be input when LRCK is H and R channel data can be input when LRCK is L.
L/H indicates L channel data can be input when LRCK is L and R channel data can be input
when LRCK is H.
AsahiKASEI LRCK BICK (32$) SDATA Mode 0 BICK (SAWS) SDATA Mode 0 BICK (64fs) SDATA Mode 1 SDATA Mode 4 LRCK BICK (64fs) SDATA Ufgfffffffffg[IIIIIIII 4 ? a a _ s / , a FJIZIIIIIZ/jIIZIIIIIQ/jff Z Z. FWJHUgJMZ’JHngM 2 ‘ ¢ % Z a Z a ‘ Z ‘ Z ‘ UMflJJMHJgJMMU I é i 2 ‘
[AK4497]
016003187-E-00 2016/05
- 51 -
SDATA
BICK
LRCK
SDATA
15
14
6
5
4
BICK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
3
2
1
0
15
14
(32fs)
(64fs)
0
14
1
15
16
17
31
0
1
14
15
16
17
31
0
1
15
14
0
15
14
0
Mode 0
Dont care
Dont care
15:MSB, 0:LSB
Mode 0
15
14
6
5
4
3
2
1
0
Lch Data
Rch Data
Figure 27. Mode 0 Timing
SDATA
LRCK
BICK
(64fs)
0
9
1
10
11
12
31
0
1
9
10
11
12
31
0
1
19
0
19
0
Mode 1
Dont care
Dont care
19:MSB, 0:LSB
SDATA
Mode 4
23:MSB, 0:LSB
20
19
0
20
19
0
Dont care
Dont care
22
21
22
21
Lch Data
Rch Data
8
23
23
8
Figure 28. Mode 1, 4 Timing
LRCK
BICK
(64fs)
SDATA
0
22
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Dont care
23
Lch Data
Rch Data
23
30
22
2
24
23
30
22
1
0
Dont care
23
22
23
Figure 29. Mode 2 Timing
AsahiKASEI WIIJV/ffffszffljiffféflfff / - I i I i ‘ W217i 9 . y 2 3 4/ 3 whim/mm M/tlIM/GZEE ‘ ‘ : ‘ . >14 >5 ‘ . ‘ . \‘ \\\\\ 3 \‘ \\\\\ 5;? E \\ \\\\ ./ “.1... J—I—1_ 9 9 a9 31 30 5 ‘2 H ‘0 gm Z 31 30 12 H ‘0 ’m g :IV I 7 IA so 234’ mmmflmmmmm 3|‘30‘/|20‘I§‘15‘/ S E 1‘1'0 3||30‘/ 201918 /-:;‘| DE s<>< ~:="" .="">
[AK4497]
016003187-E-00 2016/05
- 52 -
LRCK
BICK
(64fs)
SDATA
0
3
1
2
24
31
0
1
31
0
1
23:MSB, 0:LSB
22
1
0
Dont care
23
Lch Data
Rch Data
23
25
3
2
24
23
25
22
1
0
Dont care
23
23
Figure 30. Mode 3 Timing
LRCK
BICK(128fs)
SDATA
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
1
0
31
1
BICK(64fs)
SDATA
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
31
1
30
9
31
30
20
19
18
9
31
20
19
18
31: MSB, 0:LSB
8
0
1
8
0
1
Lch Data
Rch Data
0
31
1
Figure 31. Mode 5 Timing
LRCK
BICK(128fs)
SDATA
0
1
2
20
21
22
32
33
63
0
1
2
20
21
22
32
33
63
0
31
1
30
0
31
30
12
11
10
0
31
12
11
10
BICK(64fs)
SDATA
0
1
2
12
13
14
23
24
31
0
1
2
12
13
14
23
24
31
0
31
1
30
9
31
30
20
19
18
9
31
20
19
18
31: MSB, 0:LSB
8
0
1
8
0
1
Lch Data
Rch Data
Figure 32. Mode 6 Timing
AsahiKASEI ¥WE4 W zW’fl mmmmrm WW . \0 SW/‘WWI/H | VI2 \ \0 “WMMWIIH | \2l2 \ \0 \\\\\\ \\\\\ i4 >i< v:="" .="" .="" 11%|="" d="" i="" :="" i="" 7777777777777777="" .="" .="" i="" i="" .="" __________="" .="" :="" i="" m="" 30="" fm="" an="" h="" :="" u="" no="" ‘="" .="" .="" .="" :="" ‘="" -="" -="" .="" i="" flaiiitl="" fishiiti="" 3="" 1="" h="" llm="" i="" ‘="" .5="">
[AK4497]
016003187-E-00 2016/05
- 53 -
LRCK
BICK(128fs)
SDATA
0
1
2
20
21
22
33
34
63
0
1
2
20
21
22
33
34
63
0
1
31
0
31
13
12
11
0
13
12
11
BICK(64fs)
SDATA
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
0
1
31
9
0
31
21
20
19
9
0
21
20
19
31: MSB, 0:LSB
8
1
2
8
1
2
Lch Data
Rch Data
Figure 33. Mode 7 Timing
LRCK
BICK(128fs)
128 BICK
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
SDATA
22
0
22
0
23
23
22
23
Mode8
SDATA
30
0
30
0
31
31
30
31
Mode11,12
Figure 34. Mode 8/11/12 Timing
LRCK
BICK(128fs)
128 BICK
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
SDATA
22
0
22
0
23
23
23
SDATA
Mode9
Mode13
30
0
30
0
31
31
30
31
Figure 35. Mode 9/13 Timing
AsahiKASEI 3" 77777777 3—3" 77777777 T! 3 5E3 'MmMmMmMmMmMmMmMmm Im HTI f f : m WIWZZD ' ' TI .33||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||UH MJflML‘EMJflMJflMmMmMJflMMflf 33313—3173 3 3 3 3 3—3 mm in f—TJJ WNMMJ MMMMMHMMMMMMH WUWU i i 1 i 1 ED
[AK4497]
016003187-E-00 2016/05
- 54 -
LRCK
BICK(128fs)
128 BICK
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
SDATA
22
0
22
0
23
23
23
Figure 36. Mode 10 Timing
23
LRCK
BICK (256fs)
22
0
L1
32 BICK
256 BICK
22
0
R1
32 BICK
22
23
23
32 BICK
32 BICK
SDATA
31
30
0
30
31
31
30
0
SDATA
Mode14
Mode17,18
32 BICK
32 BICK
32 BICK
32 BICK
Figure 37. Mode 14/17/18 Timing
LRCK
BICK (256fs)
23
0
L1
32 BICK
256 BICK
23
0
R1
32 BICK
23
32 BICK
32 BICK
SDATA
Mode15
31
0
31
30
31
0
30
SDATA
Mode19
32 BICK
32 BICK
32 BICK
32 BICK
Figure 38. Mode 15/19 Timing
LRCK
BICK(256fs)
SDATA
256 BICK
22
0
L1
32 BICK
22
0
R1
32 BICK
32 BICK
32 BICK
23
23
23
32 BICK
32 BICK
32 BICK
32 BICK
Figure 39. Mode 16 Timing
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[AK4497]
016003187-E-00 2016/05
- 55 -
BICK(512fs)
SDATA
Mode8
LRCK
512BICK
22
2
0
23
22
0
23
SDATA
Mode11,12
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
22
0
31
23
22
0
31
31
Figure 40. Mode 20/23/24 Timing
BICK(512fs)
SDATA
Mode21
LRCK
512BICK
22
2
0
23
22
0
23
SDATA
Mode25
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
22
0
31
23
22
0
31
31
Figure 41. Mode 21/25 Timing
BICK(512fs)
SDATA
Mode22
LRCK
512BICK
22
2
0
23
22
0
23
L1
32 BICK
R1
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 42. Mode 22 Timing
AsahiKASEI L JIIHIIHIIHIIH|||\‘IIIHIIHIIHIIHII\IIHIIHIIHIIH|||\|||\IIIIHIIHIIHIIHIIHI1r
[AK4497]
016003187-E-00 2016/05
- 56 -
(2) Data Slot Selection Function
Data slot of 1cycle LRCK for each audio data format is defined as Figure 43~ Figure 46. DAC output data
can be selected by SDS[2:0] bits as shown in Table 25.
LRCK
SDATA
R1
L1
Figure 43. Data Slot in Normal Mode
SDATA
R1
L1
LRCK
128 BICK
R2
L2
Figure 44. Data Slot in TDM128 Mode
SDATA
R1
L1
LRCK
256 BICK
R2
L2
R3
L3
R4
L4
Figure 45. Data Slot in TDM256 Mode
SDATA
R1
L1
LRCK
512 BICK
R2
L2
R3
L3
R4
L4
R5
R6
L6
R7
L7
R8
L8
L5
Figure 46. Data Slot in TDM512 Mode
AsahiKASEl
[AK4497]
016003187-E-00 2016/05
- 57 -
Table 25. Data Select
SDS2
bit
SDS1
bit
SDS0
bit
DAC
Lch
Rch
Normal
x
x
x
L1
R1
(default)
TDM128
x
x
0
L1
R1
x
x
1
L2
R2
TDM256
x
0
0
L1
R1
x
0
1
L2
R2
x
1
0